CN109787605B

CN109787605B - Logic circuit

Info

Publication number: CN109787605B
Application number: CN201811613400.4A
Authority: CN
Inventors: 施薛优; 陈光毅
Original assignee: Beijing Anku Zhixin Technology Co ltd
Current assignee: Beijing Anku Zhixin Technology Co ltd
Priority date: 2018-12-27
Filing date: 2018-12-27
Publication date: 2023-05-09
Anticipated expiration: 2038-12-27
Also published as: CN109787605A

Abstract

The invention discloses a logic circuit, and relates to the technical field of logic circuit design. The logic circuit at least comprises a row selection logic circuit and a protection logic circuit; the row selection logic circuit comprises M row sub-row selection logic circuits; all the sub-row selection logic circuits are connected in series through OR gates contained in the sub-row selection logic circuits, and a row gating serial electric signal is output; wherein M is a natural number and M is more than or equal to 2; the protection logic circuit determines the state of the row selection logic circuit at least according to the received row strobe serial electric signal, and when the row selection logic circuit has an error state, the protection operation is triggered. By adopting the technical scheme of the invention, the row selection logic circuit can finish progressive scanning operation; the protection logic is capable of triggering a protection operation when an error condition occurs in the row select logic.

Description

Logic circuit

Technical Field

The invention relates to the technical field of logic circuit design, in particular to a logic circuit.

Background

In the prior art, an array image sensor sequentially scans and gates pixels of each row, namely, scans row by row; the selected row is read out and the unselected row is not operated, which is called row selection; however, during the row selection process, the sensor may fail for some reasons (for example, the power-on time is too long or the frame period is too short, which may cause the circuit to be burned out), and once the row selection timing error causes the power-on time to be longer, the temperature of the sensor may be rapidly increased by combining with the joule effect of the sensor, and the sensor may be burned out. Therefore, it is urgent to design a circuit capable of effectively protecting a row selection circuit when an error state occurs in the row selection process.

Disclosure of Invention

In order to solve the problems existing in the prior art, the embodiment of the invention provides a logic circuit.

A logic circuit at least comprises a row selection logic circuit and a protection logic circuit;

the row selection logic circuit comprises M row sub-row selection logic circuits; all the sub-row selection logic circuits are connected in series through OR gates contained in the sub-row selection logic circuits, and a row gating serial electric signal is output; wherein M is a natural number and M is more than or equal to 2;

the protection logic circuit determines the state of the row selection logic circuit at least according to the received row strobe serial electric signal, and when the row selection logic circuit has an error state, the protection operation is triggered.

The sub-row select logic circuit includes: a row selection control signal end and an OR gate;

one input end of the OR gate in the sub-row selection logic circuit is the row selection control signal end; the other input end of the OR gate contained in the M-th row sub-row selection logic circuit is VSS, and the other input end of the OR gate contained in the 1 st row-M-1 st row sub-row selection logic circuit is connected with the output end of the OR gate contained in the next row sub-row selection logic circuit; and the output end of the OR gate in the 1 st row sub-row selection logic circuit outputs the row strobe serial electric signal.

The row selection control signal end comprises a D trigger, a delay unit and an AND gate; the D trigger in the row selection control signal end is connected with a row selection clock signal input end and an asynchronous reset signal input end; the D trigger in each sub-row selection logic circuit is connected with the row selection signal input end of the last row except that the D trigger in the 1 st row sub-row selection logic circuit is connected with the row selection start pulse signal input end.

The protection logic circuit comprises a first sub-protection logic circuit;

the first sub-protection logic circuit comprises two inverters, an OR gate, a MOS tube, a current source, a capacitor, a comparator and a D trigger, and receives the row strobe electrical signal; the device is used for monitoring the row selection time according to the row strobe electrical signal; and if the row selection time exceeds the preset time, triggering the protection operation.

The first sub-protection logic circuit receives the row strobe serial electric signal, performs OR operation with a row strobe start pulse signal as the input of an OR gate of the first sub-protection logic circuit after passing through a first phase inverter, and outputs a result to be connected with the grid electrode of the MOS tube; when the MOS tube is disconnected, the current source charges the capacitor, and the capacitor voltage increases along with the line selection time; if the row selection time exceeds the preset time, the value of the capacitor voltage is larger than the value of the reference voltage, and the comparator is caused to overturn; when the D trigger detects that the clock signal is changed from low to high, an output result is obtained through a second inverter to reset and protect the row selection logic circuit, and the protection operation is triggered.

The protection logic circuit further comprises a second sub-protection logic circuit;

the second sub-protection logic circuit comprises a third inverter, a NOR gate and two triggers, and is used for monitoring a row selection frame period of the row selection logic circuit; and if the row selection frame period is smaller than a preset period, triggering the protection operation.

The line selection frame period is smaller than a preset period, and the triggering of the protection operation specifically comprises the following steps: and when the second sub-protection logic circuit receives a next row selection start pulse signal before the end of a normal row selection period, the second sub-protection logic circuit triggers the protection operation.

The row selection signal output end, the first trigger output end and the third inverter output end are used as three input ends of the NOR gate; the output signal of the NOR gate is used as the input signal of the second trigger; and when the second trigger is set, outputting an electric signal for resetting and protecting the row selection logic circuit, and triggering the protection operation.

When the row selection frame period is smaller than a preset period, the row selection signal outputs a low level, the first trigger is in a set state and outputs a low level, the row selection start pulse signal passes through the third inverter and then outputs a low level, and the output signal of the NOR gate is a high level; and the second trigger is in a set state, outputs an electric signal for resetting and protecting the row selection logic circuit, and triggers the protection operation.

The protection logic circuit further comprises an AND gate; the output end of the second inverter in the first sub protection logic circuit and the output end of the second trigger in the second sub protection logic circuit are used as the input ends of the AND gate.

The beneficial effects of the invention are as follows: the invention discloses a logic circuit, which at least comprises a row selection logic circuit and a protection logic circuit; wherein the row selection logic is capable of performing a progressive scan operation; the protection logic is capable of triggering a protection operation when an error condition occurs in the row select logic.

Drawings

For a clearer description of embodiments of the invention or of solutions in the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained from them without inventive effort for a person skilled in the art.

FIG. 1 is a block diagram of a logic circuit of the present disclosure;

FIG. 2 is a schematic diagram of a logic circuit according to the present disclosure;

FIG. 3 is a schematic diagram of a sub-row select logic circuit according to the present disclosure;

FIG. 4 is a timing diagram 4 of an embodiment of the present invention;

FIG. 5 is a timing diagram 5 of an embodiment of the present invention;

fig. 6 is a timing diagram 6 of an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In one embodiment of the present invention, as shown in the block diagram of fig. 1, a logic circuit includes at least a row selection logic circuit 1 and a protection logic circuit 2;

in general, when an array image sensor reads out, pixels of each row are scanned and gated in sequence, namely, a row-by-row scanning process is performed on the rows, the selected row is read out and the unselected row is not operated, and the process is called row selection; the row selection logic circuit 1 is used for completing sequential progressive scanning operation;

the protection logic 2 is used for preventing the reset operation of the row selection logic 1 when the row selection logic 1 fails due to some reasons (such as self circuit error, external interference, external power failure, etc.), and aims to prevent the bad effect of hardware damage caused by too long time that a certain pixel is gated.

Preferably, the basic workflow of the row selection logic 1 and the protection logic 2 is as follows: the row selection logic circuit 1 in the idle state enters a row selection scanning state after receiving a row selection starting signal; after the row selection is completed, the row selection logic circuit 1 returns to an idle state and waits for receiving a next row selection starting signal; if an error occurs in the row selection process (such as a dangerous condition that the circuit may be burned out, for example, when the power-on time is too long or the frame period is too short), the protection logic circuit 2 judges the error state and triggers protection, so that the row selection logic circuit 1 is asynchronously reset to an idle state.

As shown in fig. 2, a specific circuit diagram of the row selection logic circuit 1 and the protection logic circuit 2 is shown.

As shown in fig. 3, the row selection logic circuit 1 includes M row sub-row selection logic circuits 11, and each row sub-row selection logic circuit 11 includes a row selection control signal terminal and an or gate; one input terminal of the or gate in each row sub-row selection logic circuit 11 is a row strobe electrical signal (RSEL < M:1 >) output from the row selection control signal terminal; the other input end of the OR gate contained in the M-th row sub-row selection logic circuit 11 is VSS, and the other input end of the OR gate contained in the 1-th row sub-M-1-th row sub-row selection logic circuit 11 is connected with the output end of the OR gate of the next row sub-row selection logic circuit 11; the output end of the OR gate in the first row sub-row selection logic circuit 11 finally leads out an electric signal OR <1>, and is connected with the protection logic circuit 2; wherein M is a natural number and M is more than or equal to 2;

specifically, the row selection control signal end comprises a D trigger (DFF), a delay unit and an AND gate, and the output end of the AND gate outputs row strobe electric signals (RSEL < M:1 >); the row selection control signal end in each stage of row selection logic circuit 1 is connected with the input end of a row selection clock signal (RowCLK) and the input end of an asynchronous reset signal (RowRST_L), and the rest row selection logic circuits 11 are connected with the row selection signal (SELd < M >) input of the last row selection logic circuit 11 except that the first row selection logic circuit 11 is connected with the input end of a row selection start pulse signal (PreSEL); wherein the row strobe signal is active high, typically RSEL indicates that the ith row is strobed; the line selection starting pulse signal controls the line selection logic circuit 1 to enter a line selection state through high-level pulse, and each frame line selection (a normal line selection period) needs a line selection starting pulse signal; the asynchronous reset signal is effective at low level, and resets the whole row selection logic circuit 1 when the asynchronous reset signal is at low level; OR is a row strobe series electrical signal representing the result of the row select signal of the i-th row and the OR signal of the i+1-th row passing through one OR gate;

more specifically, the row strobe series electrical signal OR <1> =rsel <1> +or <2> (where "+" represents OR logic, the following); OR <2> = RSEL <2> + OR <3>; it is easy to see that OR <1> =rsel <1> +rsel <2> +or <3>; OR <3> = RSEL <3> + OR <4>; … …; OR = RSEL + OR < i+1>; … …; OR < M > =rsel < M > + VSS (0) =rsel < M >; therefore, OR <1> =rsel <1> +rsel <2> + … … RSEL + … … +rsel < M >; since the row strobe signal is inactive except for the RSEL signal in the row select ith row, the OR <1> signal outputs the RSEL signal of the ith row being row selected to the protection logic 2.

For the row selection logic circuit 1, only one OR gate is needed for each row to finish the introduction of the row strobe serial electric signal into the protection logic circuit 2; for the protection logic 2, only one row strobe serial electric signal (OR <1 >) is needed to be introduced to complete the protection of the row strobe logic 1, thereby effectively reducing the hardware cost.

As shown in fig. 2, the protection logic circuit 2 includes a first sub protection logic circuit 21, a second sub protection logic circuit 22, and a three-input and gate 23, which is configured to determine an error state and trigger protection when an error occurs in the row selection logic circuit 1 during the row selection process, and asynchronously reset the row selection logic circuit 1 to an idle state.

Specifically, the first sub-protection logic circuit 21 is composed of 2 inverters, or gates, MOS transistors, current sources, capacitors, comparators and D flip-flops, and is configured to monitor the row selection time, and if the row selection time exceeds a preset time, output an electrical signal for resetting and protecting the row selection logic circuit 1, so as to prevent the row selection logic circuit 1 from being burnt due to the overlong row selection time.

More specifically, an output signal OR <1> of the row selection logic circuit 1 passes through the first phase inverter and then performs OR operation with a row selection start pulse signal as an input end of the OR gate to obtain an output result PD, wherein the PD is connected with the grid electrode of the MOS tube; when the MOS tube is disconnected, the current source (Iref) charges the capacitor (Cint), and the voltage (Vint) on the capacitor increases along with the line selection time; if the row selection time is too long and exceeds the preset time, the value of the voltage Vint is larger than the reference voltage Vref, so that the comparator is turned over, and at the moment, the HIT pulse signal output by the comparator is changed from low to high; the HIT pulse signal is used as a clock signal (CLK) of a D flip-flop, and after the D flip-flop detects a clock rising edge, the D flip-flop outputs a result Q, and the Q is connected with the three-input and gate 23 after passing through the second inverter; if RowRST_L is low, an asynchronous reset is triggered to perform the row select logic 1 protection operation. As shown in timing 4 shown in fig. 4, the capacitor is charged during the period of T0-T1; the time T1 is preset row selection time; after T1 time, RSEL row selection time is too long, so that the value of the voltage Vint is larger than the reference voltage Vref, and the comparator turns over to generate HIT pulse signals; at this point the trigger protection logic RSEL is reset to low.

If the row select time is normal, there is no time overlap for each row strobe signal, as shown in the timing diagram 5 of FIG. 5, at time T1, there is no time of signal overlap between RSEL <1> and RSEL <2 >. Therefore, when the rows are switched, all row strobe signals in the row selection logic circuit 1 are 0, at the moment, the MOS tube is conducted, the capacitor is short-circuited, the charge on the capacitor is cleared, the voltage Vint is reset, and the row selection time of the next row is prepared for monitoring;

it should be noted that, the row selection time used when the value of the capacitor voltage Vint is equal to the value of the reference voltage Vref is a preset time.

Assuming that the i-th row is being selected in the row selection logic circuit 1, when RSEL is at a high level (i.e., RSEL =1), the OR <1> output is RSEL , i.e., OR <1> =rsel =1; since PreSEL is low during row select (i.e., presel=0); the output signal OR <1> of the row selection logic circuit 1 is subjected to an OR operation by using the inverter and the row selection start pulse signal (PreSEL) as the input end of the OR gate to obtain a result PD, namely pd= -OR <1> +presel=0 (in this embodiment, the inversion is represented by-); when pd=0, the MOS switch is turned off, the D flip-flop outputs q=d=vdd=1 (the detailed process of outputting the result Q is described in detail above and is not repeated here), q=1 is q=0 after passing through an inverter, and the q=1 is connected to the three-input and gate, so that rowrst_l becomes 0, triggering asynchronous reset, and performing protection operation; if the i-th row has normal row selection time, when switching to the next row (i.e., i+1 row), RSEL < i+1> is low (i.e., RSEL < i+1> =0), then OR <1> outputs RSEL < i+1>, i.e., OR <1> =rsel < i+1> =0; then pd= -OR <1> + presel=1, when pd=1, the MOS switch is turned on, ready for i+1th row selection time monitoring;

specifically, the second sub protection logic circuit 22 includes a third inverter, an and gate, a nor gate, and two flip-flops, and is configured to detect a row selection frame period, trigger a reset protection if the row selection frame period is less than a preset period, and output an electrical signal for resetting the row selection logic circuit 1.

In general, a PreSEL starts a normal line selection period, and after all M lines should be selected in the normal line selection period, the next normal line selection period is entered; one normal row selection period is referred to as a row selection frame period.

The row selection frame period is smaller than the preset period, specifically, when the row selection operation of all M rows is not completed in a normal row selection period, the next PreSEL is received.

The trigger in the embodiment is a synchronous setting and synchronous zero clearing trigger, and the execution function is that when the clock rising edge triggers, the trigger is SET when SET=1, and the output-Q=0; clr=1, and q=1.

More specifically, in a normal row selection period, a frame row selection is started by PreSEL, preSEL is connected to SET of the first flip-flop, and flip-flop is SET when PreSEL is equal to 1, i.e., outputs s1= -q=0; before a normal row selection period is not finished, a row selection signal (SELd < M >) of the last row of the normal row selection period is low level, a clock signal (CLR) of a first trigger is always 0, the trigger is not cleared all the time, and is always in a set state, namely s1=0; when the next PreSEL is received before the end of a normal row selection period, the PreSEL is connected to the three-input nor gate after passing through the third inverter, and at this time, the three inputs of the three-input nor gate are: s1=0, -presel=0, seld < m > =0, the output result of the nor gate is 1; the output result of the nor gate is used as a SET signal of a second trigger, the second trigger is SET, s2= -q=0 is output, the rowrst_l is low level through the three-input and gate 23, and asynchronous reset is triggered to perform the protection operation of the row selection logic circuit 1; as shown in the timing diagram 6 of fig. 6, at time T3, preSEL arrives before SELd < M > is valid, triggering a reset;

in this embodiment, the next PreSEL is received only when the line selection frame period is normal, i.e., during the last line selection period or the end of the last line selection period.

Alternatively, if the next PreSEL is received after the last row selection, SELd < M > will go high when the row selection reaches the last row, at which point PreSEL is 0; after passing through an inverter and SELd < M >, the first trigger is cleared to zero with the output result of 1, the second trigger is not set after the zero clearing is carried out, the S1 is connected to a three-input NOR gate with the output result of 0, and the reset protection is not triggered after the zero clearing is carried out, and the S2 = 1; as shown in the timing diagram 6 of fig. 6, at time T1, preSEL arrives after SELd < M > is valid, without triggering a reset;

optionally, if the next PreSEL is received between the last row selection, SELd < M > =1, SELd < M > is connected to the three-input nor gate, the output result is 0, the second flip-flop is not set, s2=1, and the reset protection is not triggered; as shown in the timing diagram 6 of fig. 6, at time T2, preSEL arrives when SELd < M > is valid, without triggering a reset;

in the present embodiment, the three inputs of the three-input and gate 23 in the protection logic circuit 2 are respectively: the D flip-flop Q in the first sub protection logic circuit 21 passes through the electric signal of the inverter, S2 and rst_l output from the second sub protection logic circuit 22.

The embodiment discloses a logic circuit, which at least comprises a row selection logic circuit and a protection logic circuit; wherein the row selection logic is capable of performing a progressive scan operation; the protection logic is capable of triggering a protection operation when an error condition occurs in the row select logic.

The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims

1. A logic circuit, characterized in that it comprises at least a row selection logic circuit and a protection logic circuit;

the protection logic circuit determines the state of the row selection logic circuit at least according to the received row strobe serial electric signal, and when the row selection logic circuit has an error state, the protection operation is triggered;

the protection logic circuit comprises a first sub protection logic circuit and a second sub protection logic circuit;

the first sub-protection logic circuit comprises two inverters, an OR gate, a MOS tube, a current source, a capacitor, a comparator and a D trigger, and receives the row strobe serial electric signal; the device is used for monitoring row selection time according to the row strobe serial electric signal; if the line selection time exceeds the preset time, triggering the protection operation;

the first sub-protection logic circuit receives the row strobe serial electric signal, performs OR operation with a row strobe start pulse signal as the input of an OR gate of the first sub-protection logic circuit after passing through a first phase inverter, and outputs a result to be connected with the grid electrode of the MOS tube; when the MOS tube is disconnected, the current source charges the capacitor, and the capacitor voltage increases along with the line selection time; if the row selection time exceeds the preset time, the value of the capacitor voltage is larger than the value of the reference voltage, and the comparator is caused to overturn; when the D trigger detects that the clock signal is changed from low to high, an output result is obtained through a second inverter to reset and protect the row selection logic circuit, and the protection operation is triggered;

the second sub-protection logic circuit comprises a third inverter, a NOR gate and two triggers, wherein a row selection signal output end, a first trigger output end and a third inverter output end are used as three input ends of the NOR gate; the output signal of the NOR gate is used as the input signal of the second trigger; when the second trigger is set, outputting an electric signal for resetting and protecting the row selection logic circuit, and triggering the protection operation;

the protection logic circuit further comprises an AND gate;

the output end of the second inverter in the first sub protection logic circuit and the output end of the second trigger in the second sub protection logic circuit are used as the input ends of the AND gate.

2. The logic circuit of claim 1, wherein the sub-row select logic circuit comprises: a row selection control signal end and an OR gate;

one input end of the OR gate in the sub-row selection logic circuit is an output end of the row selection control signal end; the other input end of the OR gate contained in the M-th row sub-row selection logic circuit is VSS, and the other input end of the OR gate contained in the 1 st row-M-1 st row sub-row selection logic circuit is connected with the output end of the OR gate contained in the next row sub-row selection logic circuit; and the output end of the OR gate in the 1 st row sub-row selection logic circuit outputs the row strobe serial electric signal.

3. The logic circuit according to claim 2, wherein the row select control signal terminal comprises a D flip-flop, a delay cell, and an and gate; the input end of the D trigger in the row selection control signal end is connected with a row selection clock signal and an asynchronous reset signal; the input ends of the D triggers in the sub-row selection logic circuits except the 1 st row are connected with row selection start pulse signals, and the input ends of the D triggers in the rest sub-row selection logic circuits are also connected with row selection signals of the previous row.

4. The logic circuit according to claim 1, wherein,

the second sub-protection logic circuit is used for monitoring a row selection frame period of the row selection logic circuit; and if the row selection frame period is smaller than a preset period, triggering the protection operation.

5. The logic circuit according to claim 4, wherein the row selection frame period is less than a predetermined period, the triggering of the protection operation is specifically: and when the second sub-protection logic circuit receives a next row selection start pulse signal before the end of a normal row selection period, the second sub-protection logic circuit triggers the protection operation.

6. The logic circuit according to claim 4, wherein when the row selection frame period is less than a preset period, the row selection signal output terminal outputs a low level, the first flip-flop is in a set state to output a low level, the row selection start pulse signal passes through the third inverter to output a low level, and the output signal of the nor gate is a high level; and the second trigger is in a set state, outputs an electric signal for resetting and protecting the row selection logic circuit, and triggers the protection operation.