CN109787602B - Floating level field effect transistor or transistor driving circuit based on coupling capacitor - Google Patents
Floating level field effect transistor or transistor driving circuit based on coupling capacitor Download PDFInfo
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- CN109787602B CN109787602B CN201811601147.0A CN201811601147A CN109787602B CN 109787602 B CN109787602 B CN 109787602B CN 201811601147 A CN201811601147 A CN 201811601147A CN 109787602 B CN109787602 B CN 109787602B
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Abstract
The invention discloses a floating level field effect transistor or transistor driving circuit based on a coupling capacitor, which comprises a FET driving circuit and a BJT driving circuit; the FET driving circuit comprises n groups of FETs, n coupling capacitors and n resistors, wherein each group of FETs comprises at least one FET; the sources of the group of FETs are at the same level; for the ith group of FETs: the switch signal terminal is connected with the gate of each FET of the group through a coupling capacitor Ci, and is connected with the source of the FET through a resistor Ri; i is a natural number from 1 to n. The BJT drive circuit comprises n groups of BJTs, wherein each group of BJTs comprises at least one BJT; the emitters of the BJTs in the same level; for the ith group of BJTs: the switch signal terminal is connected with the base of each BJT of the group through a coupling capacitor Ci ', and the switch signal terminal is connected with the emitter of the BJT through a resistor Ri'.
Description
Technical Field
The invention belongs to the technical field of electronic information engineering and electrical engineering, and particularly relates to a floating level field effect transistor or transistor driving circuit based on a coupling capacitor.
Background
In the fields of switching power supplies, signal processing, etc., it is necessary to use a switching signal (which may be a square wave, a PWM wave, etc.) to control the on and off of the MOSFET, BJT, etc. at other levels, so it is desirable that the driving signal can cross different levels.
The conventional method for solving the problem of transistor driving adopts a charge pump or a special driving chip, and has the disadvantages of complex circuit and high cost, so a simple and low-cost level-crossing driving scheme is required.
Disclosure of Invention
In view of the shortcomings of the prior art, the present invention provides a coupling capacitance based floating level FET or BJT driving circuit.
The invention adopts the following specific technical scheme:
the invention of this patent is to provide a floating level field effect transistor or transistor drive circuit based on coupling capacitance, including FET drive circuit and BJT drive circuit; wherein:
the FET drive circuit includes n groups of FETs, each group of FETs including at least one FET; for the ith group of FETs: a switching signal terminal is connected with the gate of each FET of the group through a coupling capacitor Ci, and the switching signal terminal is connected with the source of each FET through a resistor Ri; i is a natural number from 1 to n;
the selection method aiming at the coupling capacitor comprises the following steps:
labeling a coupling capacitance between the i-th group of FETs and the switch signal terminal as Ci;
first, the gate-source capacitance C of each FET in the FET group corresponding to the coupling capacitance Ci is found from the FET manual GS-ij ；
Then, the coupling capacitance Ci corresponding to the i-th group of FETs satisfies the following equation:
wherein: m is a unit of i The number of the i-th group of FETs;
the selection method aiming at the voltage-dividing resistor comprises the following steps:
the voltage dividing resistance between the i-th group of FETs and the switching signal terminal is labeled Ri; the period of the switching signal is marked T S (ii) a The maximum time of adaptation level is denoted T V ；T V Greater than 10 times T S (ii) a Resistance R i The value range of (A) is as follows:
the BJT driving circuit comprises n groups of BJTs, and each group of BJTs comprises at least one BJT; for the ith group of BJTs: a switching signal terminal is connected with the base of each BJT of the group through a coupling capacitor Ci ', and the switching signal terminal is connected with the emitter of each BJT through a resistor Ri'; i is a natural number from 1 to n;
the selection method aiming at the coupling capacitor comprises the following steps:
marking a coupling capacitance between the ith group of BJTs and the switch signal terminal as Ci';
marking the base current of the jth BJT of the group of BJTs corresponding to the coupling capacitor Ci' as I according to the current mark consumed when the transistor is started B-ij (ii) a The period of the switching signal is T S ', the value range of the coupling capacitance Ci' is
Wherein: m is a unit of i The number of the ith group of BJTs;
the selection method aiming at the resistance comprises the following steps:
marking a resistance between an emitter of the ith group of BJTs and a switch signal terminal as Ri'; the period of the switching signal is marked T S '; the maximum time of adaptation level is denoted T V '; resistance R i The value range of' is:
further: the source electrode of each FET is connected with the grid electrode of the FET through a voltage regulator tube; each coupling capacitor Ci is connected to the gate of the FET via a current limiting resistor.
The invention has the advantages and positive effects that:
by adopting the technical scheme, the driving control of a plurality of FETs and BJTs at different levels is realized by using the coupling capacitor, and the circuit structure is simplified. The method is suitable for the fields of low-power switching power supplies, battery pack equalization circuits and the like, saves the cost, reduces the circuit complexity and reduces the power consumption compared with the traditional mode of using a special driving chip.
Drawings
FIG. 1 is a circuit diagram of a first embodiment of an FET driver circuit of the present invention;
FIG. 2 is a circuit diagram of a second embodiment of the FET driver circuit of the present invention;
FIG. 3 shows a BJT driving circuit of the present invention;
Detailed Description
In order to further understand the contents, features and effects of the present invention, the following embodiments are illustrated and described in detail with reference to the accompanying drawings.
The structure of the present invention will be described in detail below with reference to the accompanying drawings.
Please refer to fig. 1 to 3: a floating level field effect transistor or transistor drive circuit based on coupling capacitance comprises a FET drive circuit and a BJT drive circuit; wherein:
as shown in fig. 1: the FET drive circuit includes n groups of FETs, each group of FETs including at least one FET; for the ith group of FETs: the sources of the FETs of the group are at a uniform level; a switching signal terminal is connected to the gate of each FET of the group via a coupling capacitor Ci, said switching signal terminal being connected to the source of the FET via a resistor Ri; i is a natural number from 1 to n;
the selection method aiming at the capacitance value of the coupling capacitor comprises the following steps:
labeling the coupling capacitance between the gates of the ith group of FETs and the switched signal terminal as Ci;
first, the gate-source capacitance C of each FET in the FET group corresponding to the coupling capacitance Ci is found from the FET manual GS-ij ；
Then, the coupling capacitance Ci corresponding to the i-th group of FETs satisfies the following equation:
wherein: m is i The number of the i-th group of FETs;
the selection method for the voltage-dividing resistor comprises the following steps:
the resistance between the source of the i-th group of FETs and the switch signal terminal is labeled Ri; the period of the switching signal is marked T S (ii) a The maximum time of adaptation level is denoted T V ；T V Greater than 10 times T S (ii) a Resistance R i The value range is as follows:
in addition, a current limiting resistor and a voltage regulator tube can be added to the topology of the FET driving circuit, as shown in FIG. 2.
As shown in fig. 3: the BJT drive circuit comprises n groups of BJTs, and each group of BJTs comprises at least one BJT; for the ith group of BJTs: the emission stages of the BJTs of the group are at a uniform level; a switching signal terminal is connected with a base of each BJT of the group through a coupling capacitor Ci ', and the switching signal terminal is connected with an emitter of the BJT through a resistor Ri'; i is a natural number from 1 to n;
the selection method aiming at the coupling capacitor comprises the following steps:
marking a coupling capacitance between the ith group of BJTs and the switch signal terminal as Ci';
marking the base current of the jth BJT of the group of BJTs corresponding to the coupling capacitor Ci' as I according to the current mark consumed when the transistor is started B-ij (ii) a The period of the switching signal is T S ', the value range of the coupling capacitance Ci' is
m i The number of the ith group of BJTs;
the selection method aiming at the voltage-dividing resistor comprises the following steps:
marking the resistance between the emitters of the BJT in the ith group and the switch signal terminal as Ri'; the period of the switching signal is marked T S '; the maximum time for adapting the level is denoted T V '; resistance R i The value range of' is:
the design process of the above circuit is explained in detail below:
first, the design method for the driving circuit of the FET includes the steps of:
1 st design of the Circuit topology
To electricity driving multiple FETsThe circuit shown in fig. 1 is used for the way design. In the figure, the level at which the FET is located is classified into GND-1, GND-2, \8230;, GND-i, \8230;, GND-n, and based on each level, a plurality of FET devices can be driven simultaneously, for example, the level FETs at GND-i include Qia, qib, \8230;, qij, \8230;, qim i 。
2, calculating element values in the FET drive circuit
Selection of capacitance values
The gate-to-source capacitance of a FET is known from the FET manual (e.g., the gate-to-source capacitance of Qij is denoted as C GS-ij )。
In line i C of FIG. 1 i The calculation of (A) is an example of the selection of the value range of the capacitance, which should satisfy
And the larger the capacity value, the better.
2.2 calculation of selection Range of resistance values
Also in line i R of FIG. 1 i The calculation of (A) is an example of the selection of the value range of the resistance, which should be based on C i The period of the switching signal (denoted as T) S ) Maximum time (T) of adaptation level V ) Required to determine the range (note: maximum time (T) for adapting the level V ) Means how long it is desired for the driver circuit to track a new level, T, when the level of the FET changes V Should be more than 10 times T S ). This resistor R i Is in the value range of
The calculation process of the capacitance and the resistance of the other rows in fig. 1 is similar to that of the ith row, and is not described herein again.
Secondly, the design method for the drive circuit of the BJT comprises the following steps:
1, designing a circuit topology
And designing a circuit topology structure according to the number of actually required levels and the number of BJTs required to be driven on each level and according to the figure 3.
2, calculating the element value range of the resistor and the capacitor in the circuit
2.1, calculating component value ranges of coupling capacitance
According to the current consumed when each transistor is turned on (the base current of BJT with serial number Qij is I) B-ij ) And assuming that the period of the switching signal is T S ' if, the value range of the coupling capacitance Ci of the ith row is
2.2 calculating element value range of resistance
Suppose that the time for tracking the level is T after the level is changed V 'in the case of action i, the range of Ri' is
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and any simple modifications, equivalent variations and modifications made to the above embodiment according to the technical spirit of the present invention are within the scope of the technical solution of the present invention.
Claims (2)
1. A floating level field effect transistor or transistor drive circuit based on coupling capacitance is characterized in that: comprises a FET drive circuit and a BJT drive circuit; wherein:
the FET driving circuit comprises n groups of FETs, n coupling capacitors and n resistors, wherein each group of FETs comprises at least one FET; for the ith group of FETs: the sources of the group of FETs are at the same level; a switch signal terminal is connected with the gate of each FET of the group through a coupling capacitor Ci, and the resistance Ri of the switch signal terminal is connected with the source of the FET; i is a natural number from 1 to n;
the selection method aiming at the coupling capacitor comprises the following steps:
labeling a coupling capacitance between the ith group of FETs and the switched signal terminal as Ci;
first, the gate-source capacitance C of each FET in the FET group corresponding to the coupling capacitance Ci is found from the FET manual GS-ij J is a natural number from 1 to n;
then, the coupling capacitance Ci corresponding to the i-th group of FETs satisfies the following equation:
wherein: m is i The number of the i-th group of FETs;
the selection method for the voltage-dividing resistor comprises the following steps:
the resistance between the source of the i-th group of FETs and the switch signal terminal is labeled Ri; the period of the switching signal is marked T S (ii) a The maximum time of adaptation level is denoted T V ；T V Greater than 10 times T S (ii) a Resistance R i The value range of (A) is as follows:
the BJT driving circuit comprises n groups of BJTs, and each group of BJTs comprises at least one BJT; for the ith group of BJTs: the emitters of the BJTs in the same level; the switch signal terminal is connected with the base electrode of each BJT of the group through a coupling capacitor Ci ', and is connected with the emitter electrode of the BJT through a resistor Ri'; i is a natural number from 1 to n;
the selection method aiming at the coupling capacitor comprises the following steps:
marking a coupling capacitance between the ith group of BJTs and the switch signal terminal as Ci';
marking as I according to the base current of the jth BJT in the ith group when the transistor is turned on B-ij A coupling capacitance Ci'; the period of the switching signal is T S ', the value range of the coupling capacitance Ci' is
Wherein: m is i The number of the ith group of BJTs;
the selection method aiming at the voltage-dividing resistor comprises the following steps:
marking a voltage division resistor between the ith group of BJTs and a switch signal terminal as Ri'; the period of the switching signal is marked T S '; the maximum time for adapting the level is denoted T V '; resistance R i The' value ranges are:
2. the coupling capacitance based floating level fet or transistor driver circuit of claim 1, wherein: the source electrode of each FET is connected with the grid electrode of the FET through a voltage regulator tube; each coupling capacitance Ci is connected to the gate of the FET through a current limiting resistor.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012103711A1 (en) * | 2011-01-31 | 2012-08-09 | Tsinghua University | Vertically foldable memory array structure |
| US9780746B1 (en) * | 2016-04-13 | 2017-10-03 | Macom Technology Solutions Holdings, Inc. | N-stacked field effect transistor based traveling wave power amplifier for monolithic microwave integrated circuits |
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| US10320379B2 (en) * | 2016-12-21 | 2019-06-11 | Qorvo Us, Inc. | Transistor-based radio frequency (RF) switch |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012103711A1 (en) * | 2011-01-31 | 2012-08-09 | Tsinghua University | Vertically foldable memory array structure |
| US9780746B1 (en) * | 2016-04-13 | 2017-10-03 | Macom Technology Solutions Holdings, Inc. | N-stacked field effect transistor based traveling wave power amplifier for monolithic microwave integrated circuits |
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Effective date of registration: 20211118 Address after: 300384 No. 6 Huake No. 7 Road, Binhai New Area, Tianjin Binhai High-tech Industrial Development Zone Applicant after: CETC Energy Co.,Ltd. Address before: 300384 No. 6 Huake No. 7 Road, Binhai New Area, Tianjin Binhai High-tech Industrial Development Zone Applicant before: The 18th Research Institute of China Electronics Technology Group Corporation |
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Address after: 300384 No. 6 Huake No. 7 Road, Binhai New Area, Tianjin Binhai High-tech Industrial Development Zone Patentee after: CETC Blue Sky Technology Co.,Ltd. Address before: 300384 No. 6 Huake No. 7 Road, Binhai New Area, Tianjin Binhai High-tech Industrial Development Zone Patentee before: CETC Energy Co.,Ltd. |
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