CN109786466A - A method of improving FinFET high frequency/high speed performance - Google Patents
A method of improving FinFET high frequency/high speed performance Download PDFInfo
- Publication number
- CN109786466A CN109786466A CN201910066276.2A CN201910066276A CN109786466A CN 109786466 A CN109786466 A CN 109786466A CN 201910066276 A CN201910066276 A CN 201910066276A CN 109786466 A CN109786466 A CN 109786466A
- Authority
- CN
- China
- Prior art keywords
- finfet
- high frequency
- high speed
- speed performance
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
FinFET high frequency/high speed performance method can be improved the invention discloses a kind of, the present invention includes the following steps: in existing FinFET manufacture craft, after completing channel etching, before gate oxide deposition, germanium (Ge) ion of a certain concentration and dosage is injected close to the half channel region of drain terminal (drain) in channel, and the prior art technology after holding is without modification.Therefore, this method and previous technique have compatibility well, and there is no the apparent difficulty and complexity for increasing technique for manufacturing process.In addition, additionally providing theoretical basis, and the calculation method of the performance improved.FinFET high frequency/high speed performance method can be improved to meet the needs of some modern circuits are higher and higher to device high frequency/high speed performance the present invention provides a kind of.
Description
Technical field
The invention belongs to semiconductor integrated information devices fields, are related to a kind of raising FinFET high frequency/high speed performance
Method.
Background technique
Semiconductor integrated device and circuitry process technology experienced fast development.In this process, usually pass through device spy
Diminution or the geometry adjustment of size are levied to increase the functional density of device.The bi-directional scaling technique usually can improve effect
Rate reduces cost and/or improves performance etc. to provide benefit.Currently, Moore's Law gradually fails, device is scaled to be become
It is more and more difficult.This is primarily due to become increasingly severe with the continuous diminution of device size, tunneling effect, particularly to
When 7nm technology node FinFET, become more difficult by reducing device size to improve device high frequency/high speed performance.
Moreover, the manufacture of integrated device and IC chip is related to thousands of different processing steps in total.With
Device size be constantly reduced to 7nm technology node, these manufacturing process such as aoxidize, photoetching, deposition requirement become high,
It is another key factor that cost, which sharply increases,.Therefore, it before finding device size and continuing to reduce in the method for improving performance, seeks
It is necessary that other methods, which are looked for, to push being constantly progressive for device performance.
Summary of the invention
In view of the problems of the existing technology, the present invention provides a kind of raising FinFET high frequency/high speed performances
Method.
The technical solution adopted for solving the technical problem of the present invention is as follows:
A method of FinFET high frequency/high speed performance is improved, is increased in existing FinFET manufacturing process
The injection step of one of germanium ion deposits it in gate oxide after completing channel etching that is, in FinFET manufacturing process
Before, the germanium ion of a certain concentration and dosage is injected close to the half channel region of drain terminal in channel, and existing after holding
Technology is without modification.
Wherein, for transoid FinFET, the concentration of germanium ion concentrates on the surface of channel.
Wherein, the concentration of germanium ion concentrates on the center of channel.
In addition, the implantation concentration of germanium ion can be adjusted according to specific current needs, and the injection of germanium ion
Mode is using rotation injection mode.
Beneficial effects of the present invention: the present invention utilizes reduction device size raising performance different from current, and the present invention is logical
The minor adjustment of device local process technology is crossed to realize the promotion of device function, compensates for existing method and technological means not
Foot especially has good prospect of the application in being directed to high frequency/high speed circuit.Pass through reduction device ruler the present invention overcomes previous
Very little raising circuit performance becomes more and more difficult problem.
Specific embodiment
Cardinal principle of the invention: FinFET mainly carries out the control of channel by gate metal.Pass through grid
Metal can change the forbidden bandwidth in channel, thus the conducting and closing of control device.The forbidden bandwidth of Ge is about 0.67eV
The forbidden bandwidth for being about 1.12eV much smaller than silicon materials (Si).Ge is doped into FinFET channel made of Si, then with pure
Net Si channel is compared, its forbidden bandwidth can reduce.Therefore, by channel close to drain terminal inject certain density Ge from
Son can be such that forbidden bandwidth reduces from source to drain terminal direction.To induce the electric field of some strength in channels, this is just
Facilitate electronics across channel.Also, the every reduction 100meV of forbidden bandwidth, the order of magnitude of induction field is just 103~104V/cm。
Meanwhile the electric current of channel increases, speed increases, to reduce time of the electronics by channel.This adds increased be doped with Ge from
The cutoff frequency of sub- FinFET improves high frequency/high speed performance of FinFET.
The calculating of induced electric field:。
Embodiment:
The present embodiment is to increase the injection step of one of Ge ion in existing FinFET manufacturing process.It is specific as follows: when complete
It is certain dense close to the half channel region injection of drain terminal (drain) in channel before gate oxide deposition after channel etching
The Ge ion of degree and dosage, and the prior art technology after holding is without modification.Therefore, this method and previous technique
With good compatibility, there is no the apparent difficulty and complexity for increasing technique for manufacturing process.
It is as follows particularly with regard to the injection details of Ge ion: for transoid FinFET, electric current master when due to break-over of device
If on the surface of channel.Therefore, when adulterating Ge ion in transoid FinFET, Implantation Energy be should not be too large: make Ge
The concentration of ion concentrates on the surface of channel, to make the working efficiency for the induction field to be formed higher.For jointless type
FinFET, according to body current effect, the conducting electric current of device is concentrated mainly on the center of channel.Therefore, when in jointless type
When adulterating Ge ion in FinFET, Implantation Energy should be properly increased: so that the concentration of Ge ion is concentrated on the center of channel,
To make the induction field to be formed higher to the drive efficiency of electronics.In addition, the implantation concentration of Ge ion can also be according to specific
Current needs be adjusted, and inject should by rotation injection mode to guarantee good Ge ion implanting efficiency.
To sum up, the germanium that the invention mainly relates to a kind of by injecting doses close to the part of drain terminal in device channel
(Ge) ion, to improve FinFET high frequency/high speed performance method.Exist more particularly to for sub- 7nm and following device
High frequency/high speed performance is improved under technology size reduction becomes further difficult, to propose a kind of not by reducer part ruler
Very little raising FinFET switching current ratio (Ion/Ioff), and then promote high frequency/high speed performance method.
Those skilled in the art are it should be appreciated that the above implementation steps and scheme are intended merely to say of the invention
Bright and explanation, and it is not intended as limitation of the invention, as long as within the scope of the invention, to the above implementation steps and scheme
Variation, deformation will all be within the scope of the present invention.
Claims (4)
1. a kind of raising FinFET high frequency/high speed performance method, it is characterised in that:
In existing FinFET manufacturing process, increase the injection step of one of germanium ion, i.e., is made in FinFET
It is certain close to the half channel region injection of drain terminal in channel before gate oxide deposition after completing channel etching in the process
The germanium ion of concentration and dosage, and the prior art technology after holding is without modification.
2. a kind of raising FinFET high frequency/high speed performance method according to claim 1, it is characterised in that: right
The surface of channel is concentrated in the concentration of transoid FinFET, germanium ion.
3. a kind of raising FinFET high frequency/high speed performance method according to claim 1, it is characterised in that: right
The center of channel is concentrated in the concentration of jointless type FinFET, germanium ion.
4. according to claim 1 to a kind of method of raising FinFET high frequency/high speed performance described in optional one in 3,
It is characterized by: the implantation concentration of germanium ion can be adjusted according to specific current needs, and the injection side of germanium ion
Formula is using rotation injection mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910066276.2A CN109786466A (en) | 2019-01-24 | 2019-01-24 | A method of improving FinFET high frequency/high speed performance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910066276.2A CN109786466A (en) | 2019-01-24 | 2019-01-24 | A method of improving FinFET high frequency/high speed performance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109786466A true CN109786466A (en) | 2019-05-21 |
Family
ID=66502285
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910066276.2A Pending CN109786466A (en) | 2019-01-24 | 2019-01-24 | A method of improving FinFET high frequency/high speed performance |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109786466A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030116792A1 (en) * | 2001-12-20 | 2003-06-26 | Board Of Regents, The University Of Texas System | Submicron MOSFET having asymmetric channel profile |
| CN106935651A (en) * | 2015-12-29 | 2017-07-07 | 台湾积体电路制造股份有限公司 | Transistor unit |
-
2019
- 2019-01-24 CN CN201910066276.2A patent/CN109786466A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030116792A1 (en) * | 2001-12-20 | 2003-06-26 | Board Of Regents, The University Of Texas System | Submicron MOSFET having asymmetric channel profile |
| CN106935651A (en) * | 2015-12-29 | 2017-07-07 | 台湾积体电路制造股份有限公司 | Transistor unit |
Non-Patent Citations (1)
| Title |
|---|
| ZHANFEI CHEN ET AL: "Investigation of the Dynamic Thermal", 《2018 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD)》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101404292A (en) | VDMOS device | |
| CN104167360B (en) | Transverse diffusion metal oxide semiconductor device and its manufacture method | |
| CN105825878A (en) | Recovery circuit for improving negative bias-temperature instability of memory clock circuit | |
| CN102543738A (en) | High-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacture method for same | |
| CN109119463A (en) | A kind of lateral trench type MOSFET element and preparation method thereof | |
| CN102124548B (en) | Transistor with gain variation compensation | |
| CN208028068U (en) | Semiconductor devices | |
| CN103474463B (en) | There is the MOSFET in the induction net charge district in thick bottom insulator | |
| CN109904220A (en) | Groove gate type silicon carbide MOSFET device and preparation method | |
| CN107845580A (en) | A kind of VDMOS device and preparation method thereof | |
| CN106449744A (en) | Novel trench gate IGBT (insulated gate bipolar transistor) provided with gate embedded diode and preparation method of novel trench gate IGBT | |
| CN109786466A (en) | A method of improving FinFET high frequency/high speed performance | |
| CN103441074B (en) | A kind of manufacture is integrated with the method for the IGBT device of diode | |
| CN104867834A (en) | Single-impurity atom junction-free silicon nano wire transistor based on SOI substrate, and preparation method thereof | |
| CN110676305A (en) | Vertical channel device with low gate charge characteristics and method of manufacture | |
| He et al. | Linearly graded doping drift region: a novel lateral voltage-sustaining layer used for improvement of RESURF LDMOS transistor performances | |
| CN105914238B (en) | High pressure JFET device and process | |
| Zhang et al. | High performance CSTBT with p-type buried layer | |
| CN106356304A (en) | Semiconductor production process | |
| CN105742179B (en) | A kind of preparation method of IGBT device | |
| CN109166804B (en) | Preparation method of zero threshold voltage NMOS | |
| CN104282753A (en) | High-integration-level source, drain and gate auxiliary control U-shaped channel high-mobility-ratio junction-free transistor shaped like Chinese character 'ri' | |
| CN205211709U (en) | Structure of power device | |
| Lu et al. | Hot-carrier-induced reliability concerns for lateral DMOS transistors with split-STI structures | |
| Li et al. | Analytical Modeling and Simulation of Dual-Material Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistors with Single-Halo Doping |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20190521 |