CN109786361B

CN109786361B - Delay chain structure for overcoming timing sequence deviation of chip under different process angles

Info

Publication number: CN109786361B
Application number: CN201910058193.9A
Authority: CN
Inventors: 袁庆; 李华东; 董建国; 徐军
Original assignee: Shenzhen Union Memory Information System Co Ltd
Current assignee: Shenzhen Union Memory Information System Co Ltd
Priority date: 2019-01-22
Filing date: 2019-01-22
Publication date: 2020-08-11
Anticipated expiration: 2039-01-22
Also published as: CN109786361A

Abstract

The invention relates to a delay chain structure for overcoming the time sequence deviation of a chip under different process angles, which comprises a plurality of delay units, wherein adjacent delay units are connected by adopting a delay line; the delay line is a meander line. The invention improves the quality of the delay chain structure, ensures that the delay chain structure is not influenced by process deviation and can better meet the requirements.

Description

Delay chain structure for overcoming timing sequence deviation of chip under different process angles

Technical Field

The invention relates to the technical field of delay chains, in particular to a delay chain structure for overcoming timing sequence deviation of a chip under different process angles.

Background

As chip processing moves into deep sub-micron, especially into 28nm, Short Channel Effects (SCE) caused by transistor channel shortening cause the chip to drift sharply under SS (slow process corner)/TT (normal process corner)/FF (fast process corner) processing.

At present, units are mainly used for meeting the delay requirement, but the delay ratio under FF/SS under different process angles reaches 1:3, the process influence is serious, and the requirement cannot be met.

Disclosure of Invention

The present invention is directed to overcome the drawbacks of the prior art, and provides a delay chain structure for overcoming timing skew of a chip under different process corners.

In order to achieve the purpose, the invention adopts the following technical scheme:

a delay chain structure for overcoming timing sequence deviation of a chip under different process angles comprises a plurality of delay units, wherein adjacent delay units are connected by adopting a delay line; the delay line is a meander line.

The further technical scheme is as follows: the delay unit is a buffer driven by 8 times.

The further technical scheme is as follows: the delay line is a second layer of metal lines.

The further technical scheme is as follows: the length of the delay line is 200-400 um.

The further technical scheme is as follows: the length of the delay line is 300 um.

The further technical scheme is as follows: the loop-shaped routing is at least 2 sections.

The further technical scheme is as follows: the line is walked to the type of returning 4 sections, and every section 75 um.

Compared with the prior art, the invention has the beneficial effects that: the quality of the structure of the delay chain is improved, so that the delay chain is not influenced by process deviation and can better meet the requirement.

The invention is further described below with reference to the accompanying drawings and specific embodiments.

Drawings

FIG. 1 is a schematic circuit diagram of a delay chain structure for overcoming timing skew of a chip under different process corners according to the present invention;

FIG. 2 is a schematic diagram of a trace of a delay chain structure for overcoming timing skew of a chip under different process corners according to the present invention.

Detailed Description

In order to more fully understand the technical content of the present invention, the technical solution of the present invention will be further described and illustrated with reference to the following specific embodiments, but not limited thereto.

As shown in fig. 1 to 2, a delay chain structure for overcoming timing skew of a chip under different process angles includes a plurality of delay units 10, wherein adjacent delay units 10 are connected by a delay line 20; the delay line 20 is a meander line.

Wherein the delay unit 10 is a buffer with a drive of 8 times.

The delay line 20 is a second layer metal line, which has relatively large resistance and can generate large line delay, thereby meeting the requirements.

Wherein the length of the delay line 20 is 200-400 um.

Further, in this embodiment, the length of the delay line 20 is 300um, which can better meet the requirement.

Wherein, the zigzag trace is at least 2 sections.

Further, in this embodiment, the loop trace has 4 segments, each segment having 75um, so that the delay cell delay and the line delay of 300um are both close to 50ps (SS process corner).

The 1-stage unit plus line delay is 100ps, and in order to meet the requirement of 10ns (FF process corner) 20ns (SS process corner) of the whole delay chain, a 200-stage design example can be used to achieve the final design requirement.

The delay difference of transistors under SS and FF in the prior art reaches 1:3, while the delay chain designed in the chip of the invention is not sensitive to the process, ideally, the delay of 100-level delay chain under SS/FF is close to less than 1:2, while the delay of metal connecting wires does not show great difference under different process corners along with the process evolution, and almost has a 1:1 relationship under SS/FF; and the ratio of the delay time of the delay unit to the delay time of the delay line directly connected with the delay unit is 1:1, so that the overall delay can obtain the effect of 2:4, thereby reaching the design requirement.

The invention reduces the delay ratio of the same delay chain to be less than 1:2 under different processes, improves the quality of the structure of the delay chain and prevents the delay chain from being influenced by process deviation.

The technical contents of the present invention are further illustrated by the examples only for the convenience of the reader, but the embodiments of the present invention are not limited thereto, and any technical extension or re-creation based on the present invention is protected by the present invention. The protection scope of the invention is subject to the claims.

Claims

1. A delay chain structure for overcoming timing sequence deviation of a chip under different process angles is characterized by comprising a plurality of delay units, wherein adjacent delay units are connected by adopting a delay line; the delay line is a zigzag routing, and the delay unit is a buffer with 8 times of driving; the delay line is a second layer of metal line; the length of the delay line is 200-400um, and the loop-shaped routing is at least 2 sections; wherein a ratio of a delay time of the delay unit to a delay time of a delay line directly connected to the delay unit is 1: 1.

2. The delay chain structure of claim 1, wherein the length of the delay line is 300 um.

3. The delay chain structure of claim 1, wherein the loop trace has 4 segments of 75um each.