CN109783055A - Floating point arithmetic circuit and method - Google Patents
Floating point arithmetic circuit and method Download PDFInfo
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- CN109783055A CN109783055A CN201711106649.1A CN201711106649A CN109783055A CN 109783055 A CN109783055 A CN 109783055A CN 201711106649 A CN201711106649 A CN 201711106649A CN 109783055 A CN109783055 A CN 109783055A
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Abstract
Disclosed herein a kind of floating point arithmetic circuit and methods.Floating point arithmetic circuit is used to carry out one first operand, one second operand and a third operand one fusion product accumulation method operation or a product accumulation method operation, or carries out a multiplying to first operand and second operand.The floating point arithmetic circuit includes two reconditioning circuits, a mlultiplying circuit, a selection circuit, a control circuit and an add circuit.Control circuit controls the scheduling and each utilization for calculating resource on path of various operations, to simplify circuit and promote the efficiency of processor.
Description
Technical field
The present invention relates to the operations of floating number, multiplying, product accumulation method operation especially with respect to floating number
(multiplication and accumulation, mac) and fusion product accumulation method operation (fused
multiplication and accumulation,fused mac)。
Background technique
The arithmetical operation that processor carries out floating number is related to addition, subtraction, multiplication, division, product accumulation method, fusion often
The operations such as product accumulation method.The operation of product accumulation method and fusion product accumulation method operation are all that (A, B, C are all floating to calculating A*B+C
Points), but because product accumulation method is performed on multiplying and add operation and respectively does primary finishing (rounding), and merge and multiply
Accumulation add operation only does primary finishing in add operation, so fusion product accumulation method operation can obtain relatively accurate knot
Fruit.Known processor, which usually does a other operation, to be optimized, but optimizes a other operation to promotion processor
Overall efficiency is limited.Therefore the optimization circuit for accounting for a variety of operations simultaneously is needed, to simplify circuit and more mention
Rise the efficiency of processor.
Summary of the invention
In view of the deficiency of prior art, a purpose of the present invention is that a kind of floating point arithmetic circuit and method are provided, with
Simplify circuit and promotes the efficiency of processor.
The invention discloses a kind of floating point arithmetic circuits, for one first operand, one second operand and a third
Operand carries out a fusion product accumulation method operation or a product accumulation method operation, or to first operand and second fortune
It calculates member and carries out a multiplying.The floating point arithmetic circuit includes a mlultiplying circuit, a selection circuit, a control circuit and one
Add circuit.The mlultiplying circuit receives first operand and second operand, and to first operand and second fortune
It calculates member and carries out the multiplying to generate not trimmed product and a trimmed product.It is not trimmed that the selection circuit receives this
Product and the trimmed product, and export the not trimmed product and trimmed one of the product.When the floating number is transported
When calculation circuit executes the product accumulation method operation, controls the selection circuit and export the trimmed product, and when the floating number is transported
When calculation circuit executes the fusion product accumulation method operation, controls the selection circuit and export the not trimmed product.The add circuit
Receive one of the not trimmed product and the trimmed product and the third operand, and by the not trimmed product
And one of the trimmed product is added with the third operand, to obtain an operation result, wherein the operation result is
The result of the fusion product accumulation method operation or the product accumulation method operation.Total input digit of the add circuit is greater than twice
The digit of first operand, the second operand or third operand.
The present invention separately discloses a kind of floating point arithmetic method, for one first operand, one second operand and 1 the
Three operands carry out an a fusion product accumulation method operation or product accumulation method operation, or to first operand and this second
Operand carries out a multiplying.The method includes the steps of: with a mlultiplying circuit receive first operand and this second
Operand, and the multiplying is carried out to first operand and second operand to generate one without repairing with the mlultiplying circuit
The trimmed product of whole product and one；The not trimmed product and the trimmed product are received with a selection circuit, and exports this not
Trimmed product and trimmed one of the product；When the product accumulation method operation is performed, the selection circuit is controlled
Export the trimmed product, and when the fusion product accumulation method operation is performed, controlling selection circuit output should be without
The product of finishing；And one of the not trimmed product and the trimmed product and the third are received with an add circuit
Operand, and with the add circuit to one of the not trimmed product and the trimmed product and the third operand into
One add operation of row, to obtain an operation result, wherein the operation result is that the fusion product accumulation method operation or the product are tired
The result of add operation.Total input digit of the add circuit is greater than twice of first operand, the second operand or third
The digit of operand.
Floating point arithmetic circuit of the invention and method integrate the multiplying of floating number, the operation of product accumulation method and fusion
Product accumulation method operation.Compared to traditional technology, the floating point arithmetic circuit and method of the present invention simultaneously thus three kinds of operations into
Row optimization, to promote the efficiency of processor and simplify circuit.
Feature, implementation and effect for the present invention, hereby schema being cooperated to make embodiment, detailed description are as follows.
Detailed description of the invention
[Fig. 1] is the circuit diagram of the calculating section of floating point arithmetic circuit of the present invention；
[Fig. 2] is the flow chart of the calculating section of floating point arithmetic method of the present invention；
[Fig. 3] is the circuit diagram of an embodiment of the detecting part of floating point arithmetic circuit of the present invention；
[Fig. 4] is the flow chart of an embodiment of the detecting part of floating point arithmetic method of the present invention；
[Fig. 5] is the circuit diagram of another embodiment of the detecting part of floating point arithmetic circuit of the present invention；And
[Fig. 6] is the flow chart of another embodiment of the detecting part of floating point arithmetic method of the present invention.
Specific embodiment
The technical terms of following description are the idioms referring to the art, if this specification is to part term
It is illustrated or defines, the explanation or definition of this specification are subject in the explanation of the part term.
Disclosure of the invention includes floating point arithmetic circuit and method.By floating point arithmetic circuit institute of the invention
For the members for including are independent may be known tip assemblies, therefore do not influence the device inventions it is abundant disclose and it is implementable
Under the premise of property, illustrate that memorandum will be given for the details of known tip assemblies below.In addition, floating point arithmetic method of the invention
Part or all of process can be executed by floating point arithmetic circuit or its equivalent device of the invention, not influence this method
Under the premise of the abundant exposure of invention and exploitativeness, the explanation that following methods are invented will focus on step content and non-hardware.
The circuit diagram of the calculating section of Fig. 1 system floating point arithmetic circuit of the present invention.With double precision (double in figure
Precision) (sign is indicated with a position, exponential part is indicated with 11 positions, indicates significant figure with 52 positions
(significand) fractional part) for, but the present invention is equally applicable for other precision that IEEE 754-2008 is defined.
The general calculating that the computing architecture 100 of floating point arithmetic circuit is used to carry out floating number (is transported comprising multiplying, product accumulation method
Calculate and fusion the operation of product accumulation method), comprising mlultiplying circuit 110, reconditioning circuit 112, selection circuit 120, add circuit 130,
Reconditioning circuit 132 and control circuit 140.The computing architecture 100 of floating point arithmetic circuit is by shared or reuse multiplication electricity
Road 110 and add circuit 130 optimize this three kinds of operations simultaneously, to promote circuit performance and save circuit area.
Fig. 2 is the flow chart of the calculating section of floating point arithmetic method of the present invention, this flow chart corresponds to the circuit of Fig. 1
Figure.Firstly, mlultiplying circuit 110 receives operand A and B (step S210) in the stage 1, then mlultiplying circuit 110 to operand A and
B carries out multiplying, and generates product D and product D_r (step S220).Product D is not trimmed, regular
(normalize) or truncation (rounding/truncate) as a result, product D_r be then the finishing of product D trimmed circuit 112,
Result after normalization or truncation.The digit of product D_r is identical as operand A and B.Reconditioning circuit 112 is according to preset finishing
Mode is modified, such as is rounded up (round-to-nearest), past positive number approximation (round-toward-
Positive), toward negative approximate (round-toward-negative) or past zero approximate (round-toward-zero).Finishing
Circuit 112 may include in mlultiplying circuit 110；Or mlultiplying circuit 110 and reconditioning circuit 112 can be independent circuit.
The operation result R_no1=D_r of the multiplying of the computing architecture 100 of floating point arithmetic circuit is exported in the stage 1
(step S230).Product D and product D_r is in 2 input selection circuit 120 (step S235) of stage.Following control circuit 140 is sentenced
The computing architecture 100 of disconnected floating point arithmetic circuit carries out the operation of product accumulation method or fusion product accumulation method to operand A, B and C
Operation (step S240), and corresponding control selections circuit 120 exports product D or product D_r.When product accumulation method operation is performed
When, 140 control selections circuit 120 of control circuit output product D_r and add circuit 130 the stage 2 by operand C with multiply
Product D_r is added (step S250)；When fusion product accumulation method operation is performed, 140 control selections circuit 120 of control circuit is defeated
Operand C is added (step S260) with product D in the stage 2 by product D and add circuit 130 out.It note that add circuit
130 can receive operand C in stage 1 or stage 2.It is exported and (step finally, reconditioning circuit 132 modifies add circuit 130
S270), operation result R_no2 is obtained.In more detail, according to the selection result of selection circuit 120, reconditioning circuit 132 is to C
The result of+D or the result of C+D_r are modified.The digit of operation result R_no2 is identical as operand A, B and C.Floating number
The computing architecture 100 of computing circuit exports operation result R_no2 as the operation of product accumulation method or fusion product accumulation method operation
Result (step S280).Reconditioning circuit 132 may include in add circuit 130；Or add circuit 130 and reconditioning circuit
132 can be independent circuit.The above-mentioned stage 2 was located at after the stage 1.
The computing architecture 100 of floating point arithmetic circuit is acted according to work clock；More particularly, mlultiplying circuit 110, repair
Whole circuit 112, selection circuit 120, add circuit 130, reconditioning circuit 132 and control circuit 140 are acted according to work clock.Multiply
Method circuit 110 is Pipelining circuit, and occupies an at least period for work clock；That is, from receive operand A, B to
Generate operation result R_no1, period of the mlultiplying circuit 110 at least through a work clock.Similarly, add circuit 130 is
Pipelining circuit, and occupy an at least period for the clock；That is, from operand C and product (D or D_r) is received extremely
Generate operation result R_no2, period of the add circuit 130 at least through a work clock.
Circuit as shown in Figure 1, mlultiplying circuit 110 are also responsible for product accumulation method other than being responsible for multiplying (A*B)
Operation (A*B+C) and the multiplication part for merging the operation of product accumulation method (A*B+C).Furthermore because add circuit 130 is responsible for product
Summation operation and the addition section for merging the operation of product accumulation method, so add circuit 130 distributes to one of operand
(operand C) general digit (depending on the precision designed by the computing architecture 100 of floating point arithmetic circuit), is distributed to another
The not trimmed digit of a operand (D or D_r).By taking double precision as an example, total input digit of add circuit 130 is 64+119
Position, wherein 1,12 and 106 position in 119 is respectively used to indicate the fractional part of sign, exponential part and significant figure.
As a comparison, being provided purely for the add circuit of product accumulation method operation operation (that is, not with merge product accumulation method operation shared)
Total input digit be 64+64.
The circuit diagram of one embodiment of the detecting part of Fig. 3 system floating point arithmetic circuit of the present invention, floating point arithmetic circuit
Detecting structure 300 be used to detect the particular value (special value) of floating point arithmetic, include circuit for detecting 310, detecting electricity
Road 320, circuit for detecting 330, union (union) circuit 340, selection circuit 350 and control circuit 360.Control circuit 360 can be with
Circuit is shared with the control circuit 140 of Fig. 1, also or the two is with independent circuit implementation.The detecting frame of floating point arithmetic circuit
Structure 300 is for detecting whether operand A, B and C are particular value.When part or all of operand A, B and C are particular value,
The operation result of multiplying, the operation of product accumulation method and fusion product accumulation method operation can detecing by floating point arithmetic circuit
It surveys framework 300 to generate, without the calculating of the computing architecture 100 by floating point arithmetic circuit.Particular value include ± 0, ± ∞,
Nonumeric (not a number, NaN), unnomalized number (subnormal) etc..For example, the result of following operation can
To be determined by the detecting structure 300 of floating point arithmetic circuit, without the meter of the computing architecture 100 by floating point arithmetic circuit
It calculates:
± ∞ * 0=NaN (1)
± ∞ * F1=± ∞ (2)
± 0*F1=± 0 (3)
± 0+F1=F1 (4)
F1*F2+NaN=NaN (5)
Wherein F1 and F2 is the floating number of no special value and is unnomalized number.Example (1) to (5) is non-only as illustration
To limit the present invention.
Circuit for detecting 310 corresponds to multiplying, and circuit for detecting 320 corresponds to fusion product accumulation method operation, Yi Jizhen
Slowdown monitoring circuit 330 corresponds to add operation.Circuit for detecting 310, circuit for detecting 320 and circuit for detecting 330 more accordingly export operation
State flags (status flag).According to the definition of IEEE754-2008, state flags include (1) invalid operation
Position is owed in (invalid operation), (2) division by 0 (divided by zero), (3) overflow (overflow), (4)
(underflow), (5) are non-precision (inexact).Other than this is five kinds, state flags also may include the flag that user defines
Mark.
Fig. 4 is the flow chart of an embodiment of the detecting part of floating point arithmetic method of the present invention, this flow chart corresponds to
The circuit diagram of Fig. 3.The detecting structure 300 of floating point arithmetic circuit receives operand A and B in the stage 1 and (is connect by circuit for detecting 310
Receive) or operand A, B and C (step S410) (is received) by circuit for detecting 320.Circuit for detecting 310 is in the stage 1 according to operand A
And B generates detecting result R_sp1 and flag flag1 (step S420), detecting result R_sp1 and flag flag1 and corresponds to multiplication fortune
It calculates.Detecting result R_sp1 is, for example, one of above-mentioned particular value.For example, if operand A and B at least within
One of be particular value, cause multiplying be invalid operation or be not required to operation, then the operation result of multiplying is electric by detecting
Road 310 generates in the stage 1, without the calculating via mlultiplying circuit 110.
Circuit for detecting 320 generates detecting result R_sp2 and flag flag2 (step according to operand A, B and C in the stage 1
S430), the corresponding fusion product accumulation method operation of detecting result R_sp2 and flag flag2.Detecting result R_sp2 is e.g. above-mentioned
One of particular value.For example, if at least one of operand A, B and C are particular value, cause to merge product
Summation operation is invalid operation or is not required to operation, then merges the operation result of product accumulation method operation by circuit for detecting 320
It is generated in the stage 1, without the calculating via mlultiplying circuit 110 and add circuit 130.
Circuit for detecting 330 generates detecting result R_sp3 and intermediate flag according to detecting result R_sp1 and operand C in the stage 2
It marks flag ' (step S440).And collector 340 generates flag flag3 (step according to flag flag1 and centre flag flag '
S450), more particularly, and collector 340 is flag flag1 and centre flag flag ' by turn or operation (bitwise OR
Operation), to generate flag flag3.Detecting result R_sp3 and flag flag3 corresponds to product accumulation method operation.
Selection circuit 350 in the stage 2 from circuit for detecting 320 receive detecting result R_sp2 and flag flag2, from detecting electricity
Road 330 receives detecting result R_sp3 and receives flag flag3 (step S455) from simultaneously collector 340.Following control circuit
360 judge that the detecting structure 300 of floating point arithmetic circuit carries out the operation of product accumulation method or fusion product to operand A, B and C
Summation operation (step S460), and control selections circuit 350 export (R_sp2, flag2) or (R_sp3, flag3) using as
Final detecting result R_sp4 and final flag flag4.When product accumulation method operation is performed, control circuit 360 is controlled
Selection circuit 350 exports detecting result R_sp3 and flag flag3 (step S470) in the stage 2；When fusion product accumulation method operation
It is performed, 360 control selections circuit 350 of control circuit exports detecting result R_sp2 and flag flag2 (step in the stage 2
S480)。
The circuit diagram of another embodiment of the detecting part of Fig. 5 system floating point arithmetic circuit of the present invention, floating point arithmetic electricity
The detecting structure 500 on road is used to detect the particular value of floating point arithmetic, includes circuit for detecting 510, circuit for detecting 520, detecting electricity
Road 530 and collector 540, selection circuit 550 and control circuit 560.Control circuit 560 can be with the control circuit 140 of Fig. 1
Shared circuit, also or the two is with independent circuit implementation.The detecting structure 500 of floating point arithmetic circuit is for detecting operand
A, whether B and C is particular value.When part or all of operand A, B and C are particular value, multiplying, product accumulation method
Operation and the operation result for merging the operation of product accumulation method can be generated by the detecting structure 500 of floating point arithmetic circuit, without
It need to be by the calculating of the computing architecture 100 of floating point arithmetic circuit.Circuit for detecting 510 corresponds to multiplying, circuit for detecting 520
Correspond to add operation corresponding to fusion product accumulation method operation and circuit for detecting 530.Circuit for detecting 510, circuit for detecting
520 and circuit for detecting 530 more accordingly export the state flags of operation.
Fig. 6 is the flow chart of another embodiment of the detecting part of floating point arithmetic method of the present invention, this flow chart is corresponding
In the circuit diagram of Fig. 5.The detecting structure 500 of floating point arithmetic circuit receives operand A and B in the stage 1 (by circuit for detecting 510
Receive) or operand A, B and C (step S610) (is received) by circuit for detecting 520.Circuit for detecting 510 is in the stage 1 according to operand
A and B generates detecting result R_sp1 and flag flag1 (step S620), detecting result R_sp1 and flag flag1 and corresponds to multiplication fortune
It calculates.Detecting result R_sp1 is, for example, one of above-mentioned particular value.For example, if operand A and B at least within
One of be particular value, cause multiplying be invalid operation or be not required to operation, then the operation result of multiplying is electric by detecting
Road 510 generates in the stage 1, without the calculating via mlultiplying circuit 110.
Circuit for detecting 520 generates detecting result R_sp2 and flag flag2 (step according to operand A, B and C in the stage 1
S630), the corresponding fusion product accumulation method operation of detecting result R_sp2 and flag flag2.Detecting result R_sp2 is e.g. above-mentioned
One of particular value.For example, if at least one of operand A, B and C are particular value, cause to merge product
Summation operation is invalid operation or is not required to operation, then the operation result of multiplying is produced by circuit for detecting 520 in the stage 1
It is raw, without the calculating via mlultiplying circuit 110 and add circuit 130.
Selection circuit 550 in the stage 1 from circuit for detecting 510 receive detecting result R_sp1 and flag flag1, from detecting electricity
Road 520 receives detecting result R_sp2 and flag flag2 (step S635).Following control circuit 560 judges floating point arithmetic electricity
500 system of detecting structure on road carries out multiplying or the fusion operation of product accumulation method (step S640), and control selections circuit 550
(R_sp1, flag1) or (R_sp2, flag2) is exported using the flag flag4 of detecting result R_sp4 and stage 1 as the stage 1.
When multiplying is performed, 560 control selections circuit 550 of control circuit exports detecting result R_sp1 and flag in the stage 1
Flag1 (step S650)；When fusion product accumulation method operation is performed, 560 control selections circuit 550 of control circuit is in the stage
1 output detecting result R_sp2 and flag flag2 (step S660).
Circuit for detecting 530 generates detecting result R_sp3 and intermediate flag according to detecting result R_sp1 and operand C in the stage 2
It marks flag ' (step S670).And collector 540 generates flag flag3 (step according to flag flag1 and centre flag flag '
S680), more particularly, and collector 540 is flag flag1 and centre flag flag ' by turn or operation, to generate flag
flag3.Detecting result R_sp3 and flag flag3 corresponds to product accumulation method operation, and exports (step S690) in the stage 2.
Circuit for detecting 310~330 and circuit for detecting 510~530 can be by logic circuit implementations, and those circuit for detecting
How detecting result is generated according to input value and flag is that the art has known to usually intellectual, so it will not be repeated.
The computing architecture 100 of the floating point arithmetic circuit of Fig. 1 can be with the detecting structure of the floating point arithmetic circuit of Fig. 3
The detecting structure 500 of the floating point arithmetic circuit of 300 or Fig. 5 forms floating point arithmetic circuit of the invention.In Fig. 1 and Fig. 3 group
In the embodiment of conjunction, the result (the detecting result R_sp1 of the result R_no1 or particular value that generally calculate) of multiplying is in rank
Section 1 exports, and the operation of product accumulation method or result (the result R_no2 generally calculated or the spy of merging the operation of product accumulation method
The detecting result R_sp4 being very worth) it is exported in the stage 2.In the embodiment that Fig. 1 is combined with Fig. 5, the result of multiplying is (general
The result R_no1 of the calculating or detecting result R_sp1 of particular value) and fusion the operation of product accumulation method particular value detecting knot
Fruit R_sp2 is exported in the stage 1, and merges the result R_no2 of the operation of product accumulation method or product accumulation method operation generally calculated
And the detecting result R_sp3 of the particular value of product accumulation method operation is exported in the stage 2.It can be seen that compared to Fig. 1 and Fig. 3
Combined embodiment has an opportunity more early obtain fusion product accumulation method operation in the embodiment that Fig. 1 is combined with Fig. 5
As a result it (is exported in stage 1 rather than stage 2).
(for purpose of brevity, control circuit 140,360 and 560 above-mentioned is electrically connected with other circuits in Fig. 1,3 and 5 respectively
Do not show that those are online), for controlling the scheduling and each utilization for calculating resource on path of various operations.Control circuit 140,
360 and 560 can be for example by finite state machine (finite state machine, FSM) implementation, and but not limited to this.
In the computing architecture 100 of floating point arithmetic circuit, 140 system of control circuit (1) responds multiplying order and controls multiplication
Circuit 110 carries out operation (corresponding step S210~S230)；(2) response product accumulation method operational order controls mlultiplying circuit 110
And add circuit 130 carry out operation and control selections circuit 120 select product D_r rather than product D (corresponding step S210~
S250, S270~S280)；And (3) response fusion product accumulation method operational order controls mlultiplying circuit 110 and add circuit
130 carry out operations and control selections circuit 120 select product D rather than product D_r (corresponding step S210~S240, S260~
S280)。
In the detecting structure 300 of floating point arithmetic circuit, 360 system of control circuit (1) responds multiplying order control detecting
Circuit 310 is detected (corresponding step S410~S420)；(2) response fusion product accumulation method operational order controls circuit for detecting
320 are detected (corresponding step S410, S430) and the selection of control selections circuit 350 (R_sp2, flag2) (corresponding step
S460,S480)；And (3) response product accumulation method operational order control circuit for detecting 310 and circuit for detecting 330 are detected
(corresponding step S410~S420, S440~S450) and control selections circuit 350 select (R_sp3, flag3) (corresponding step
S460~S470).
In the detecting structure 500 of floating point arithmetic circuit, 560 system of control circuit (1) responds multiplying order control detecting
Circuit 510 is detected (corresponding step S610~S620) and control selections circuit 550 selects (R_sp1, flag1) (corresponding
Step S640~S650)；(2) response fusion product accumulation method operational order control circuit for detecting 520 is detected (corresponding step
S610, S630) and the selection of control selections circuit 550 (R_sp2, flag2) (corresponding step S640, S660)；And (3) response
Product accumulation method operational order control circuit for detecting 510 and circuit for detecting 530 detected (corresponding step S610~S620,
S670~S690).
Two embodiments of present invention proposition floating point arithmetic circuit: (1) combination of Fig. 1 and Fig. 3 (corresponding diagram 2 and Fig. 4's
Process)；And the combination (process of corresponding diagram 2 and Fig. 6) of (2) Fig. 1 and Fig. 5.Two embodiments all integrate multiplying, product
Summation operation and fusion product accumulation method operation simultaneously simultaneously optimize three, therefore floating point arithmetic electricity of the invention
Road can promote the efficiency of processor in the processing of these three operations and simplify circuit.It is worth noting that, of the invention
The computing architecture 100 of floating point arithmetic circuit can complete the general calculating of floating number, or collocation others with independent work
Detecting structure general is calculated and the detecting of the particular value of floating point arithmetic with complete floating number together.Similarly, floating number is transported
The detecting structure 300 and 500 for calculating circuit also can be with independent work or other computing architectures of arranging in pairs or groups.
Due to the art, tool usually intellectual can understand this case by the disclosure of the device inventions of this case
Method invention implementation detail and variation, therefore, to avoid superfluous text, in the exposure requirement for not influencing this method invention and can be real
Under the premise of the property applied, the explanation of repetition gives memorandum herein.Taken off in icon before note that, the shape of component, size, ratio with
And sequence of step etc. is only to illustrate, and is to understand the present invention for the art tool usually intellectual to be used, it is non-to limit
The present invention.Furthermore though preceding embodiment of taking off, by taking double precision as an example, so this is not the limitation to the present invention, and the art personage can
Suitably apply the present invention to other precision according to the exposure of the present invention.
Although embodiments of the present invention are as described above, however those embodiments not are used to limit the present invention, this technology neck
Domain tool usually intellectual can express according to the present invention or implicit content imposes variation to the technical characteristic of the present invention, it is all this
Many variations may belong to the sought patent protection scope of the present invention, and in other words, the scope of patent protection of the present invention must regard
Subject to the claim institute defender of this specification.
Symbol description
The computing architecture of 100 floating point arithmetic circuits
110 mlultiplying circuits
112,132 reconditioning circuit
120,350,550 selection circuit
130 add circuits
140,360,560 control circuit
300, the detecting structure of 500 floating point arithmetic circuits
310,320,330,510,520,530 circuit for detecting
340,540 and collector
S210~S280, S410~S480, S610~S690 step.
Claims (10)
1. a kind of floating point arithmetic circuit, for carrying out one to one first operand, one second operand and a third operand
The operation of product accumulation method or a product accumulation method operation are merged, or one is carried out to first operand and second operand and is multiplied
Method operation, which includes:
One mlultiplying circuit receives first operand and second operand, to first operand and second operand into
The row multiplying is to generate not trimmed product and a trimmed product；
One selection circuit couples the mlultiplying circuit, for receiving the not trimmed product and the trimmed product, and exports this not
Trimmed product and trimmed one of the product；
One control circuit couples the selection circuit, and when the floating point arithmetic circuit executes the product accumulation method operation, control should
Selection circuit exports the trimmed product, and when the floating point arithmetic circuit executes the fusion product accumulation method operation, control
It makes the selection circuit and exports the not trimmed product；And
One add circuit couples the selection circuit, receive one of the not trimmed product and the trimmed product and
One of the not trimmed product and the trimmed product are added by the third operand with the third operand, with
To an operation result, wherein the operation result is the fusion product accumulation method operation or the result of the product accumulation method operation；
Wherein, total input digit of the add circuit is greater than twice of first operand, the second operand or third operand
Digit.
2. floating point arithmetic circuit as described in claim 1, wherein the floating point arithmetic circuit is acted according to a clock, this multiplies
Method circuit operation is in a first stage and occupies at least period of the clock, which operates in a second stage and account for
With an at least period for the clock, and the second stage was located at after the first stage.
3. floating point arithmetic circuit as claimed in claim 2, wherein the add circuit receives third fortune in the first stage
Calculate member.
4. floating point arithmetic circuit as claimed in claim 2, wherein it is trimmed in the first stage to generate this for the mlultiplying circuit
Product.
5. floating point arithmetic circuit as claimed in claim 2, wherein the selection circuit is a first choice circuit, the floating number
Computing circuit also includes:
One first circuit for detecting receives first operand and second operand in the first stage, and in the first stage
One first detecting result and one first flag are generated according to first operand and second operand, wherein the first detecting knot
Fruit and first flag correspond to the multiplying；
One second circuit for detecting receives first operand, second operand and the third operand in the first stage, and
One second detecting result and one is generated according to first operand, second operand and the third operand in the first stage
Second flag, wherein second detecting result and second flag correspond to the fusion product accumulation method operation；
One third circuit for detecting couples first circuit for detecting and second circuit for detecting, in the second stage receive this first
Detecting result and the third operand, and one the is generated according to first detecting result and the third operand in the second stage
Three detecting results and an intermediate flag；
Collector together couples first circuit for detecting and the third circuit for detecting, is used among according to first flag and this
Flag generates a third flag, and wherein the third flag is first flag and the union of the intermediate flag, and the third is detected
As a result and the third flag corresponds to the product accumulation method operation；And
One second selection circuit, couple second circuit for detecting, the third circuit for detecting and should and collector, receive this and second detect
Survey result, second flag, the third detecting result and the third flag；
Wherein, which is also coupled to second selection circuit, when the floating point arithmetic circuit executes the fusion product accumulation
When method operation, controls second selection circuit and export second detecting result and second flag, and work as the floating point arithmetic
When circuit executes the product accumulation method operation, controls second selection circuit and export the third detecting result and the third flag.
6. floating point arithmetic circuit as claimed in claim 2, wherein the selection circuit is a first choice circuit, the floating number
Computing circuit also includes:
One first circuit for detecting receives first operand and second operand in the first stage, and in the first stage
One first detecting result and one first flag are generated according to first operand and second operand, wherein the first detecting knot
Fruit and first flag correspond to the multiplying；
One second circuit for detecting receives first operand, second operand and the third operand in the first stage, and
One second detecting result and one is generated according to first operand, second operand and the third operand in the first stage
Second flag, wherein second detecting result and second flag correspond to the fusion product accumulation method operation；
One second selection circuit couples first circuit for detecting and second circuit for detecting, receive first detecting result, this
One flag, second detecting result and second flag；
One third circuit for detecting couples first circuit for detecting and second circuit for detecting, in the second stage receive this first
Detecting result and the third operand, and one the is generated according to first detecting result and the third operand in the second stage
Three detecting results and an intermediate flag；And
Collector together couples first circuit for detecting and the third circuit for detecting, is used among according to first flag and this
Flag generates a third flag, and wherein the third flag is first flag and the union of the intermediate flag, and the third is detected
As a result and the third flag corresponds to the product accumulation method operation；
Wherein, which is also coupled to second selection circuit, when the floating point arithmetic circuit executes the multiplying, control
It makes second selection circuit and exports first detecting result and first flag, and melt when the floating point arithmetic circuit executes this
When rideshare accumulates add operation, controls second selection circuit and export second detecting result and second flag.
7. floating point arithmetic circuit as claimed in claim 6, wherein the control circuit control second selection circuit in this
One stage exported first detecting result and first flag or exported second detecting result and second flag.
8. a kind of floating point arithmetic method, for carrying out one to one first operand, one second operand and a third operand
The operation of product accumulation method or a product accumulation method operation are merged, or one is carried out to first operand and second operand and is multiplied
Method operation, this method include:
Receive first operand and second operand with a mlultiplying circuit, and with the mlultiplying circuit to first operand and
Second operand carries out the multiplying to generate not trimmed product and a trimmed product；
Receive the not trimmed product and the trimmed product with a selection circuit, and export the not trimmed product and this through repairing
One of whole product；
When the product accumulation method operation is performed, controls the selection circuit and export the trimmed product, and when the fusion multiplies
Accumulation add operation is performed, and is controlled the selection circuit and is exported the not trimmed product；And
One of the not trimmed product and the trimmed product and the third operand are received with an add circuit, and
One addition is carried out to one of the not trimmed product and the trimmed product and the third operand with the add circuit
Operation, to obtain an operation result, wherein the operation result is the fusion product accumulation method operation or the product accumulation method operation
Result；
Wherein, total input digit of the add circuit is greater than twice of first operand, the second operand or third operand
Digit.
9. floating point arithmetic method as claimed in claim 8, when wherein the multiplying is implemented in a first stage and occupies
An at least period for clock, the add operation are implemented in a second stage and occupy an at least period for the clock, the second stage
After the first stage, and the selection circuit is a first choice circuit, and this method also includes:
One first detecting result and one first flag are generated according to first operand and second operand in the first stage,
Wherein first detecting result and first flag correspond to the multiplying；
One second detecting result is generated according to first operand, second operand and the third operand in the first stage
And one second flag, wherein second detecting result and second flag correspond to the fusion product accumulation method operation；
One third detecting result and an intermediate flag are generated according to first detecting result and the third operand in the second stage
Mark；
A third flag is generated according to first flag and the intermediate flag, wherein the third flag is in first flag and this
Between flag union, and the third detecting result and the third flag correspond to the product accumulation method operation；
Second detecting result, second flag, the third detecting result and the third flag are received with one second selection circuit；
When the floating point arithmetic method executes the fusion product accumulation method operation, control second selection circuit export this second
Detecting result and second flag；And
When the floating point arithmetic method executes the product accumulation method operation, controls second selection circuit and export third detecting
And the third flag as a result.
10. floating point arithmetic method as claimed in claim 8, when wherein the multiplying is implemented in a first stage and occupies
An at least period for clock, the add operation are implemented in a second stage and occupy an at least period for the clock, the second stage
After the first stage, and the selection circuit is a first choice circuit, and this method also includes:
One first detecting result and one first flag are generated according to first operand and second operand in the first stage,
Wherein first detecting result and first flag correspond to the multiplying；
One second detecting result is generated according to first operand, second operand and the third operand in the first stage
And one second flag, wherein second detecting result and second flag correspond to the fusion product accumulation method operation；
First detecting result, first flag, second detecting result and second flag are received with one second selection circuit；
One third detecting result and an intermediate flag are generated according to first detecting result and the third operand in the second stage
Mark；
A third flag is generated according to first flag and the intermediate flag, wherein the third flag is in first flag and this
Between flag union, and the third detecting result and the third flag correspond to the product accumulation method operation；
When the floating point arithmetic method executes the multiplying, control second selection circuit export first detecting result and
First flag；And
When the floating point arithmetic method executes the fusion product accumulation method operation, control second selection circuit export this second
Detecting result and second flag.
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