CN109765814A - A kind of FPGA IC chip of built-in high speed data converter - Google Patents
A kind of FPGA IC chip of built-in high speed data converter Download PDFInfo
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Abstract
The present invention provides a kind of FPGA IC chips of built-in high speed data converter, including substrate, FPGA module, analog-to-digital conversion module and D/A converter module, FPGA module, analog-to-digital conversion module and D/A converter module are disposed on the substrate, analog-to-digital conversion module and D/A converter module are connected to the I/O interface of FPGA module by high speed digital interface, and high-speed digital signal, analog signal, clock signal, control signal and GPIO signal are drawn out on chip pin by substrate.Built-in high performance analog-to-digital conversion module (ADC) and D/A converter module (DAC), chip size is within 30mm*30mm, while the chip size of also built-in independent DSP is within 40mm*40mm.The present invention can be substantially reduced FPGA and add ADC and the occupied space of DAC module, while because of the raising of integrated level, moreover it is possible to reduce by 20% or more cost.
Description
Technical field
The present invention relates to a kind of FPGA IC chip more particularly to a kind of FPGA collection of built-in high speed data converter
At circuit chip.
Background technique
FPGA (Field-Programmable Gate Array), i.e. field programmable gate array, be PAL, GAL,
The product further developed on the basis of the programming devices such as CPLD, as one of field specific integrated circuit (ASIC) half
Custom circuit and occur, not only solved the deficiency of custom circuit, but overcome original programming device gate circuit number it is limited lack
Point.
Many digital processing systems can all use FPGA, the reason is that FPGA has a large amount of special DSP and blockRAM money
Source can be used to implement parallel and pipelining algorithm.Once executing particular task, FPGA system must be connected with real world
Connect, and it is with analog signal rather than digital signal operates that all engineers, which both know about real world, it means that need using
Analog-digital converter (ADC) or digital analog converter (DAC) are converted between analog signal domain and domain digital signal.Therefore, lead to
In normal situation, FPGA will carry out interface with high performance ADC and DAC.
It is generally free of inside existing FPGA or only performance very low ADC and DAC, engineer is added using FPGA
Have to when ADC and DAC using independent fpga chip, multiple ADC chips and DAC chip.It is needed when these chips are used in conjunction with
It selects the PCB material of higher performance and bigger cost and occupies many spaces, this considers cost and space to many
For more application scenarios, multiple chips are applied in combination on PCB can not meet demand.General FPGA add ADC and
DAC occupies PCB space in 200mm2More than, this is too big for many application scenarios such as handheld device, far beyond
Practical acceptable range.
Summary of the invention
In order to solve above-mentioned this problem, the present invention provides a kind of novel FPGA IC chip, built-in high property
The analog-to-digital conversion module (ADC) and D/A converter module (DAC) of energy, chip size are built-in only within 30mm*30mm, while also
The chip size of vertical DSP is within 40mm*40mm.FPGA can be greatly reduced in this way adds ADC and the occupied sky of DAC module
Between, while because of the raising of integrated level, moreover it is possible to reduce by 20% or more cost.Specific technical solution is as follows:
A kind of FPGA IC chip of built-in high speed data converter, comprising: substrate, FPGA module, analog-to-digital conversion
Module and D/A converter module；FPGA module, analog-to-digital conversion module and the D/A converter module is disposed on the substrate and leads to
High speed digital interface interconnection is crossed, the analog-to-digital conversion module and D/A converter module are connected to by high speed digital interface
The I/O interface of FPGA module, high-speed digital signal, analog signal, clock signal, control signal and GPIO signal are drawn by substrate
Out on chip pin.
Further, the FPGA module include at least 16 groups of 12.5Gb/s high-speed-differential digital interfaces, at least 150 groups
The low speed differential digital interface of 1.6Gb/s.
Further, the high-speed-differential digital interface or be GTX interface, or be GTH interface, low speed differential digital interface
For LVDS interface.
Further, the high speed digital interface or be LVDS interface, or be JESD204B interface, the FPGA module
I/O interface is LVDS I/O interface, or is GTX/GTH I/O interface.
Further, chip size is within 30mm*30mm.
Further, the built-in independent DSP module of at least one set, the DSP module are connected to by high speed digital interface
The I/O interface of FPGA module.
Further, the high speed digital interface is any one of PCI, PCIe, Rapid-IO interface, the FPGA module
I/O interface be any one of LVDS I/O, GTX/GTH I/O interface.
Further, built-in 1 group 32 or 64 DDR cache modules, the DDR cache module pass through DDR3 or DDR4
Bus is connected to the LVDS I/O interface of FPGA module.
Further, chip size is within 40mm*40mm.
A kind of FPGA IC chip of built-in high speed data converter, including substrate, FPGA module, analog-to-digital conversion mould
Block (ADC) and D/A converter module (DAC).FPGA module, analog-to-digital conversion module (ADC) and the D/A converter module
(DAC) it is placed on substrate and is connected with each other by high speed digital interface (LVDS or GTX/GTH), high speed number not interconnected
Word signal, analog signal, clock signal, control signal and GPIO signal etc. are drawn out on chip pin by substrate.
The FPGA module include at least 16 groups of 12.5Gb/s high-speed-differential digital interfaces (GTX/GTH), at least 150 groups
The low speed differential digital interface (LVDS) of 1.6Gb/s.
The analog-to-digital conversion module (ADC) passes through high speed digital interface (LVDS or JESD204B or other high-speed interfaces)
It is connected to the I/O interface (LVDS I/O or GTX/GTH I/O) of FPGA module.The output interface of analog to digital data conversion is
When JESD204B, ADC sampling rate is up to 12 4GSPS or 14 3GSPS or 16 1GSPS；When output interface is LVDS,
ADC sampling rate is up to 12 1000MSPS or 14 400MSPS or 16 250MSPS.
The D/A converter module (DAC) passes through high speed digital interface (LVDS or JESD204B or other high-speed interfaces)
It is connected to the I/O interface (LVDS I/O or GTX/GTH I/O) of FPGA module.The input interface of digital to analogy data conversion is
When JESD204B, DAC sample rate is up to 12 3.3GSPS or 14 2.8GSPS or 16 2.5GSPS；Input interface is LVDS
When, DAC sample rate is up to 12 1000MSPS or 14 1000MSPS or 16 1000MSPS.
The FPGA IC chip, built-in high performance analog-to-digital conversion module (ADC) and D/A converter module
(DAC) chip size is within 30mm*30mm, while the chip size of also built-in independent DSP is within 40mm*40mm.
It can be with built-in 1 group or the independent High Performance DSP module of multiple groups inside FPGA IC chip.The DSP
Module is connect by the I/O that high speed digital interface (PCI or PCIe or Rapid-IO or other high-speed interfaces) is connected to FPGA module
Mouth (LVDS I/O or GTX/GTH I/O), data processing speed is up to fixed point 4800MIPS or more.
It can be with built-in 1 group 32 or 64 DDR cache modules inside FPGA IC chip.The DDR is slow
Storing module is connected to the LVDS I/O interface of FPGA module by DDR3 or DDR4 bus, and buffer memory capacity is up to 2GB or more.
General FPGA adds ADC and DAC to occupy PCB space in 200mm2More than, this such as holds many application scenarios and sets
It is too big for standby etc., far beyond practical acceptable range.A kind of novel FPGA IC chip of the invention,
Built-in high performance analog-to-digital conversion module (ADC) and D/A converter module (DAC), chip size is within 30mm*30mm, simultaneously
The chip size of also built-in independent DSP is within 40mm*40mm.
FPGA can be greatly reduced in this way and adds ADC and the occupied space of DAC module, while because of the raising of integrated level,
20% or more cost can also be reduced.
Detailed description of the invention
Fig. 1 is the 30mm*30mm topology layout figure of the embodiment of the present invention 1.
Fig. 2 is the 30mm*30mm chip concept schematic diagram of the embodiment of the present invention 1.
Fig. 3 is the 30mm*30mm chip pin positions and dimensions figure of the embodiment of the present invention 1.
Fig. 4 is the 30mm*30mm chip size figure of the embodiment of the present invention 1.
Fig. 5 is the top view of Fig. 4.
Fig. 6 is the rearview of Fig. 4.
Fig. 7 is the 40mm*40mm topology layout figure of the embodiment of the present invention 2.
Fig. 8 is the 40mm*40mm chip concept schematic diagram of the embodiment of the present invention 2.
Fig. 9 is the 40mm*40mm chip pin positions and dimensions figure of the embodiment of the present invention 2.
Figure 10 is the 40mm*40mm chip size figure of the embodiment of the present invention 2.
Figure 11 is the top view of Figure 10.
Figure 12 is the rearview of Figure 10.
Specific embodiment
The object, technical solutions and advantages of the present invention are understood in order to be more clearly understood, below with reference to embodiment and attached drawing,
The present invention is described in further detail, exemplary embodiment of the invention and its explanation for explaining only the invention, and
It is not as a limitation of the invention.
A kind of FPGA IC chip of built-in high speed data converter, including substrate 1, FPGA module 2, analog-to-digital conversion
Module (ADC) 3 and D/A converter module (DAC) 4.FPGA module 2, analog-to-digital conversion module (ADC) 3 and the digital-to-analogue modulus of conversion
Block (DAC) 4 is placed on substrate 1 and is connected with each other by high speed digital interface (LVDS or GTX/GTH), height not interconnected
Speed digital signal, analog signal, clock signal, control signal and GPIO signal etc. are drawn out on chip pin by substrate 1.
FPGA module 2 include at least 16 groups of 12.5Gb/s high-speed-differential digital interfaces (GTX/GTH), at least 150 groups
The low speed differential digital interface (LVDS) of 1.6Gb/s.Wherein at least 4 groups of 12.5Gb/s high-speed-differential digital interfaces (GTX/GTH)
It is drawn out to spare on SIP chip pin, other are for ADC, DAC, DSP or are drawn out to SIP chip pin.Wherein at least 50
Group 1.6Gb/s low speed differential digital interface (LVDS) be drawn out to it is spare on SIP chip pin, other be used for ADC, DAC, DSP
Or it is drawn out on SIP chip pin.
Analog-to-digital conversion module (ADC) 3 is connected by high speed digital interface (LVDS or JESD204B or other high-speed interfaces)
To the I/O interface (LVDS I/O or GTX/GTH I/O) of FPGA module.The output interface of analog to digital data conversion is
When JESD204B, ADC sampling rate is up to 12 4GSPS or 14 3GSPS or 16 1GSPS；When output interface is LVDS,
ADC sampling rate is up to 12 1000MSPS or 14 400MSPS or 16 250MSPS.
D/A converter module (DAC) is connected to by high speed digital interface (LVDS or JESD204B or other high-speed interfaces)
The I/O interface (LVDS I/O or GTX/GTH I/O) of FPGA module.The input interface of digital to analogy data conversion is
When JESD204B, DAC sample rate is up to 12 3.3GSPS or 14 2.8GSPS or 16 2.5GSPS；Input interface is LVDS
When, DAC sample rate is up to 12 1000MSPS or 14 1000MSPS or 16 1000MSPS.
It is limited to current chip processing technology ability, wouldn't support the ADC/DAC module of higher performance, when the following technique energy
Power is promoted, and the corresponding sampling rate of ADC/DAC can continue to lift up.
Refering to attached drawing 1, a kind of SIP interior layout schematic diagram comprising FPGA, ADC and DAC module, having a size of 30mm*
30mm, with a thickness of 2.5mm or 3mm.SIP chip interior places 1 group of FPGA die, 2 groups or multiple groups ADC and DAC bare die.In chip
Portion's signal connection relationship is shown in attached drawing 2,30mm*30mm chip concept block diagram.ADC and DAC passes through JESD204B (or LVDS) signal
It is connected with FPGA, other signals are drawn out on SIP chip pin.The Pin locations and outer dimension of 30mm*30mm chip are for example attached
Fig. 3.
It can be with built-in 1 group or the independent High Performance DSP module 5 of multiple groups inside FPGA IC chip.The DSP
Module 5 is connected to the I/O of FPGA module 2 by high speed digital interface (PCI or PCIe or Rapid-IO or other high-speed interfaces)
Interface (LVDS I/O or GTX/GTH I/O), data processing speed is up to fixed point 4800MIPS or more.
It can be with built-in 1 group 32 or 64 DDR cache modules inside FPGA IC chip.The DDR is slow
Storing module is connected to the LVDS I/O interface of FPGA module by DDR3 or DDR4 bus, and buffer memory capacity is up to 2GB or more.
Refering to attached drawing 7, a kind of SIP interior layout schematic diagram comprising FPGA, ADC, DAC, DSP and DDR module, having a size of
40mm*40mm, with a thickness of 2.5mm or 3mm.SIP chip interior places 1 group of FPGA die, 4 groups of ADC bare dies, 2 groups of DAC bare dies, 2
Group DSP bare die and 4 DDR3 chips.Chip interior signal connection relationship is shown in attached drawing 8.ADC and DAC passes through LVDS signal and FPGA
It is connected, DSP is connected by pci signal with FPGA, and DDR is connected by 64BIT DDR3 bus with FPGA, other signals are drawn out to
On SIP chip pin, refering to attached drawing 9.
Claims (9)
1. a kind of FPGA IC chip of built-in high speed data converter characterized by comprising substrate, FPGA module,
Analog-to-digital conversion module and D/A converter module；FPGA module, analog-to-digital conversion module and the D/A converter module is arranged in base
It is connected with each other on plate and by high speed digital interface, the analog-to-digital conversion module and D/A converter module are connect by high-speed figure
Mouth is connected to the I/O interface of FPGA module, and high-speed digital signal, analog signal, clock signal, control signal and GPIO signal are logical
Substrate is crossed to be drawn out on chip pin.
2. a kind of FPGA IC chip of built-in high speed data converter according to claim 1, which is characterized in that
It include: the FPGA module include at least 16 groups of 12.5Gb/s high-speed-differential digital interfaces, at least 150 groups of 1.6Gb/s' is low
Fast differential digital interface.
3. a kind of FPGA IC chip of built-in high speed data converter according to claim 2, which is characterized in that
Include: the high-speed-differential digital interface or for GTX interface, or be GTH interface, low speed differential digital interface connects for LVDS
Mouthful.
4. a kind of FPGA IC chip of built-in high speed data converter according to claim 1, which is characterized in that
Include: the high speed digital interface or for LVDS interface, or be JESD204B interface, the I/O interface of the FPGA module or
It for LVDS I/O interface, or is GTX/GTH I/O interface.
5. a kind of FPGA IC chip of built-in high speed data converter according to any one of claim 1 to 4,
It is characterised by comprising: chip size is within 30mm*30mm.
6. a kind of FPGA IC chip of built-in high speed data converter according to claim 1, which is characterized in that
It include: built-in at least one set of independent DSP module, the DSP module is connected to FPGA module by high speed digital interface
I/O interface.
7. a kind of FPGA IC chip of built-in high speed data converter according to claim 6, which is characterized in that
It include: the high speed digital interface is any one of PCI, PCIe, Rapid-IO interface, the I/O interface of the FPGA module
For any one of LVDS I/O, GTX/GTH I/O interface.
8. according to claim 1 to a kind of FPGA integrated circuit of built-in high speed data converter described in any one of 4,6,7
Chip characterized by comprising built-in 1 group 32 or 64 DDR cache modules, the DDR cache module pass through DDR3
Or DDR4 bus is connected to the LVDS I/O interface of FPGA module.
9. a kind of FPGA IC chip of built-in high speed data converter according to claim 8, which is characterized in that
It include: chip size within 40mm*40mm.
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| CN112054867A (en) * | 2020-08-30 | 2020-12-08 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Large-scale digital array signal synchronous acquisition system |
| CN113126878A (en) * | 2021-03-20 | 2021-07-16 | 北京轩宇空间科技有限公司 | Programmable signal processing module based on SiP |
| CN113451291A (en) * | 2021-06-19 | 2021-09-28 | 中国电子科技集团公司第五十八研究所 | High-bandwidth digital signal processing SiP circuit device based on FPGA and AD/DA converter |
| CN117294751A (en) * | 2023-11-24 | 2023-12-26 | 浙江大学 | Transmission system, transmission method, communication equipment and medium of JESD204C interface compatible with SIP architecture |
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Application publication date: 20190517 Assignee: Zhejiang Weigu Information Technology Co.,Ltd. Assignor: SHANGHAI V&G INFORMATION TECHNOLOGY CO.,LTD. Contract record no.: X2024980016641 Denomination of invention: A FPGA integrated circuit chip with built-in high-speed data converter Granted publication date: 20240709 License type: Common License Record date: 20240929 |