CN109755319B - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Download PDF

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Publication number
CN109755319B
CN109755319B CN201811042219.2A CN201811042219A CN109755319B CN 109755319 B CN109755319 B CN 109755319B CN 201811042219 A CN201811042219 A CN 201811042219A CN 109755319 B CN109755319 B CN 109755319B
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region
fin
fin structure
gate
semiconductor device
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CN201811042219.2A
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CN109755319A (en
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金成玟
金洞院
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

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Abstract

There is provided a semiconductor device including: a substrate; a fin structure protruding from the substrate in a direction perpendicular to the upper surface of the substrate, the fin structure including a first fin region extending in a first direction and a second fin region extending in a second direction different from the first direction; source/drain regions disposed on the fin structure; a gate structure intersecting the fin structure; a first contact connected to one of the source/drain regions; and a second contact connected to the gate structure and located between the second fin regions in a plan view.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips
The present application claims priority from korean patent application No. 10-2017-0147238 filed on the korean intellectual property office at 11.7 and korean patent application No. 10-2017-0165794 filed on the korean intellectual property office at 5.12.2017, the disclosures of which are incorporated herein by reference in their entireties.
Technical Field
Example embodiments of the inventive concepts relate to a semiconductor device, and more particularly, to a semiconductor device capable of reducing parasitic capacitance and short-circuit faults.
Background
The semiconductor devices are divided into memory devices storing data and logic devices such as processors processing data. With the increasing demand for miniaturized, high-performance, low-power semiconductor devices, semiconductor devices having a three-dimensional (3D) structure have been developed. With the increase in density and decrease in critical dimensions of these miniaturized 3D semiconductor devices, parasitic capacitance between interconnects and possible short circuit faults may increase without proper structural design, resulting in reduced performance or failure of the semiconductor devices.
Disclosure of Invention
According to example embodiments of the inventive concepts, a semiconductor device includes a substrate, a first fin structure, a source/drain region, a gate structure, a first contact, and a second contact. The first fin structure protrudes from the substrate in a direction perpendicular to an upper surface of the substrate and includes a first fin region and a second fin region. The first fin region extends in a first direction. The second fin region extends in a second direction different from the first direction. The source/drain regions are disposed on the first fin structure. The gate structure intersects the first fin structure. The first contact is connected to one of the source/drain regions. The second contact is connected to the gate structure and is located between the second fin regions in a plan view.
According to example embodiments of the inventive concepts, a semiconductor device includes a substrate, first and second fin structures, a gate structure, and a gate contact. The substrate includes a first region and a second region. The first fin structure and the second fin structure extend in a first direction parallel to the upper surface of the substrate in the first region and the second region to be spaced apart from each other. The gate structure intersects at least one of the first fin structure and the second fin structure. A gate contact is connected to the gate structure. The distance between the first fin structure and the second fin structure in the first region is smaller than the distance between the first fin structure and the second fin structure in the second region. The gate contact is disposed between the first fin structure and the second fin structure in the second region in a plan view.
According to example embodiments of the inventive concepts, a semiconductor device includes a substrate, a first fin structure, a second fin structure, a gate structure, and a gate contact. The substrate includes an isolation region and an active region. The isolation region includes a first isolation region and a second isolation region. The active region includes a first active region and a second active region separated by an isolation region. The first fin structure is located in the first active region. The second fin structure is located in the second active region. The gate structure intersects the first fin structure. A gate contact is connected to the gate structure and is located on a boundary between the first active region and the second isolation region. The first fin structure includes a first fin region and a second fin region. The first fin region extends in a first direction. The second fin region connects the first fin region and extends in a second direction different from the first direction.
Drawings
Example embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
fig. 1 is a plan view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;
FIG. 2 is a cross-sectional view taken along line I-I' of FIG. 1;
FIG. 3 is a cross-sectional view taken along line II-II' of FIG. 1;
FIG. 4 is a cross-sectional view taken along line III-III' of FIG. 1;
FIG. 5 is a cross-sectional view taken along line IV-IV' of FIG. 1;
fig. 6 is a plan view illustrating a semiconductor device according to an example embodiment of the inventive concepts;
fig. 7 is a plan view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;
FIG. 8 is a cross-sectional view taken along line V-V' of FIG. 7;
FIG. 9 is a cross-sectional view taken along line VI-VI' of FIG. 7;
fig. 10 is a plan view illustrating a semiconductor device according to an example embodiment of the inventive concepts;
FIG. 11 is a cross-sectional view taken along line VII-VII' of FIG. 10;
fig. 12 to 28 illustrate a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.
Because the drawings in fig. 1-28 are intended for illustrative purposes, the elements in the drawings are not necessarily drawn to scale. For example, some elements may be exaggerated or exaggerated for clarity.
Detailed Description
Various example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the present application.
Fig. 1 is a plan view of a semiconductor device illustrating an exemplary embodiment of the inventive concept. Fig. 2 to 5 are sectional views taken along the line I-I ', the line II-II', the line III-III 'and the line IV-IV' of fig. 1, respectively.
Referring to fig. 1 and 2, a semiconductor device 100 includes a fin structure (e.g., a first fin structure 110A and a second fin structure 110B) and a gate structure 130. The first fin structure 110A and the second fin structure 110B may extend in the first direction X and may be spaced apart from each other in the second direction Y. The first direction X may be perpendicular to the second direction Y. The gate structure 130 may extend in the second direction Y and may intersect the first fin structure 110A and the second fin structure 110B. The first fin structure 110A and the second fin structure 110B may protrude from the semiconductor substrate 101 in a direction perpendicular to the upper surface of the semiconductor substrate 101. Although two pairs of first and second fin structures 110A and 110B are disposed on the semiconductor substrate 101 (as shown in fig. 1 to 5), the inventive concept is not limited thereto. For example, more than two pairs of first fin structures 110A and second fin structures 110B may be disposed on the semiconductor substrate 101. For example, the plurality of second fin structures may extend parallel to each other in the first direction X. Optionally, a first fin structure 110A and/or a second fin structure 110B may be disposed on the semiconductor substrate 101.
The region including the first fin structure 110A and the second fin structure 110B is defined as an active region (e.g., as a first active region ACT1 and a second active region ACT2, respectively). The isolation region ISO may be disposed between the first active region ACT1 and the second active region ACT2, and separates the first active region ACT1 and the second active region ACT 2. For example, the semiconductor substrate 101 may include first and second active regions ACT1 and ACT2 and an isolation region ISO. The isolation region ISO may include an insulating material. In example embodiments of the inventive concepts, the first active region ACT1 and the second active region ACT2 may include different types of impurities, and thus may include different types of transistors. For example, the first active region ACT1 may include a p-channel metal oxide semiconductor (PMOS) transistor, and the second active region ACT2 may include an n-channel metal oxide semiconductor (NMOS) transistor.
In example embodiments of the inventive concepts, at least one of the first fin structure 110A and the second fin structure 110B may include a first fin region F1 extending in a first direction X and a second fin region F2 extending in a direction different from the first direction X. As shown in fig. 1, the first fin structure 110A in the first active region ACT1 may include a first fin region F1 and a second fin region F2.
The second fin regions F2 may be disposed between adjacent first fin regions F1 and may connect the first fin regions F1 located at different position levels in the second direction Y. The second fin region F2 may not extend in the first direction X but may extend in a direction inclined at a predetermined angle with respect to the first direction X. The first fin structure 110A including such first and second fin regions F1 and F2 may be formed by an Extreme Ultraviolet (EUV) lithography process.
The semiconductor device 100 includes first contacts 150A and 150B and second contacts 160A and 160B. First contacts 150A and 150B may be connected to source/drain regions 120A and 120B, respectively, as shown in fig. 2. The first contacts 150A and 150B may be referred to as source/drain contacts. The second contacts 160A and 160B may be connected to the gate structure 130. The second contacts 160A and 160B may be referred to as gate contacts. As the size of the semiconductor device 100 decreases and the integration thereof increases, the distance between the first contacts 150A and 150B and the second contacts 160A and 160B may decrease. Accordingly, parasitic capacitance between the first contacts 150A and 150B and the second contacts 160A and 160B may increase, and a short circuit fault between the first contacts 150A and 150B and the second contacts 160A and 160B may occur due to a process fault.
According to example embodiments of the inventive concepts, the above-described problems may be solved because the second fin region F2 is formed in at least one of the first fin structure 110A and the second fin structure 110B. That is, as shown in fig. 1, the first fin structure 110A includes a first fin region F1 and a second fin region F2, and the first fin structure 110A may have a shape that bends some portions in a predetermined direction. Accordingly, the first contact 150A connected to the source/drain region 120A on the second fin region F2 may be located at a position level different from a position level of the first contact 150A connected to the source/drain region 120A on the first fin region F1 in the second direction Y. For example, two source/drain regions 120A may be disposed at opposite sides of the gate structure 130, wherein the two source/drain regions 120A may be disposed at different position levels in the second direction Y. In addition, the first contact 150A connected to the source/drain region 120A on the second fin region F2 at one side of the gate structure 130 may be located at the same level in the second direction Y as the first contact 150A connected to the source/drain region 120A on the second fin region F2 at the other side of the gate structure 130. Accordingly, the second contact 160A may be connected to the gate structure 130 and may be disposed between the second fin regions F2 in a plan view.
The curved shape of the first fin structure 110A may allow the first contact 150A to be offset in its position in the second direction Y and away from the second contact 160A. The first contact 150A and the second contact 160A adjacent thereto on the second fin region F2 may have a reduced facing area (or reduced lateral overlap area) therebetween. Accordingly, a short-circuit fault in which the first contact 150A and the second contact 160A are short-circuited can be prevented or reduced, and parasitic capacitance between the first contact 150A and the second contact 160A can be minimized.
The gate structure 130 is divided by a gate separation pattern CT. The gate separation pattern CT may be disposed on the isolation region ISO and may extend into the lower insulating layer 103 surrounding the first and second fin structures 110A and 110B. The first active region ACT1 and the second active region ACT2 may be defined by an isolation layer 102 in the isolation region ISO. The lower insulating layer 103 may be disposed between adjacent first fin structures 110A and between adjacent second fin structures 110B.
Source/drain regions 120A and 120B may be disposed at opposite sides of gate structure 130, wherein source/drain region 120A may be disposed on first active region ACT1 and source/drain region 120B may be disposed on second active region ACT2. The source/drain regions 120A and 120B may have a polygonal shape as shown in fig. 2. But the inventive concept is not so limited. For example, the source/drain regions 120A and 120B may have various shapes such as a circular shape or a rectangular shape.
Source/drain regions 120A and 120B may be disposed on the first fin structure 110A and the second fin structure 110B, respectively, and may have a merged structure or a combined structure. As shown in fig. 1 and 2, one or both of the source/drain regions 120A and 120B may be connected to the respective two first fin structures 110A and second fin structures 110B, but the inventive concept is not limited thereto. For example, the number of first fin structures 110A and second fin structures 110B connected to each of the source/drain regions 120A and 120B may be variously changed. For example, the source/drain regions 120A may be connected to more than two first fin structures 110A of the plurality of first fin structures 110A and/or the source/drain regions 120B may be connected to more than two second fin structures 110B of the plurality of second fin structures 110B. Alternatively, source/drain regions 120A may be connected to a first fin structure 110A and/or source/drain regions 120B may be connected to a second fin structure 110B.
The material forming the source/drain regions 120A and 120B may vary depending on the kind of the semiconductor device 100. In example embodiments of the inventive concepts, the PMOS transistor in the first active region ACT1 may include silicon germanium (SiGe), and the NMOS transistor in the second active region ACT2 may include silicon (Si).
Source/drain region 120A includes a first layer 121A and a second layer 122A, and source/drain region 120B includes a first layer 121B and a second layer 122B. First layers 121A and 121B may be grown from first fin structure 110A and second fin structure 110B, respectively. The second layers 122A and 122B may be grown from the first layers 121A and 121B, respectively. Source/drain regions 120A and 120B may include n-type impurities or p-type impurities. In example embodiments of the inventive concepts, the source/drain regions 120A and 120B may include different impurity doping concentrations.
Source/drain regions 120A and 120B may be connected to first contacts 150A and 150B, respectively. The gate structure 130 may be connected to the second contacts 160A and 160B. Referring to fig. 2 to 5, the first contact 150A includes a first contact layer 151A and a second contact layer 152A, and the first contact 150B includes a first contact layer 151B and a second contact layer 152B. In example embodiments of the inventive concepts, the first contact layers 151A and 151B may be barrier metal layers acting as diffusion barriers, and the second contact layers 152A and 152B may be filler metal layers having low resistivity. The first contact layers 151A and 151B may include, for example, titanium nitride (TiN), tantalum nitride (TaN), and/or tungsten nitride (WN). The second contact layers 152A and 152B may include, for example, tungsten (W), aluminum (Al), and/or molybdenum (Mo). The second contacts 160A and 160B may have a structure similar to that of the first contacts 150A and 150B, respectively, and/or may include a material similar to that of the first contacts 150A and 150B, respectively.
In example embodiments of the inventive concepts, a metal silicide layer 145 may be disposed between each of the source/drain regions 120A and 120B and each of the first contacts 150A and 150B. The metal silicide layer 145 may be formed by a reaction between silicon and one of, for example, titanium (Ti), cobalt (Co), nickel (Ni), tungsten (W), copper (Cu), tantalum (Ta), platinum (Pt), hafnium (Hf), molybdenum (Mo), radium (Ra), and alloys thereof. The metal silicide layer 145 may be formed on a portion or the entire upper surface of the upper surface of each of the source/drain regions 120A and 120B, and may be formed by depositing a metal on the source/drain regions 120A and 120B and annealing the metal.
The first contacts 150A and 150B may extend into the source/drain regions 120A and 120B, respectively. Source and drain regions 120A and 120B may be formed by epitaxial growth using first fin structure 110A and second fin structure 110B, respectively, as a seed. After forming the first interlayer insulating layer 171 on the source/drain regions 120A and 120B, the first interlayer insulating layer 171 may be etched, and then the source/drain regions 120A and 120B may be recessed by a predetermined depth, so that a trench may be formed. The first contacts 150A and 150B may be formed by filling the trenches with a conductive material. Accordingly, the first contacts 150A and 150B may extend into the source/drain regions 120A and 120B, respectively, at a predetermined depth.
A second interlayer insulating layer 172 is disposed on the first interlayer insulating layer 171 to cover the first contacts 150A and 150B and the gate structure 130. The first interlayer insulating layer 171 and the second interlayer insulating layer 172 may constitute an interlayer insulating layer 170. In example embodiments of the inventive concepts, the second contacts 160A and 160B may penetrate the second interlayer insulating layer 172 to be connected to the gate structure 130. For example, the second contacts 160A and 160B may be formed by etching the second interlayer insulating layer 172 to form a trench exposing the gate structure 130 and filling the trench with a conductive material. In example embodiments of the inventive concepts, the second contacts 160A and 160B may be located at a higher level than the first contacts 150A and 150B with respect to the upper surface of the semiconductor substrate 101 (see, e.g., the second contact 260A and the first contact 250A of fig. 8).
Referring to fig. 2, a first contact 150A connected to the first fin structure 110A including the first fin region F1 and the second fin region F2 is connected to the power line PL and the circuit pattern P0 through vias (e.g., a lower via V0 and an upper via V1). Since the first contact 150A may be connected to the source/drain region 120A (as shown in fig. 2), the source/drain region 120A may be connected to the power line PL. The lower and upper vias V0 and V1 and the circuit pattern P0 may be covered by the second interlayer insulating layer 172 and the inter-metal insulating layer IML. For example, the lower via V0 may be disposed in the second interlayer insulating layer 172, and may be at the same level as the second contacts 160A and 160B. The upper via V1 may be disposed in the inter-metal insulating layer IML. In example embodiments of the inventive concepts, the first fin structure 110A including the first fin region F1 and the second fin region F2 may be bent toward the power line PL in a plan view. In a plan view, the first contact 150A on the second fin region F2 may be closer to the power line PL than the first contact 150A on the first fin region F1. Accordingly, the first contact 150A on the second fin region F2 can be easily connected to the power line PL.
Referring to fig. 3 to 5, the gate structure 130 includes a gate insulating layer 131, a first gate metal layer 132, a second gate metal layer 133, and a cap layer 134 sequentially stacked on the semiconductor substrate 101. A gate insulating layer 131 may be disposed between each of the first and second fin structures 110A and 110B and the first gate metal layer 132. The cap layer 134 may be disposed on the gate insulating layer 131, the first gate metal layer 132, and the second gate metal layer 133, and may include an insulating material, for example, silicon nitride (Si 3N 4). The gate spacer 140 is disposed on sidewalls of the gate structure 130 and may also include an insulating material, for example, silicon oxide (SiO 2), silicon nitride (Si 3N 4), and/or silicon oxynitride (SiON). Source/drain regions 120A and 120B may be disposed at the outer sides of gate spacers 140.
The first fin structure 110A may include a lower fin region 111A and an upper fin region 112A. The gate structure 130 may cover the upper fin region 112A and may extend in the second direction Y. The upper fin region 112A may be connected to the semiconductor substrate 101 through the lower fin region 111A and may serve as a channel region of a transistor included in the semiconductor device.
As described above, the first fin structure 110A may include the first fin region F1 and the second fin region F2. Unlike the first fin region F1 extending in the first direction X, the second fin region F2 may not extend in the first direction X. Accordingly, as shown in fig. 1, 3, and 4, the position levels of the first fin structures 110A covered by the adjacent gate structures 130 having the second fin region F2 therebetween may be different from each other in the second direction Y. For example, two adjacent gate structures 130 may overlap the first fin structure 110A at two adjacent first fin regions F1. Thus, the second fin region F2 may be disposed between the two adjacent first fin regions F1, and the two first fin regions F1 located at different position levels may be connected. As shown in fig. 1 and 5, without the second fin structure 110B of the second fin region F2, the position level of the second fin structure 110B covered by the adjacent gate structure 130 in the second direction Y may be the same.
Source/drain regions 120A and 120B and first contacts 150A and 150B may be disposed between adjacent gate structures 130. In example embodiments of the inventive concepts, the first contacts 150A and 150B may at least partially contact the gate spacer 140. Referring to fig. 3 to 5, portions of the upper sidewalls of the first contacts 150A and 150B may contact the sidewalls of the gate spacers 140.
Fig. 6 is a plan view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.
Referring to fig. 6, the semiconductor device 100A includes a plurality of fin structures (e.g., a first fin structure 110A 'and a second fin structure 110B'), a gate structure 130, and a plurality of contacts 150A ', 150B', 160A ', and 160B'. In example embodiments of the inventive concepts, the first contacts 150A 'and 150B' may be connected to source/drain regions on the first fin structure 110A 'and the second fin structure 110B' (see, e.g., 120A and 120B of fig. 2). The second contacts 160A 'and 160B' may be connected to the gate structure 130.
To reduce or prevent parasitic capacitance or short circuit faults between the first contacts 150A ' and 150B ' and the second contacts 160A ' and 160B ', the first fin structure 110A ' may include an inclined portion. For example, the inclined portion of the first fin structure 110A' may extend in a direction different from the first direction X and the second direction Y and be parallel to an upper surface of the semiconductor substrate (see, e.g., 101 of fig. 2). That is, unlike the second fin structure 110B 'extending parallel to the first direction X, the first fin structure 110A' may include an inclined portion that is not parallel to the first direction X. In example embodiments of the inventive concepts, the inclined portion of the first fin structure 110A' may be disposed in the second region A2 of the semiconductor substrate (see, e.g., 101 of fig. 2) including the first region A1 and the second region A2. For example, the first fin structure 110A 'and the second fin structure 110B' may be spaced apart from each other in the first region A1 and the second region A2 in a second direction Y parallel to an upper surface of the semiconductor substrate (see, e.g., 101 of fig. 2). In the first region A1, the first fin structure 110A 'and the second fin structure 110B' may extend in a first direction X crossing the second direction Y and extend in parallel with an upper surface of the semiconductor substrate (see, e.g., 101 of fig. 2). In the second region A2, at least one of the source/drain regions (see, e.g., 120A of fig. 2) is disposed on the sloped portion of the first fin structure 110A'.
In example embodiments of the inventive concepts, the first fin structure 110A' including the first fin region F1 and the second fin region F2 may be bent toward the power line (see, e.g., PL of fig. 2) in the second region A2 in a plan view. For example, in plan view, the first fin region F1 of the first fin structure 110A 'in the second region A2 may be closer to the power line than the first fin region F1 of the first fin structure 110A' in the first region A1 (see, e.g., PL of fig. 2).
The distance between the first fin structure 110A 'and the second fin structure 110B' adjacent to each other in the first region A1 may be smaller than the distance between the first fin structure 110A 'and the second fin structure 110B' adjacent to each other in the second region A2. In fig. 6, a distance between adjacent first and second fin structures 110A 'and 110B' in the first region A1 may be defined as D1, and a distance between adjacent first and second fin structures 110A 'and 110B' in the second region A2 may be defined as D2. The distance D2 may have different values according to the position. As shown in fig. 6, the distance D2 may have a value greater than that of the distance D1.
An isolation region ISO may be disposed between the first fin structure 110A 'and the second fin structure 110B'. The isolation regions ISO may be formed by etching a portion of the semiconductor substrate (see, e.g., 101 of fig. 2) to form trenches and filling the trenches with an insulating material. The isolation region ISO may have a shape corresponding to the first fin structure 110A 'and the second fin structure 110B'. The isolation region ISO may include a first isolation region ISO1 and a second isolation region ISO2 connected to each other in the first direction X, and the first isolation region ISO1 and the second isolation region ISO2 may have different widths in the second direction Y. The first and second isolation regions ISO1 and ISO2 may correspond to the first and second regions A1 and A2, respectively. In example embodiments of the inventive concepts, the width of the second isolation region ISO2 in the second direction Y may be greater than the width of the first isolation region ISO1 in the second direction Y. This is because the second isolation region ISO2 is formed adjacent to the second fin region F2 of the first fin structure 110A'. Similar to the distance D2, the width of the second isolation region ISO2 in the second direction Y may have a different value according to the position.
In plan view, the second contact 160A ' may be disposed between the first fin structure 110A ' and the second fin structure 110B ' in the second region A2. Because the isolation region ISO has a shape corresponding to the first fin structure 110A ' and the second fin structure 110B ', at least a portion of the second contact 160A ' connected to the gate structure 130 may be disposed on (or overlap with) the isolation region ISO (e.g., the second isolation region ISO 2) in a plan view. The second contact 160A' may be disposed on a boundary between the isolation region ISO and the active region defined by the isolation region ISO. A portion of the second contact 160A' may be disposed on the active region and another portion may be disposed on the isolation region ISO. In example embodiments of the inventive concepts, at least a portion of the second contact 160A' disposed on the isolation region ISO may be included in the second region A2.
Fig. 7 is a plan view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 8 is a sectional view taken along line V-V' of fig. 7. Fig. 9 is a cross-sectional view taken along line VI-VI' of fig. 7.
Referring to fig. 7, semiconductor device 200 includes a plurality of fin structures (e.g., first fin structure 210A and second fin structure 210B) and a plurality of contacts 250A, 250B, 260A, and 260B. In example embodiments of the inventive concepts, first contacts 250A and 250B may be connected to source/drain regions on first fin structure 210A and second fin structure 210B, respectively (see, e.g., 120A and 120B of fig. 2). The second contacts 260A and 260B may be connected to the gate structure 230.
First fin structure 210A includes a first fin region F1 and a second fin region F2. The second fin region F2 may be connected with the spaced apart first fin regions F1 at different position levels. The first fin region F1 may extend in the first direction X. The second fin region F2 may extend in a direction different from the first direction X. The second fin region F2 may extend in a direction inclined at a predetermined angle with respect to the first direction X, and may be covered by the gate structure 230.
First fin structure 210A and second fin structure 210B may have different types of impurities, and first fin structure 210A and second fin structure 210B may each function as a channel region of a PMOS transistor and/or an NMOS transistor. The isolation region ISO may be disposed between the first fin structure 210A and the second fin structure 210B, and may have a shape corresponding to the first fin structure 210A and the second fin structure 210B. Because first fin structure 210A includes first fin region F1 and second fin region F2, a distance between first fin structure 210A and second fin structure 210B adjacent to each other with isolation region ISO therebetween may not be constant.
The distance between first fin structure 210A and second fin structure 210B may vary from D1 to D2. Because first fin structure 210A and second fin structure 210B are not parallel to each other in second fin region F2. In the region where the distance between first fin structure 210A and second fin structure 210B is D2, first contact 250A and second contact 260A may not face each other or may have a reduced facing area (or reduced lateral overlap region) therebetween. Accordingly, a short circuit fault between the first contact 250A and the second contact 260A may be reduced or prevented, and parasitic capacitance between the first contact 250A and the second contact 260A may also be minimized.
Referring to fig. 8 and 9, the gate structure 230 includes a gate insulating layer 231, a first gate metal layer 232, a second gate metal layer 233, and a capping layer 234 sequentially stacked on the substrate 201. The gate spacer 240 may be disposed on sidewalls of the gate structure 230 and may include an insulating material. First fin structure 210A includes a lower fin region 211A and an upper fin region 212A. The upper fin region 212A may be covered by the gate structure 230 and may serve as a channel region. The lower fin region 211A may be surrounded by the lower insulating layer 203. The trenches formed in the substrate 201 may be filled with an insulating material to form the isolation layer 202.
Referring to fig. 8, the capping layer 234 may not be disposed in a region in which the gate structure 230 is connected to the second contact 260A. To form the capping layer 234, the gate spacers 240 may be formed in advance, and then the gate insulating layer 231, the first gate metal layer 232, and the second gate metal layer 233 may be filled in a space between the opposite gate spacers 240. Then, portions of the gate insulating layer 231, the first gate metal layer 232, and the second gate metal layer 233 may be removed to form recesses, and then the recesses may be filled with an insulating material such as silicon nitride (Si 3N 4) to form the cap layer 234.
In order to simplify the process of connecting the second contact 260A to the gate structure 230, the gate insulating layer 231, the first gate metal layer 232, and the second gate metal layer 233 may not be removed in the region where the first gate metal layer 232 and the second gate metal layer 233 are connected to the second contact 260A. Thus, a portion of gate structure 230 may not include cap layer 234.
The source/drain region 220A includes a first layer 221A and a second layer 222A. First layer 221A may be a layer grown from first fin structure 210A. The second layer 222A may be grown from the first layer 221A. The second layers 222A formed from different first fin structures 210A may be combined or merged with each other in the second direction Y to form a single source/drain region 220A.
The source/drain region 220A and the gate structure 230 may be covered by a first interlayer insulating layer 271 and a second interlayer insulating layer 272. A second interlayer insulating layer 272 may be disposed on the first interlayer insulating layer 271 to cover the first contact 250A and the gate structure 230. The first contact 250A may penetrate the first interlayer insulating layer 271 and may be connected to the source/drain region 220A. The second contact 260A may penetrate the second interlayer insulating layer 272 and may be connected to the gate structure 230 crossing the first fin region F1 between adjacent second fin regions F2. In example embodiments of the inventive concepts, the second contact 260A may be located at a higher level than that of the first contact 250A with respect to the upper surface of the substrate 201, as shown in fig. 8. The first contact 250A may not be disposed at an opposite side of the second contact 260A (or not laterally overlap the second contact 260A), as shown in fig. 7. This is because source/drain regions 220A are disposed at relatively different position levels in second direction Y due to the shape of first fin structure 210A.
The curved shape of first fin structure 210A may allow first contact 250A to be offset in its position in second direction Y and away from second contact 260A. The first contact 250A and the second contact 260A may be located at different position levels in the second direction Y, and thus, the first contact 250A may not be disposed at opposite sides of the second contact 260A. Accordingly, a short-circuit failure between the first contact 250A and the second contact 260A does not occur, and parasitic capacitance between the first contact 250A and the second contact 260A can be prevented.
Referring to fig. 9, a void VO may be formed under the source/drain region 220A between adjacent first fin structures 210A. In an example embodiment of the inventive concepts, a portion of the void VO may be filled with the interlayer insulating layer 270.
Fig. 10 is a plan view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 11 is a cross-sectional view taken along line VII-VII' of fig. 10.
Referring to fig. 10, a semiconductor device 300 includes a plurality of fin structures (e.g., a first fin structure 310A and a second fin structure 310B), a gate structure 330, and a plurality of contacts 350A, 350B, 360A, and 360B. In example embodiments of the inventive concepts, the first contacts 350A and 350B may be connected to source/drain regions on the first fin structure 310A and the second fin structure 310B (see, e.g., 120A and 120B of fig. 2, but the number of first fin structures 310A and second fin structures 310B shown in fig. 10 may be different). The second contacts 360A and 360B may be connected to the gate structure 330. In the semiconductor device 300 according to an example embodiment of the inventive concepts, each of the first fin structure 310A and the second fin structure 310B is a single fin structure.
The first fin structure 310A may include a first fin region F1 extending in a first direction X and a second fin region F2 extending in a direction different from the first direction X. Referring to fig. 10, the second fin region F2 may extend in a direction inclined at a predetermined angle with respect to the first direction X. Source/drain regions (see, e.g., 120A of fig. 2) may be disposed on the second fin region F2, and first contacts 350A may be disposed on the source/drain regions (see, e.g., 120A of fig. 2), although the inventive concept is not so limited. For example, in example embodiments of the inventive concept, the gate structure 330 may intersect the second fin region F2, and source/drain regions (see 120A of fig. 2) may be disposed on the first fin region F1. For example, the gate structure 330 may intersect at least one of the second fin regions F2 of the first fin structure 310A.
The first fin structure 310A and the second fin structure 310B may include different types of impurities and may each serve as a channel region of a PMOS transistor and/or an NMOS transistor. In example embodiments of the inventive concepts, the isolation region ISO may be disposed separately from the first fin structure 310A and the second fin structure 310B. The isolation region ISO may include an isolation layer 302 (see fig. 11).
Referring to fig. 11, the isolation layer 302 may be formed by filling a trench formed in the substrate 301 with an insulating material. The first fin structure 310A and the second fin structure 310B may each include a respective one of the lower fin regions 311A and 311B and a respective one of the upper fin regions 312A and 312B. The lower fin regions 311A and 311B may be surrounded by the lower insulating layer 303. The upper fin regions 312A and 312B may be covered by the gate structure 330 and may serve as channel regions for transistors included in the semiconductor device 300.
The gate structure 330 includes a gate insulating layer 331, a first gate metal layer 332, a second gate metal layer 333, and a cap layer 334 sequentially stacked on the substrate 301. The first gate metal layer 332 may be a barrier metal layer acting as a diffusion barrier, and the second gate metal layer 333 may be a filler metal layer having low resistivity. The cap layer 334 may include a material different from that of the second interlayer insulating layer 372 thereon. For example, the cap layer 334 may include silicon nitride (Si 3N 4), and the second interlayer insulating layer 372 may include silicon oxide (SiO 2).
As described above, the cap layer 334 may not be disposed in the region where the first and second gate metal layers 332 and 333 are connected to the second contact 360A. Accordingly, referring to fig. 11, the cap layer 334 may not be formed in at least one region in the second direction Y. An upper surface of the second gate metal layer 333 under the second contact 360A may be coplanar with an upper surface of the cap layer 334.
The second contact 360A may include a first contact layer 361A as a barrier metal layer and a second contact layer 362A as a filler metal layer. The first contact layer 361A and the second contact layer 362A of the second contact 360A may include the same structure and material as those of the first contact layer 151A and the second contact layer 152A of the first contact 150A described above. In example embodiments of the inventive concepts, referring to fig. 10 and 11, a portion of the second contact 360A may overlap the isolation region ISO (or vertically overlap the isolation layer 302). The curved shape of the first fin structure 310A may allow the first contact 350A to be offset in its position in the second direction Y and away from the second contact 360A. The first contact 350A on the second fin region F2 and the second contact 360A adjacent thereto may have a reduced or no facing region (or a reduced or no lateral overlap region) therebetween. Accordingly, a short-circuit fault in which the first contact 350A and the second contact 360A are short-circuited can be prevented or reduced, and parasitic capacitance between the first contact 350A and the second contact 360A can be minimized.
Fig. 12 to 28 illustrate a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 12, 13, 15, 17, 19, 21, 23, and 26 are plan views. Fig. 14, 16, 18, 20, 22, 24, 25, 27 and 28 are cross-sectional views taken along lines VIII-VIII ', IX-IX', X-X ', XI' -XI ', XII-XII', XIII-XIII ', XIV-XIV', XV-XV 'and XVI-XVI' of fig. 13, 15, 17, 19, 21, 23 and 26, respectively.
Referring to fig. 12, a semiconductor substrate 101 is patterned to form a plurality of fin structures 110. To pattern the plurality of fin structures 110, an EUV lithography process and/or a conventional lithography process such as an ArF (193 nm) Deep Ultraviolet (DUV) immersion lithography process may be used. The fin structure 110 may be formed to provide a channel region and source/drain regions of a semiconductor transistor, and may include a first fin region F1 extending in a first direction X. The at least one fin structure 110 may further include a second fin region F2 that does not extend in the first direction X. As shown in fig. 12, the first fin region F1 and the second fin region F2 may extend linearly, but the inventive concept is not limited thereto. For example, the first fin region F1 and the second fin region F2 may be curvedly connected at a boundary therebetween.
Referring to fig. 13 and 14, a mask layer M is formed to cover some of the fin structures 110. The mask layer may be formed by a photolithography process. Masking layer M may cover some of fin structures 110 and may expose the remaining ones of fin structures 110.
Referring to fig. 15 and 16, an etching process may be performed using the mask layer M as an etching mask to remove the fin structures 110 except for the first fin structure 110A and the second fin structure 110B. The etching process may be a Reactive Ion Etching (RIE) process. At this time, a portion of the semiconductor substrate 101 may also be removed to form a trench T1, as shown in fig. 16. After the etching process, the mask layer M may be subsequently removed.
Referring to fig. 17 and 18, an insulating material may be deposited on the semiconductor substrate 101 to expose a portion of each of the first fin structure 110A and the second fin structure 110B. Accordingly, the isolation layer 102 is formed to fill the trench T1, and the lower insulating layer 103 is formed to surround at least some of the first fin structure 110A and the second fin structure 110B. The isolation layer 102 and the lower insulating layer 103 may include, for example, silicon oxide (SiO 2).
Referring to fig. 19 and 20, the dummy gate structure 180 and the gate spacer 140 are formed to cross the first fin structure 110A and the second fin structure 110B. The dummy gate structure 180 and the gate spacer 140 may extend in the second direction Y and cover a portion of each of the first fin structure 110A and the second fin structure 110B. The dummy gate structure 180 may include a dummy gate insulating layer 181, a dummy gate layer 182, and a mask pattern layer 183. The dummy gate insulating layer 181 may include, for example, silicon oxide (SiO 2). The dummy gate layer 182 may include, for example, polysilicon.
After forming the insulating material on the dummy gate structure 180, the first fin structure 110A, the second fin structure 110B, and the lower insulating layer 103, the gate spacers 140 are formed by performing an anisotropic etching process thereon, such as a RIE process. The gate spacer 140 may include, for example, silicon oxide (SiO 2), silicon nitride (Si 3N 4), and/or silicon oxynitride (SiON).
Referring to fig. 21 and 22, source/drain regions 120A and 120B may be formed from the first fin structure 110A and the second fin structure 110B, respectively, exposed between adjacent gate spacers 140. After forming the dummy gate structure 180 and the gate spacer 140, the first fin structure 110A and the second fin structure 110B at the outer side of the gate spacer 140 may be selectively removed to form a recess region. The first fin structure 110A and the second fin structure 110B may be etched using the additional mask or mask pattern layer 183 and the gate spacer 140 as an etch mask to form a recess region. After forming the recess region, a curing process may be selectively performed on the surfaces of the recessed first fin structure 110A and second fin structure 110B.
Source/drain regions 120A and 120B may be formed by performing a Selective Epitaxial Growth (SEG) process using recessed first fin structure 110A and second fin structure 110B as seeds. The source/drain regions 120A and 120B may include a semiconductor layer doped with impurities. In example embodiments of the inventive concepts, the source/drain regions 120A and 120B may include or be formed of, for example, silicon (Si) or silicon germanium (SiGe) doped with impurities.
Referring to fig. 23 through 25, the dummy gate structure 180 is replaced with the gate structure 130. The gate separation pattern CT is formed to divide the gate structure 130 into a plurality of portions. In example embodiments of the inventive concepts, the gate separation pattern CT may be formed before the gate structure 130 is formed.
The first interlayer insulating layer 171 may be formed to cover the dummy gate structure 180 and the source/drain regions 120A and 120B before replacing the dummy gate structure 180 with the gate structure 130. In example embodiments of the inventive concepts, an upper surface of the first interlayer insulating layer 171 may be coplanar with an upper surface of the dummy gate structure 180. After forming the first interlayer insulating layer 171, a portion of the dummy gate structure 180 corresponding to the gate separation pattern CT may be removed by an etching process, and an insulating material may fill the region from which the portion of the dummy gate structure 180 is removed, thereby forming the gate separation pattern CT.
When the gate separation pattern CT is formed, the dummy gate structure 180 between the adjacent gate spacers 140 may be removed. In example embodiments of the inventive concepts, after the first interlayer insulating layer 171 is formed, the mask pattern layer 183 of the dummy gate structure 180 may be removed through a Chemical Mechanical Polishing (CMP) process. The gate structure 130 may be formed in the space between the adjacent gate spacers 140 from which the dummy gate structure 180 is removed.
Referring to fig. 24 and 25, the gate structure 130 includes a gate insulating layer 131, a first gate metal layer 132, a second gate metal layer 133, and a cap layer 134 sequentially stacked on the semiconductor substrate 101. The gate insulating layer 131 may be conformally formed along inner surfaces of the spaces between the adjacent gate spacers 140, and may include, for example, oxide, nitride, and/or a high-k dielectric material having a dielectric constant greater than that of silicon oxide (SiO 2). The gate insulating layer 131 may cover the first fin structure 110A and the second fin structure 110B exposed between adjacent gate spacers 140.
The first gate metal layer 132 and the second gate metal layer 133 may include, for example, metal and/or polysilicon. In example embodiments of the inventive concepts, the first gate metal layer 132 and the second gate metal layer 133 may include different materials. The first gate metal layer 132 may serve as a barrier metal layer to prevent metal diffusion, and may include, for example, titanium nitride (TiN). The second gate metal layer 133 may include a metal such as tungsten (W), copper (Cu), and/or molybdenum (Mo), or silicon (Si). In example embodiments of the inventive concepts, an additional metal layer may also be formed between the first gate metal layer 132 and the second gate metal layer 133.
The capping layer 134 may cover the gate insulating layer 131, the first gate metal layer 132, and the second gate metal layer 133, and may include an insulating material, for example, silicon nitride (Si 3N 4). Referring to fig. 24, the cap layer 134 may not be formed in a predetermined region in the second direction Y. For example, cap layer 134 may be divided into multiple portions. In the region where the cap layer 134 is not formed, upper surfaces of the first gate metal layer 132 and the second gate metal layer 133 may be exposed.
Referring to fig. 26 to 28, first contacts 150A and 150B and second contacts 160A and 160B are formed. First contacts 150A and 150B may be connected to source/drain regions 120A and 120B, respectively. The second contacts 160A and 160B may be connected to the gate structure 130.
The first contacts 150A and 150B may be formed by removing a portion of the first interlayer insulating layer 171 by an etching process and filling the removed region with a conductive material. When the etching process is performed on the first interlayer insulating layer 171, portions of the source/drain regions 120A and 120B may also be removed. After the first contacts 150A and 150B are formed, a second interlayer insulating layer 172 may be formed on the first interlayer insulating layer 171. The first and second interlayer insulating layers 171 and 172 may include, for example, silicon oxide (SiO 2), silicon nitride (Si 3N 4), and/or silicon oxynitride (SiON). The first interlayer insulating layer 171 and the second interlayer insulating layer 172 may form an interlayer insulating layer 170. The second contacts 160A and 160B may be formed in a region from which a portion of the second interlayer insulating layer 172 is removed, and may be connected to the gate structure 130. The second contacts 160A and 160B may be formed by removing a portion of the first interlayer insulating layer 171 in a region of the gate structure 130 where the cap layer 134 is not formed by an etching process and filling the removed region with a conductive material.
When the process of forming the first contacts 150A and 150B and the second contacts 160A and 160B is not controlled, a short circuit fault that connects (or shorts) the corresponding one of the first contacts 150A and 150B with the corresponding one of the second contacts 160A and 160B may occur. In addition, when the corresponding one of the first contacts 150A and 150B and the corresponding one of the second contacts 160A and 160B are close to each other, parasitic capacitance therebetween may be increased.
According to example embodiments of the inventive concepts, the above-described problems may be solved by adjusting a shape of at least one of the first fin structure 110A and the second fin structure 110B. As described above with reference to fig. 1 and 12, the first fin structure 110A may include a first fin region F1 and a second fin region F2, and the second fin region F2 may extend in a direction different from the first direction X. Accordingly, the first fin structure 110A may have a curved shape in at least a predetermined portion. The curved shape of the first fin structure 110A may allow the first contact 150A to be offset in its position in the second direction Y and away from the second contact 160A. The first contact 150A and the second contact 160A adjacent thereto on the second fin region F2 may have a reduced facing area (or reduced lateral overlap area) therebetween. Accordingly, a short-circuit fault in which the first contact 150A and the second contact 160A are short-circuited can be prevented or reduced, and parasitic capacitance between the first contact 150A and the second contact 160A can be minimized.
As shown in fig. 26, the source/drain region 120A on the second fin region F2 may be disposed at a different position level in the second direction from the position level of the other source/drain region 120A on the first fin region F1. Accordingly, the first contact 150A may be formed away from the second contact 160A, and a facing area between the first contact 150A and the second contact 160A may be reduced. Accordingly, parasitic capacitance between the first contact 150A and the second contact 160A may be reduced, and short-circuit fault occurrence may be reduced or prevented during formation of the first contact 150A and the second contact 160A. The second contact 160A may be connected to an upper surface of the gate structure 130 exposed in a region where the cap layer 134 is not formed.
While the present inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as set forth in the following claims.

Claims (17)

1. A semiconductor device, the semiconductor device comprising:
a substrate;
a first fin structure protruding from the substrate in a direction perpendicular to the upper surface of the substrate, the first fin structure including a first fin region extending in a first direction and a second fin region connecting the first fin region and extending in a second direction different from the first direction;
The source/drain region is arranged on the first fin structure;
a gate structure intersecting the first fin structure;
a first contact connected to one of the source/drain regions;
a second contact connected to the gate structure, the second contact being located between the second fin regions in plan view,
wherein the substrate comprises an active region and an isolation region,
the isolation region includes a first isolation region and a second isolation region connected to each other and having different widths in a third direction perpendicular to the first direction.
2. The semiconductor device according to claim 1, wherein,
the active region includes a first fin structure,
a portion of the second contact is disposed on the isolation region.
3. The semiconductor device of claim 1, wherein each of the second fin regions of the first fin structure is connected to one of the source/drain regions.
4. The semiconductor device according to claim 3, further comprising power lines on a substrate,
wherein at least one of the source/drain regions is connected to a power line.
5. The semiconductor device of claim 3, wherein the gate structure intersects the first fin region of the first fin structure.
6. The semiconductor device of claim 1, further comprising a plurality of second fin structures,
Wherein the plurality of second fin structures extend parallel to each other in the first direction.
7. The semiconductor device of claim 1, wherein the gate structure intersects at least one of the second fin regions of the first fin structure.
8. The semiconductor device of claim 1, wherein two of the source/drain regions are disposed at opposite sides of the gate structure,
the two source/drain regions are disposed at different positions horizontally in a third direction perpendicular to the first direction.
9. The semiconductor device of claim 1, wherein one of the source/drain regions is connected to at least two of the plurality of first fin structures.
10. The semiconductor device according to claim 1, wherein the second isolation region has a width larger than a width of the first isolation region in the third direction.
11. The semiconductor device of claim 10, wherein at least a portion of the second contact overlaps the second isolation region in a plane.
12. A semiconductor device, the semiconductor device comprising:
a substrate including a first region and a second region connected to each other;
the first fin structure and the second fin structure extend continuously in the first region and the second region to be spaced apart from each other in a first direction parallel to the upper surface of the substrate;
A gate structure intersecting at least one of the first fin structure and the second fin structure;
a gate contact connected to the gate structure,
wherein a distance between the first fin structure and the second fin structure in the first region is smaller than a distance between the first fin structure and the second fin structure in the second region,
the gate contact is disposed in plan view between the first fin structure and the second fin structure in the second region,
in the first region, the first fin structure and the second fin structure extend in a second direction intersecting the first direction and parallel to the upper surface of the substrate,
in the second region, a portion of the first fin structure extends in a third direction different from the second direction and parallel to the upper surface of the substrate.
13. The semiconductor device of claim 12, further comprising source/drain regions disposed on the first fin structure,
wherein, in the second region, at least one of the source/drain regions is disposed on the portion of the first fin structure.
14. The semiconductor device of claim 12, wherein the plurality of gate structures intersect the first fin structure,
at least one of the plurality of gate structures is located on the portion of the first fin structure in the second region.
15. The semiconductor device according to claim 12, further comprising:
a source/drain region disposed on the first fin structure,
a power line disposed on the substrate, the power line connected to at least one of the source/drain regions,
wherein, in plan view, the first fin structure is bent toward the power line in the second region.
16. The semiconductor device according to claim 12, further comprising:
a source/drain region disposed on the first fin structure,
source/drain contacts disposed on the source/drain regions,
wherein some of the source/drain contacts are disposed at different location levels in the first direction.
17. A semiconductor device, the semiconductor device comprising:
the substrate comprises an isolation region and an active region, wherein the isolation region comprises a first isolation region and a second isolation region, and the active region comprises a first active region and a second active region which are separated by the isolation region;
a first fin structure disposed in the first active region;
a second fin structure disposed in the second active region;
a gate structure intersecting the first fin structure;
a gate contact connected to the gate structure, the gate contact disposed on a boundary between the first active region and the second isolation region,
Wherein the first fin structure includes a first fin region and a second fin region,
the first fin region extends in a first direction,
the second fin region connects the first fin region and extends in a second direction different from the first direction.
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