CN109740282A - Chip pin configuration method, device, equipment and medium - Google Patents
Chip pin configuration method, device, equipment and medium Download PDFInfo
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- CN109740282A CN109740282A CN201910038723.3A CN201910038723A CN109740282A CN 109740282 A CN109740282 A CN 109740282A CN 201910038723 A CN201910038723 A CN 201910038723A CN 109740282 A CN109740282 A CN 109740282A
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- 238000012795 verification Methods 0.000 abstract 3
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Abstract
The application discloses a chip pin configuration method, a device, equipment and a medium. The method at least comprises the following steps: displaying a visual pin configuration interface, wherein a plurality of pins of the chip are displayed in the interface in a graph; receiving a configuration instruction of a user for the displayed pins, wherein the configuration instruction specifies attributes to be configured for the pins; and performing feasibility verification according to the configuration instruction, and generating a corresponding configuration file for the chip after the feasibility verification is passed. According to the method and the device, the user can carry out visual operation through the visual pin configuration interface, so that the attributes of the pins can be configured visually and conveniently, and the user can be helped to avoid errors when the attributes are configured based on the feasibility verification carried out automatically.
Description
Technical field
This application involves chip technology field more particularly to a kind of chip pin configuration method and device, equipment, media.
Background technique
Chip, and it is properly termed as integrated circuit, since the over half a century that it occurs, effectively push information industry
Development, play central role in most of electronic equipments.Often be integrated in chip the logic gate of magnanimity, trigger,
Multiplexer and other circuits, the small size of these circuits make chip compared with plate grade is integrated, have higher speed and lower
The characteristic of power consumption, and reduce manufacturing cost.
Chip includes multiple pins, can be configured to the attribute of each pin in chip package, user is referred to
The attribute that each pin is configured uses chip.
In the prior art, research staff is the attribute of the collocation in successive steps chip pin by way of hand-written code.
But existing this scheme excessively depends on the hand-written code ability and careful degree of research staff, it is easy to
There is mistake, can not work normally so as to cause chip.
Summary of the invention
The embodiment of the present application provides a kind of chip pin configuration method and device, equipment, medium, to solve the prior art
In following technical problem: existing chip pin allocation plan excessively depends on the hand-written code ability and carefulness of research staff
Degree, it is easy to mistake occur, can not work normally so as to cause chip.
The embodiment of the present application adopts the following technical solutions:
A kind of chip pin configuration method, comprising:
It shows and visualizes pin configuration interface, multiple pins of chip are illustrated with figure in the interface；
The configuration-direct that user is directed to the pin shown is received, is that the pin specifies institute in the configuration-direct
The attribute to be configured；
Feasibility verifying is carried out according to the configuration-direct, and after the feasibility is verified, is the chip
Generate corresponding configuration file.
Optionally, optional chip can be shown in the interface；
It is illustrated in the interface with figure: the multiple pins for the chip that user selectes from each optional chip, or
The multiple pins for the chip to be configured that person automatically identifies.
Optionally, multiple attributes are illustrated also directed to the chip or its pin in the interface, so that user is directed to
The pin shown selects the attribute to be configured.
Optionally, each pin of the chip, the layout of each pin of displaying are illustrated with figure in the interface
It is consistent with the layout of corresponding material object.
Optionally, the configuration-direct includes sequential multiple configuration sub-instructions；
The method also includes:
According to the user having received for the configuration sub-instructions of the pin shown, to subsequent configuration can be passed through
Sub-instructions are screened for the attribute to be configured that the pin is specified, for selection by the user.
Optionally, the feasibility verifying includes following at least a kind of verifying:
Whether will lead to pin to repeat to configure；Whether pin level configuration error will lead to；Whether will lead between pin
Function is obscured.
Optionally, the format of the configuration file is the data interchange format of lightweight；
After the corresponding configuration file for chip generation, the method also includes:
According to the configuration file, compileable language file accordingly is generated, the chip is used for.
Optionally, the configuration file is JS object tag (JavaScript Object Notation, JSON) file,
Corresponding compileable language file is C language file.
A kind of chip pin configuration device, comprising:
Display module shows and visualizes pin configuration interface, illustrates multiple pins of chip in the interface with figure；
Receiving module, receives the configuration-direct that user is directed to the pin shown, is described draw in the configuration-direct
Foot specifies the attribute to be configured；
Configuration module carries out feasibility verifying according to the configuration-direct, and after the feasibility is verified, is
The chip generates corresponding configuration file.
Optionally, optional chip can be shown in the interface；
It is illustrated in the interface with figure: the multiple pins for the chip that user selectes from each optional chip, or
The multiple pins for the chip to be configured that person automatically identifies.
Optionally, multiple attributes are illustrated also directed to the chip or its pin in the interface, so that user is directed to
The pin shown selects the attribute to be configured.
Optionally, each pin of the chip, the layout of each pin of displaying are illustrated with figure in the interface
It is consistent with the layout of corresponding material object.
Optionally, the configuration-direct includes sequential multiple configuration sub-instructions；
Described device further include:
Screening module, according to the user having received for the configuration sub-instructions of the pin shown, to can pass through
The attribute to be configured that subsequent configuration sub-instructions are specified for the pin is screened, for selection by the user.
Optionally, the feasibility verifying includes following at least a kind of verifying:
Whether will lead to pin to repeat to configure；Whether pin level configuration error will lead to；Whether will lead between pin
Function is obscured.
Optionally, the format of the configuration file is the data interchange format of lightweight；
The configuration module is after the chip generates corresponding configuration file, also to execute:
According to the configuration file, compileable language file accordingly is generated, the chip is used for.
Optionally, the configuration file is JSON file, and corresponding compileable language file is C language file.
A kind of chip pin configuration equipment, comprising:
At least one processor；And
The memory being connect at least one described processor communication；Wherein,
The memory is stored with the instruction that can be executed by least one described processor, and described instruction is by described at least one
A processor executes so that at least one described processor can:
It shows and visualizes pin configuration interface, multiple pins of chip are illustrated with figure in the interface；
The configuration-direct that user is directed to the pin shown is received, is that the pin specifies institute in the configuration-direct
The attribute to be configured；
Feasibility verifying is carried out according to the configuration-direct, and after the feasibility is verified, is the chip
Generate corresponding configuration file.
A kind of chip pin configuring non-volatile computer storage medium is stored with computer executable instructions, the meter
The setting of calculation machine executable instruction are as follows:
It shows and visualizes pin configuration interface, multiple pins of chip are illustrated with figure in the interface；
The configuration-direct that user is directed to the pin shown is received, is that the pin specifies institute in the configuration-direct
The attribute to be configured；
Feasibility verifying is carried out according to the configuration-direct, and after the feasibility is verified, is the chip
Generate corresponding configuration file.
The embodiment of the present application use at least one above-mentioned technical solution can reach following the utility model has the advantages that make user without
Need in a manner of hand-written code configuring chip pin attribute, can by visualize pin configuration interface carry out visualization behaviour
Make, thus attribute that is intuitive and being conveniently arranged pin, and based on the feasibility verifying carried out automatically, help avoid user
Occurs mistake when configuration attribute.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present application, constitutes part of this application, this Shen
Illustrative embodiments and their description please are not constituted an undue limitation on the present application for explaining the application.In the accompanying drawings:
Fig. 1 is a kind of flow diagram for chip pin configuration method that some embodiments of the present application provide；
Fig. 2 is a kind of schematic diagram at visualization pin configuration interface that some embodiments of the present application provide；
The visualization pin configuration realized under a kind of practical application scene that Fig. 3 is provided by some embodiments of the present application
The detailed maps at interface；
Fig. 4 is that a kind of structure for chip pin configuration device corresponding to Fig. 1 that some embodiments of the present application provide is shown
It is intended to；
Fig. 5 is that a kind of structure for chip pin configuration equipment corresponding to Fig. 1 that some embodiments of the present application provide is shown
It is intended to.
Specific embodiment
To keep the purposes, technical schemes and advantages of the application clearer, below in conjunction with the application specific embodiment and
Technical scheme is clearly and completely described in corresponding attached drawing.Obviously, described embodiment is only the application one
Section Example, instead of all the embodiments.Based on the embodiment in the application, those of ordinary skill in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall in the protection scope of this application.
As described in background technique, existing chip pin allocation plan excessively depends on the hand-written generation of research staff
Code ability and careful degree, it is easy to mistake occur.For example, the variable naming of many pin attributes may be much like, people is researched and developed
Member is easy to obscure, and leads to configuration error.Moreover, in chip product iteration, since the attribute of chip pin is also with hand
What the mode of work code was safeguarded, it is equally also easy error when maintenance, influences iteration progress.And the scheme of the application can at least portion
Divide and solves these problems.Here the type of chip is not limited, and the scheme of the application is suitable for a plurality of types of chips, for example, specially
With integrated circuit, field programmable gate array, Complex Programmable Logic Devices etc..
The scheme of the application is described in detail below.
Fig. 1 is a kind of flow diagram for chip pin configuration method that some embodiments of the present application provide.In the stream
Cheng Zhong, for equipment angle, executing subject can be one or more and calculate equipment, for example, controlling to chip package
Server, the chip debugging server etc. of tubulation reason, for program angle, executing subject can correspondingly be mounted in these
The program in equipment is calculated, for example, chip configuration platform, chip design program etc., these programs can be to user (for example, core
The research staff of piece uses the integration of equipments quotient of chip, client etc.) graphic user interface for being used for configuration pin is provided
(Graphical User Interface, GUI) allows user directly to carry out visual configuration to pin, without hand-written generation
Code.
Process in Fig. 1 may comprise steps of:
S102: showing and visualize pin configuration interface, illustrates multiple pins of chip in the interface with figure.
In some embodiments of the present application, the relevant code of pin configuration can be packaged in advance, this will be called
The entrance of a little codes is presented in a manner of patterned to user, then user need not pay close attention to how these codes run, and need to only be passed through
Visualized operation is carried out in visualization pin configuration interface, it is incoming that function is entered ginseng.The visualized operation such as includes:
Figure is clicked, figure is pulled, clicks to select option, drop-down option frame, switching figure visual angle etc..
Visualizing pin configuration interface may include main interface, and the operation based on user in main interface is (for example, cut
Change tabs, drop-down option frame, click control carry out interface jump), other interfaces further shown.
In some embodiments of the present application, for the ease of user's intuitively configuration pin, pin can be shown with figure,
Specific exhibition method can be multiplicity.For example, indicating a pin with one or more drop-down option frame respectively, pass through
Option is selected in drop-down option frame, to configure corresponding pin；For another example, with the figure for directly reflecting chip appearance or structure
Shape indicates chip, indicates the region of pin in the figure by clicking, and to configure the pin, this mode is more intuitive, uses
Family is easier upper hand.
S104: the configuration-direct that user is directed to the pin shown is received, is that the pin refers in the configuration-direct
The attribute to be configured is determined.
In some embodiments of the present application, user by visualization pin configuration interface in carry out visualized operation,
Assign the configuration-direct for pin.The attribute that can be configured such as includes the function of pin, the design parameter for drawing level, function
It such as include that (some functions can also be according to used different agreement into one for ground connection, serial ports, clock, timer etc. Deng, function
The subdivision of step ground), drawing level may include drawing high level, dragging down level etc..
S106: feasibility verifying is carried out according to the configuration-direct, and is described after the feasibility is verified
Chip generates corresponding configuration file.
In some embodiments of the present application, feasibility verifying can be single aspect or various.With regard to single side
For face, such as: on the one hand, can verifying configuration-direct itself, properly whether (configuration-direct is specified multiple for same pin
Whether attribute conflicts, configuration-direct is whether the attribute that different pins are specified is obscured), it is tested if so, feasibility can be considered as
Card passes through, and otherwise, can be considered as feasibility verifying and not pass through；On the other hand, can verify configuration-direct whether can with it is configured
Pin property contradictories, if so, can be considered as feasibility verifying do not pass through, otherwise, feasibility can be considered as and be verified；
If being postponed in another aspect, can verify and match according to configuration-direct, the configurable attribute of other pin scripts not yet configured
It is whether still configurable, it is verified if so, feasibility can be considered as, does not pass through if it is not, feasibility verifying can be considered as, or
After person can also adjust accordingly the configurable attribute for the pin script being not configured, it is considered as feasibility and is verified；Deng
Deng.
In some embodiments of the present application, the configuration file accordingly generated after feasibility is verified be can be
Compileable language file, can be directly used for chip after compiling to it；Alternatively, the data that configuration file is also possible to lightweight are handed over
Formatted file is changed, in this way, being more convenient for successive iterations compared to compileable language file, reconvert is obtained accordingly when need to use
Compileable language file, after compiling be used for chip.The data interchange format of lightweight such as includes JSON, extensible markup language
Say formats such as (Extensible Markup Language, XML).Compileable language such as includes C language, C Plus Plus, compilation
Language etc..
In some embodiments of the present application, if feasibility verifying does not pass through, user can be given and prompted accordingly, with
Just user corrects configuration-direct, alternatively, can also correct configuration-direct automatically and be supplied to user's confirmation.
By the method for Fig. 1, so that attribute of the user without the configuring chip pin in a manner of hand-written code, can pass through
It visualizes pin configuration interface and carries out visualized operation, thus attribute that is intuitive and being conveniently arranged pin, and based on automatic
The feasibility of progress is verified, and helps avoid mistake occur when configuration attribute.
Method based on Fig. 1, some embodiments of the present application additionally provide some specific embodiments of this method, and
Expansion scheme is illustrated below.
It, can be right in the case where the equipment as executing subject is not connected with chip in some embodiments of the present application
The pin configuration process of selected chip carries out analog simulation, can also be connected to the feelings of chip in the equipment as executing subject
Under condition, directly the pin of the chip is configured, to improve user experience.Visualization can open up in pin configuration interface
Show optional chip, so that user selectes the current chip to be configured from these optional chips, more intelligently, visualizes pin
Configuration interface can also automatically be selected from these optional chips current connected independent of the active operation of user
Chip.Based on this, visualizing can be shown in pin configuration interface with figure: the chip that user selectes from each optional chip
Multiple pins, or the multiple pins of chip to be configured automatically identified；This exhibition method intuitive is preferable, facilitates
Prevent user from obscuring error.
In some embodiments of the present application, chip or its pin exhibition can also be directed to by visualizing in pin configuration interface
Show multiple attributes, so that user selects the attribute to be configured for the pin shown.User can first select and draw in configuration
Foot then visualizes the multiple attributes for showing that the pin is configurable in pin configuration interface, and user is yet further in this multiple category
Property in select the attribute to be configured.
For configuring the user of pin of chip, often also the chip material object is known quite well, for example, the chip has
How many pins, layout of the pin on chip is as how.Based on this, can make to show in visualization pin configuration interface with figure
Each pin of chip, and the layout of each pin shown is consistent with the layout of corresponding material object, so, it is possible to reduce user
Practise cost, user can directly continue to use oneself understanding to the chip material object, easily in visualizing pin configuration interface into
Row configuration.
Further, visualizing can also be according to the appearance of chip material object, simulation true as far as possible in pin configuration interface
Show that chip facilitates user and more accurately configure to improve the sense of reality of user.
In some embodiments of the present application, configuration-direct can be an individually instruction, be also possible to a series of
Instruction.For the previous case, for example, configuration-direct can be for one attribute of pin configuration or configure simultaneously multiple categories
Property；For latter situation, for example, configuration-direct such as may include sequential multiple configuration sub-instructions, each configuration
Instruction is successively assigned, and feasibility verifying is also possible to respectively for the configuration sub-instructions execution currently assigned, Ke Yisui
The corresponding feasibility verifying of each configuration sub-instructions pass through, and corresponding configuration file is generated, it is of course also possible in each configuration
After sub-instructions corresponding feasibility verifying passes through, then configuration file is integrally generated, the advantages of latter scheme helps
In reducing the wasting of resources due to caused by user's modification configuration, because user is likely to before whole pin configuration completion
Existing configuration is modified, then generated configuration file is also required to accordingly modify.
In some embodiments of the present application, after user assigns arbitrary disposition sub-instructions, if the configuration sub-instructions execute,
Configurable attribute may be then influenced, causes to be suitble to the attribute selected to become to be no longer appropriate for being selected originally, use in order to prevent
Resulting unsuitable attribute is falsely dropped at family, can be referred to according to the user having received for configuration of the pin shown
Enable, to can by it is subsequent configuration sub-instructions be pin specify the attribute to be configured screen, and then can exhibition
Show the attribute filtered out, for selection by the user.
In some embodiments of the present application, before listed several respects feasibility verifying.More specifically, in office
In the feasibility verifying of one side, in order to cater to the actual demand of user, multinomial particular content can be verified, for example, verifying
Whether will lead to pin to repeat to configure；Whether pin level configuration error will lead to；Whether will lead to function between pin to obscure
Deng.By taking pin level configures as an example, for example, level should be drawn high to it to Mr. Yu's pin, if but being mis-configured to draw
Low level can then be considered as feasibility verifying and not pass through, further, it is assumed that level should be drawn high to it to 12 volts, if but wrong
It accidentally is configured to draw high level to 5 volts, then can also be considered as feasibility verifying and not pass through.
According to explanation above, some embodiments of the present application provide a kind of signal for visualizing pin configuration interface
Figure, as shown in Figure 2.
In fig. 2, it is seen that chip and its pin are shown with figure, user according to the layout of chip material object
Any pin for wanting configuration shown can be clicked, for example, what is currently clicked is the pin of bottom on the left of chip, institute's point
The pin hit is as current pin, and after user clicks pin, visualization pin configuration interface can show matching for current pin
The attribute set, such as 1~N of attribute that left side is shown in Fig. 2, user further clicks selected attribute, matches as current pin
The attribute set, user select attribute after, can directly be shown at pin be the pin configuration attribute, or user again
When clicking the pin, then show be the pin configuration attribute.
Certainly, Fig. 2 briefly schematically shows visualization pin configuration interface, the content and layout in interface
It is not limited to represented by Fig. 2, can there is the pattern of multiplicity.
For example, more intuitively, some embodiments of the present application additionally provide realized under a kind of practical application scene can
Detailed maps depending on changing pin configuration interface, as shown in Figure 3.
In FIG. 3, it is seen that the top on the left of visualization pin configuration interface, selected chip is that some can be compiled
Journey input and output array illustrates the chip and its multiple pins on the right side of interface with figure, illustrates and draw specific illustratively
Foot IO_0~IO_47, the grid where pin name indicate the pin, and the black matrix wrongly written or mispronounced character tag representation in grid has been this
The attribute of pin configuration, for example, being configured with attribute SPI0_D0 for pin IO_0, lower section is illustrated configurable on the left of interface
Pin attribute.
For example, JTAG Test attribute, belongs to JTAG type, if the pin is configured for the attribute, which can be with
It is used as jtag interface；For another example, Debug attribute belongs to DEBUG type, should if the pin is configured for the attribute
Pin can be used as debugging interface use；Etc..
User, can be by selecting chip when utilizing the visualization pin configuration interface configurations chip in Fig. 3, and selection should
The pin of chip selects to be the attribute of the pin configuration, assigns corresponding configuration-direct, then after visualizing pin configuration interface
The logic at end can verify whether pin conflict according to configuration-direct, for example, duplicate pin configuration, the drawing that may be malfunctioned
Level (for example, drawing high level to clock pin configuration drawing level, to ground connection pin configuration) etc., can after being verified
To generate corresponding JSON configuration file, and then C language configuration file can also be generated according to JSON configuration file, be used for core
Piece.
Based on same thinking, some embodiments of the present application additionally provide the corresponding device of the above method, equipment and non-
Volatile computer storage medium.
Fig. 4 is that a kind of structure for chip pin configuration device corresponding to Fig. 1 that some embodiments of the present application provide is shown
It is intended to, dashed rectangle indicates optional module, which includes:
Display module 401 shows visualization pin configuration interface, illustrates the multiple of chip in the interface with figure and draw
Foot；
Receiving module 402, receives the configuration-direct that user is directed to the pin shown, is described in the configuration-direct
Pin specifies the attribute to be configured；
Configuration module 403 carries out feasibility verifying according to the configuration-direct, and is verified in the feasibility
Afterwards, corresponding configuration file is generated for the chip.
Optionally, optional chip can be shown in the interface；
It is illustrated in the interface with figure: the multiple pins for the chip that user selectes from each optional chip, or
The multiple pins for the chip to be configured that person automatically identifies.
Optionally, multiple attributes are illustrated also directed to the chip or its pin in the interface, so that user is directed to
The pin shown selects the attribute to be configured.
Optionally, each pin of the chip, the layout of each pin of displaying are illustrated with figure in the interface
It is consistent with the layout of corresponding material object.
Optionally, the configuration-direct includes sequential multiple configuration sub-instructions；
Described device further include:
Screening module 404, according to the user having received for the configuration sub-instructions of the pin shown, to can lead to
It crosses the attribute to be configured that subsequent configuration sub-instructions are specified for the pin to be screened, for selection by the user.
Optionally, the feasibility verifying includes following at least a kind of verifying:
Whether will lead to pin to repeat to configure；Whether pin level configuration error will lead to；Whether will lead between pin
Function is obscured.
Optionally, the format of the configuration file is the data interchange format of lightweight；
The configuration module 403 is after the chip generates corresponding configuration file, also to execute:
According to the configuration file, compileable language file accordingly is generated, the chip is used for.
Optionally, the configuration file is JSON file, and corresponding compileable language file is C language file.
Fig. 5 is that a kind of structure for chip pin configuration equipment corresponding to Fig. 1 that some embodiments of the present application provide is shown
It is intended to, which includes:
At least one processor；And
The memory being connect at least one described processor communication；Wherein,
The memory is stored with the instruction that can be executed by least one described processor, and described instruction is by described at least one
A processor executes so that at least one described processor can:
It shows and visualizes pin configuration interface, multiple pins of chip are illustrated with figure in the interface；
The configuration-direct that user is directed to the pin shown is received, is that the pin specifies institute in the configuration-direct
The attribute to be configured；
Feasibility verifying is carried out according to the configuration-direct, and after the feasibility is verified, is the chip
Generate corresponding configuration file.
A kind of chip pin configuring non-volatile computer corresponding to Fig. 1 that some embodiments of the present application provide stores
Medium is stored with computer executable instructions, computer executable instructions setting are as follows:
It shows and visualizes pin configuration interface, multiple pins of chip are illustrated with figure in the interface；
The configuration-direct that user is directed to the pin shown is received, is that the pin specifies institute in the configuration-direct
The attribute to be configured；
Feasibility verifying is carried out according to the configuration-direct, and after the feasibility is verified, is the chip
Generate corresponding configuration file.
Various embodiments are described in a progressive manner in the application, same and similar part between each embodiment
It may refer to each other, each embodiment focuses on the differences from other embodiments.Especially for device, set
For standby and media embodiment, since it is substantially similar to the method embodiment, so be described relatively simple, related place referring to
The part of embodiment of the method illustrates.
Device, equipment and medium provided by the embodiments of the present application and method be it is one-to-one, therefore, device, equipment and
The advantageous effects that medium also has corresponding method similar, due to above to the advantageous effects of method into
Go detailed description, therefore, the advantageous effects of which is not described herein again device, equipment and medium.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method, system or computer program
Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the present invention
Apply the form of example.Moreover, it wherein includes the computer of computer usable program code that the present invention, which can be used in one or more,
The computer program implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) produces
The form of product.
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
In a typical configuration, calculating equipment includes one or more processors (CPU), input/output interface, net
Network interface and memory.
Memory may include the non-volatile memory in computer-readable medium, random access memory (RAM) and/or
The forms such as Nonvolatile memory, such as read-only memory (ROM) or flash memory (flash RAM).Memory is computer-readable medium
Example.
Computer-readable medium includes permanent and non-permanent, removable and non-removable media can be by any method
Or technology come realize information store.Information can be computer readable instructions, data structure, the module of program or other data.
The example of the storage medium of computer includes, but are not limited to phase change memory (PRAM), static random access memory (SRAM), moves
State random access memory (DRAM), other kinds of random access memory (RAM), read-only memory (ROM), electric erasable
Programmable read only memory (EEPROM), flash memory or other memory techniques, read-only disc read only memory (CD-ROM) (CD-ROM),
Digital versatile disc (DVD) or other optical storage, magnetic cassettes, tape magnetic disk storage or other magnetic storage devices
Or any other non-transmission medium, can be used for storage can be accessed by a computing device information.As defined in this article, it calculates
Machine readable medium does not include temporary computer readable media (transitory media), such as the data-signal and carrier wave of modulation.
It should also be noted that, the terms "include", "comprise" or its any other variant are intended to nonexcludability
It include so that the process, method, commodity or the equipment that include a series of elements not only include those elements, but also to wrap
Include other elements that are not explicitly listed, or further include for this process, method, commodity or equipment intrinsic want
Element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including described want
There is also other identical elements in the process, method of element, commodity or equipment.
The above description is only an example of the present application, is not intended to limit this application.For those skilled in the art
For, various changes and changes are possible in this application.All any modifications made within the spirit and principles of the present application are equal
Replacement, improvement etc., should be included within the scope of the claims of this application.
Claims (18)
1. a kind of chip pin configuration method characterized by comprising
It shows and visualizes pin configuration interface, multiple pins of chip are illustrated with figure in the interface；
The configuration-direct that user is directed to the pin shown is received, is that the pin specifies to be matched in the configuration-direct
The attribute set；
Feasibility verifying is carried out according to the configuration-direct, and after the feasibility is verified, is generated for the chip
Corresponding configuration file.
2. the method as described in claim 1, which is characterized in that can show optional chip in the interface；
It is illustrated in the interface with figure: the multiple pins for the chip that user selectes from each optional chip, or from
Multiple pins of the dynamic chip to be configured identified.
3. method according to claim 2, which is characterized in that shown in the interface also directed to the chip or its pin
Multiple attributes, so that user selects the attribute to be configured for the pin shown.
4. the method as described in claim 1, which is characterized in that illustrate respectively drawing for the chip in the interface with figure
The layout of foot, each pin of displaying is consistent with the layout of corresponding material object.
5. the method as described in claim 1, which is characterized in that the configuration-direct includes that sequential multiple configuration refer to
It enables；
The method also includes:
According to the user having received for the configuration sub-instructions of the pin shown, to can be referred to by subsequent configuration
The attribute to be configured specified for the pin is enabled to be screened, for selection by the user.
6. the method as described in claim 1, which is characterized in that the feasibility verifying includes following at least a kind of verifying:
Whether will lead to pin to repeat to configure；Whether pin level configuration error will lead to；Whether pin between function will lead to
Obscure.
7. the method as described in claim 1, which is characterized in that the format of the configuration file is the data exchange lattice of lightweight
Formula；
After the corresponding configuration file for chip generation, the method also includes:
According to the configuration file, compileable language file accordingly is generated, the chip is used for.
8. the method as described in claim 1, which is characterized in that the configuration file is JSON file, corresponding to compile
Translating language file is C language file.
9. a kind of chip pin configuration device characterized by comprising
Display module shows and visualizes pin configuration interface, illustrates multiple pins of chip in the interface with figure；
Receiving module receives the configuration-direct that user is directed to the pin shown, is that the pin refers in the configuration-direct
The attribute to be configured is determined；
Configuration module carries out feasibility verifying according to the configuration-direct, and is described after the feasibility is verified
Chip generates corresponding configuration file.
10. device as claimed in claim 9, which is characterized in that can show optional chip in the interface；
It is illustrated in the interface with figure: the multiple pins for the chip that user selectes from each optional chip, or from
Multiple pins of the dynamic chip to be configured identified.
11. device as claimed in claim 10, which is characterized in that also directed to the chip or its pin exhibition in the interface
Multiple attributes are shown, so that user selects the attribute to be configured for the pin shown.
12. device as claimed in claim 9, which is characterized in that illustrate respectively drawing for the chip in the interface with figure
The layout of foot, each pin of displaying is consistent with the layout of corresponding material object.
13. device as claimed in claim 9, which is characterized in that the configuration-direct includes that sequential multiple configuration refer to
It enables；
Described device further include:
Screening module, according to the user having received for the configuration sub-instructions of the pin shown, to can be by subsequent
Configuration sub-instructions for the pin specify the attribute to be configured screened, for selection by the user.
14. device as claimed in claim 9, which is characterized in that the feasibility verifying includes following at least a kind of verifying:
Whether will lead to pin to repeat to configure；Whether pin level configuration error will lead to；Whether pin between function will lead to
Obscure.
15. device as claimed in claim 9, which is characterized in that the format of the configuration file is the data exchange of lightweight
Format；
The configuration module is after the chip generates corresponding configuration file, also to execute:
According to the configuration file, compileable language file accordingly is generated, the chip is used for.
16. device as claimed in claim 9, which is characterized in that the configuration file is JSON file, corresponding to compile
Translating language file is C language file.
17. a kind of chip pin configures equipment characterized by comprising
At least one processor；And
The memory being connect at least one described processor communication；Wherein,
The memory is stored with the instruction that can be executed by least one described processor, and described instruction is by described at least one
Manage device execute so that at least one described processor can:
It shows and visualizes pin configuration interface, multiple pins of chip are illustrated with figure in the interface；
The configuration-direct that user is directed to the pin shown is received, is that the pin specifies to be matched in the configuration-direct
The attribute set；
Feasibility verifying is carried out according to the configuration-direct, and after the feasibility is verified, is generated for the chip
Corresponding configuration file.
18. a kind of chip pin configuring non-volatile computer storage medium, is stored with computer executable instructions, feature exists
In the computer executable instructions setting are as follows:
It shows and visualizes pin configuration interface, multiple pins of chip are illustrated with figure in the interface；
The configuration-direct that user is directed to the pin shown is received, is that the pin specifies to be matched in the configuration-direct
The attribute set；
Feasibility verifying is carried out according to the configuration-direct, and after the feasibility is verified, is generated for the chip
Corresponding configuration file.
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| CN201910038723.3A CN109740282A (en) | 2019-01-16 | 2019-01-16 | Chip pin configuration method, device, equipment and medium |
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| CN110263485A (en) * | 2019-06-27 | 2019-09-20 | 珠海泰芯半导体有限公司 | A kind of automatic Plotting System and computer system of chip package figure |
| CN112379931A (en) * | 2020-11-10 | 2021-02-19 | 西安核桃树软件科技有限公司 | Embedded terminal drive configuration method based on mobile terminal in visual environment |
| CN113190478A (en) * | 2021-03-19 | 2021-07-30 | 山东英信计算机技术有限公司 | GPIO (general purpose input/output) efficient configuration method, system and medium |
| CN114296808A (en) * | 2021-12-23 | 2022-04-08 | 科东(广州)软件科技有限公司 | Pin configuration method and device, electronic equipment and storage medium |
| CN114942899A (en) * | 2022-03-30 | 2022-08-26 | 深圳市广和通无线股份有限公司 | Pin configuration method, module, equipment and storage medium |
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| CN113190478A (en) * | 2021-03-19 | 2021-07-30 | 山东英信计算机技术有限公司 | GPIO (general purpose input/output) efficient configuration method, system and medium |
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| TWI820807B (en) * | 2022-07-20 | 2023-11-01 | 新唐科技股份有限公司 | Online integrated microcontroller development tool system, method for implementing the same, and microcontroller development conbination kit |
| CN115168239A (en) * | 2022-09-06 | 2022-10-11 | 中国汽车技术研究中心有限公司 | Method, equipment and storage medium for identifying JTAG debugging pin |
| CN116187227A (en) * | 2023-02-21 | 2023-05-30 | 广东高云半导体科技股份有限公司 | SoC generation method and device |
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