CN109739712A - FPGA accelerator card transmission performance test method, device and equipment and medium - Google Patents
FPGA accelerator card transmission performance test method, device and equipment and medium Download PDFInfo
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Abstract
This application discloses a kind of FPGA accelerator card transmission performance test method, apparatus and electronic equipments and computer readable storage medium, this method comprises: obtaining the first data packet and the second data packet being transmitted；Determine period 1 counting, the first frame count and the second round counting of the second data packet, the second frame count of the first data packet；Cycle count is the clock cycle count of FPGA when data packet is sent, and frame count is the counting that identification data packet sends sequence；Using period 1 counting, the first frame count, second round counting, the second frame count and unit data size, clock cycle, determines the unit data transfer amount in the unit time, obtain the first transmission performance indicators.The application determines unit data transfer amount in the unit time, obtains realizing the test to accelerator card transmission performance for the first transmission performance indicators for characterizing FPGA accelerator card transmission performance using the corresponding cycle count of data packet and frame count that are transmitted.
Description
Technical field
This application involves field of computer technology, more specifically to a kind of FPGA accelerator card transmission performance test side
Method, device and a kind of electronic equipment and a kind of computer readable storage medium.
Background technique
FPGA isomery accelerator card provides acceleration capacity for large-scale data calculating, is generally deployed in host server end,
Data interaction is carried out by PCIE interface and host, when the task of acceleration in need, host side utilizes DMA by PCIE interface
Technology transfers data to accelerator card, after accelerator card handles data, returns result to host side.Above-mentioned accelerator
The data transmission bauds of middle PCIE and DMA can have a direct impact the efficiency entirely accelerated, therefore, in FPGA isomery accelerator card
In early development and debugging process, need to test the DMA transfer performance of PCIE, to which theoretical transmission speed can be reached.
Therefore, how to carry out test to transmission performance is those skilled in the art's problem to be solved.
Summary of the invention
The application's is designed to provide a kind of FPGA accelerator card transmission performance test method, apparatus and a kind of electronic equipment
With a kind of computer readable storage medium, the test to FPGA accelerator card transmission performance is realized.
To achieve the above object, this application provides a kind of FPGA accelerator card transmission performance test methods, comprising:
Obtain the first data packet and the second data packet after being transmitted；
Determine the period 1 counting of first data packet, the second round of the first frame count and second data packet
It counts, the second frame count；Wherein, the cycle count is the clock cycle count of corresponding FPGA when data packet is sent, described
Frame count is the counting for identifying current data packet and sending sequence；
It is counted using period 1 counting, first frame count, the second round, second frame count,
And the clock cycle of the unit data size of every frame, FPGA, it determines the unit data transfer amount in the unit time, obtains first
Transmission performance indicators.
Optionally, described to be counted using period 1 counting, first frame count, the second round, is described
The clock cycle of the unit data size of second frame count and every frame, FPGA, determine the unit data transfer in the unit time
Amount, comprising:
When determining that data are transmitted using period 1 counting, second round counting and the clock cycle
Between；
It is total to determine that data are transmitted using first frame count, second frame count and the unit data size
Amount；
The unit data transfer amount is determined using the data transmission period and data transmission total amount.
Optionally, described to be determined using period 1 counting, second round counting and the clock cycle
Data transmission period, comprising:
It is counted using the clock cycle, the period 1 and the second round counts, be based on time calculation formula
Determine data transmission period；Wherein, the time calculation formula are as follows:
Transfer_time=(dma_cntnow-dma_cntpre)*T；
Wherein, transfer_time is the data transmission period；dma_cntnowFor period 1 counting；dma_
cntpreFor second round counting；T is the clock cycle.
Optionally, described to be determined using first frame count, second frame count and the unit data size
Data transmit total amount, comprising:
Using first frame count, second frame count and the unit data size, calculated based on transmission public
Formula determines that data transmit total amount；Wherein, the transmission calculation formula are as follows:
Transfer_data=(frame_cntnow-frame_cntpre)*frame_len；
Wherein, transfer_data is that the data transmit total amount；frame_cntnowFor first frame count；
frame_cntpreFor second frame count；Frame_len is the unit data size.
Optionally, further includes:
Obtain third data packet corresponding with the adjacent target frame count of first frame count；
The period 1 based on first data packet counts and the period 3 of the third data packet counts, really
Determine the actual transmissions time；
It determines the Preset Transfer time of the unit data size, and is based on the actual transmissions time and the default biography
The defeated time determines transmission delay, obtains the second transmission performance indicators.
To achieve the above object, this application provides a kind of FPGA accelerator card transmission performance test devices, comprising:
Data acquisition module, for obtaining the first data packet after being transmitted and the second data packet,
Count determining module, for determine the period 1 of first data packet count, the first frame count and described the
The second round counting of two data packets, the second frame count；Wherein, the cycle count is corresponding FPGA when data packet is sent
Clock cycle count, the frame count are the counting for identifying current data packet and sending sequence；
Performance determining module, by using period 1 counting, first frame count, based on the second round
The clock cycle of the unit data size of several, described second frame count and every frame, FPGA, determine the unit in the unit time
Volume of transmitted data obtains the first transmission performance indicators.
Optionally, the performance determining module, comprising:
Time determination unit, for being counted using the period 1, the second round counts and clock week
Phase determines data transmission period；
Total amount determination unit, for big using first frame count, second frame count and the unit data
Small determining data transmit total amount；
Unit determining module, for determining the units using the data transmission period and data transmission total amount
According to transmission quantity.
Optionally, further includes:
Adjacent acquisition module, for obtaining the corresponding third data of the target frame count adjacent with first frame count
Packet；
Practical determining module counts and the third data packet for the period 1 based on first data packet
Period 3 count, determine the actual transmissions time；
Be delayed determining module, for determining the Preset Transfer time of the unit data size, and based on the practical biography
Defeated time and the Preset Transfer time determine transmission delay, obtain the second transmission performance indicators.
To achieve the above object, this application provides a kind of electronic equipment, comprising:
Memory, for storing computer program；
Processor realizes any FPGA accelerator card transporting as previously disclosed when for executing the computer program
The step of energy test method.
To achieve the above object, this application provides a kind of computer readable storage medium, the computer-readable storages
It is stored with computer program on medium, any FPGA as previously disclosed is realized when the computer program is executed by processor
The step of accelerator card transmission performance test method.
By above scheme it is found that a kind of FPGA accelerator card transmission performance test method provided by the present application, comprising: obtain
The first data packet and the second data packet after being transmitted；Determine period 1 counting, the first frame meter of first data packet
Several and second data packet second round counting, the second frame count；Wherein, the cycle count be data packet send when pair
The clock cycle count of the FPGA answered, the frame count are the counting for identifying current data packet and sending sequence；Utilize described first
Cycle count, first frame count, the second round count, the unit data of second frame count and every frame is big
Small, FPGA clock cycle determines the unit data transfer amount in the unit time, obtains the first transmission performance indicators.That is, this
Application determines unit data transfer in the unit time using the corresponding cycle count of data packet and frame count that are transmitted
Amount, obtains the first transmission performance indicators for characterizing FPGA accelerator card transmission performance, realizes to FPGA accelerator card transporting
The test of energy.Disclosed herein as well is a kind of FPGA accelerator card transmission performance test device and a kind of electronic equipment and a kind of calculating
Machine readable storage medium storing program for executing is equally able to achieve above-mentioned technical effect.
It should be understood that the above general description and the following detailed description are merely exemplary, this can not be limited
Application.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of application for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is a kind of flow chart of FPGA accelerator card transmission performance test method disclosed in the embodiment of the present application；
Fig. 2 passes for unit data determining in a kind of FPGA accelerator card transmission performance test method disclosed in the embodiment of the present application
The flow chart of throughput rate process；
Fig. 3 prolongs to obtain data transmission in a kind of FPGA accelerator card transmission performance test method disclosed in the embodiment of the present application
The flow chart of slow process；
Fig. 4 is a kind of structure chart of FPGA accelerator card transmission performance test device disclosed in the embodiment of the present application；
Fig. 5 is the structure chart of a kind of electronic equipment disclosed in the embodiment of the present application；
Fig. 6 is the structure chart of another kind electronic equipment disclosed in the embodiment of the present application.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall in the protection scope of this application.
In the prior art, FPGA isomery accelerator card is generally deployed in host server end, passes through PCIE interface and host
Data interaction is carried out, when the task of acceleration in need, host side, which is transferred data to by PCIE interface using DMA technology, to be added
Speed is blocked, and data transmission bauds can have a direct impact the efficiency entirely accelerated in accelerator, therefore, is accelerated in FPGA isomery
In card early development and debugging process, need to test the DMA transfer performance of PCIE.
The embodiment of the present application discloses a kind of FPGA accelerator card transmission performance test method.Referring to Fig. 1, the embodiment of the present application
The flow chart of a kind of disclosed FPGA accelerator card transmission performance test method, as shown in Figure 1, comprising:
S101: the first data packet and the second data packet after being transmitted are obtained；
In the present embodiment, any two data packets intercepted after being transmitted obtain the first data packet and the second data packet.
S102: determine the period 1 of first data packet count, the first frame count and second data packet the
Two cycles counting, the second frame count；Wherein, the clock cycle meter that the cycle count is corresponding FPGA when data packet is sent
Number, the frame count are the counting for identifying current data packet and sending sequence；
In this step, the corresponding period 1 counting of the first data packet, the first frame count and the second data packet are determined
Second round counting, the second frame count.Specifically, the clock cycle meter that cycle count is data packet corresponding FPGA when sending
Number, frame count are the counting determined when data packet is sent according to transmission sequence.
It is understood that data packet encapsulates cycle count and frame count in a data frame when sending together.Wherein,
Data frame includes frame head preamble, and frame head can be arbitrary value, is parsed for host side to data packet；Frame_len,
Indicate data frame length；Payload can be arbitrary value；Frame_cnt, dma_cnt are frame count and cycle count, save
In the postamble of data packet.
S103: it is counted using period 1 counting, first frame count, the second round, second frame
It the clock cycle of the unit data size of counting and every frame, FPGA, determines the unit data transfer amount in the unit time, obtains
To the first transmission performance indicators.
Further, based on period 1 counting, the first frame count, second round counting, the second frame count and every frame
Unit data size, FPGA clock cycle, determine the unit data transfer amount in the unit time, utilize unit data transfer
The transmission performance of amount description FPGA accelerator card.
By above scheme it is found that a kind of FPGA accelerator card transmission performance test method provided by the present application, comprising: obtain
The first data packet and the second data packet after being transmitted；Determine period 1 counting, the first frame meter of first data packet
Several and second data packet second round counting, the second frame count；Wherein, the cycle count be data packet send when pair
The clock cycle count of the FPGA answered, the frame count are the counting for identifying current data packet and sending sequence；Utilize described first
Cycle count, first frame count, the second round count, the unit data of second frame count and every frame is big
Small, FPGA clock cycle determines the unit data transfer amount in the unit time, obtains the first transmission performance indicators.That is, this
Application determines unit data transfer in the unit time using the corresponding cycle count of data packet and frame count that are transmitted
Amount, obtains the first transmission performance indicators for describing FPGA accelerator card transmission performance, realizes to FPGA accelerator card transporting
The test of energy.
In the present embodiment, counted for utilization period 1 counting, the first frame count, second round, the second frame count, with
And the clock cycle of the unit data size of every frame, FPGA, determine that the process of the unit data transfer amount in the unit time carries out
It is further described, referring to fig. 2, which specifically includes:
S201: it is counted using the period 1, the second round counts and the clock cycle determines that data pass
The defeated time；
It is counted using the clock cycle, the period 1 and the second round counts, be based on time calculation formula
Determine data transmission period；Wherein, the time calculation formula are as follows:
Transfer_time=(dma_cntnow-dma_cntpre)*T；
Wherein, transfer_time is the data transmission period；dma_cntnowFor period 1 counting；dma_
cntpreFor second round counting；T is the clock cycle.
In this step, the cycle count for arbitrarily intercepting two obtained data packets is made into poor, the period differed, then obtain
To the product with the clock cycle, as data transmission period.Specifically, the clock cycle T of FPGA is 4ns (nanosecond).
S202: determine that data pass using first frame count, second frame count and the unit data size
Defeated total amount；
Using first frame count, second frame count and the unit data size, calculated based on transmission public
Formula determines that data transmit total amount；Wherein, the transmission calculation formula are as follows:
Transfer_data=(frame_cntnow-frame_cntpre)*frame_len；
Wherein, transfer_data is that the data transmit total amount；frame_cntnowFor first frame count；
frame_cntpreFor second frame count；Frame_len is the unit data size.
It is understood that being multiplied using the difference of the frame count of two data packets with unit data size, data biography is obtained
Defeated total amount.
S203: the unit data transfer amount is determined using the data transmission period and data transmission total amount.
Further, after obtaining data transmission total amount and data transmission period, using data transmission total amount divided by data
Transmission time obtains unit data transfer amount.In specific implementation, it can use transmission calculation formula and determine unit data transfer
Amount, transmission calculation formula are as follows:
Speed=[(transfer_data/ (1024*1024))/transfer_time] * 109；
Wherein, speed is transmission speed namely unit data transfer amount, and unit is million/second.
Further, based on any of the above embodiments, FPGA accelerator card transporting provided by the embodiments of the present application
Can test can also obtain data transfer delay, the index as another description data transmission performance.As shown in figure 3, obtaining
The process of data transfer delay includes:
S301: third data packet corresponding with the adjacent target frame count of first frame count is obtained；
In the present embodiment, after acquisition the target frame count namely the first data packet adjacent with the first frame count are transmitted
The third data packet of transmission.
S302: it is counted by the period 1 of first data packet and based on the period 3 of the third data packet
Number, determines the actual transmissions time；
It is understood that counting the difference counted with the period 3 using the period 1, the actual transmissions time is determined.
S303: determining the Preset Transfer time of the unit data size, and based on actual transmissions time and described
The Preset Transfer time determines transmission delay, obtains the second transmission performance indicators.
In this step, the Preset Transfer time of unit data size is determined, can use default determining formula specifically to count
It calculates, wherein default to determine formula are as follows:
Mv_da_time=(frame_len*8/256) * 4ns；
Wherein, mv_da_time is the Preset Transfer time；Frame_len is unit size of data；4ns is the clock cycle.
Further, it is poor to be made using actual transmissions time and Preset Transfer time, obtains transmission delay, transmission delay is made
For the index of another evaluation transmission performance.
A kind of FPGA accelerator card transmission performance test device provided by the embodiments of the present application is introduced below, is hereafter retouched
A kind of FPGA accelerator card transmission performance test device stated and a kind of above-described FPGA accelerator card transmission performance test method
It can be cross-referenced.
Referring to fig. 4, the structure chart of a kind of FPGA accelerator card transmission performance test device provided by the embodiments of the present application is such as schemed
Shown in 4, comprising:
Data acquisition module 100, for obtaining the first data packet after being transmitted and the second data packet；
Count determining module 200, for determine the period 1 of first data packet count, the first frame count and described
The second round counting of second data packet, the second frame count；Wherein, the cycle count is corresponding FPGA when data packet is sent
Clock cycle count, the frame count be identify current data packet send sequence counting；
Performance determining module 300, for utilizing period 1 counting, first frame count, the second round
It counts, the clock cycle of the unit data size of second frame count and every frame, FPGA, determines the list in the unit time
Position volume of transmitted data, obtains the first transmission performance indicators.
Further, the performance determining module, comprising:
Time determination unit, for being counted using the period 1, the second round counts and clock week
Phase determines data transmission period；
Total amount determination unit, for big using first frame count, second frame count and the unit data
Small determining data transmit total amount；
Unit determining module, for determining the units using the data transmission period and data transmission total amount
According to transmission quantity.
Further, the FPGA accelerator card transmission performance test device can also include:
Adjacent acquisition module, for obtaining the corresponding third data of the target frame count adjacent with first frame count
Packet；
Practical determining module counts and the third data packet for the period 1 based on first data packet
Period 3 count, determine the actual transmissions time；
Be delayed determining module, for determining the Preset Transfer time of the unit data size, and based on the practical biography
Defeated time and the Preset Transfer time determine transmission delay, obtain the second transmission performance indicators.
Present invention also provides a kind of electronic equipment, referring to Fig. 5, the knot of a kind of electronic equipment provided by the embodiments of the present application
Composition, as shown in Figure 5, comprising:
Memory 11, for storing computer program；
Step provided by above-described embodiment may be implemented in processor 12 when for executing the computer program.
Specifically, memory 11 includes non-volatile memory medium, built-in storage.The non-volatile memory medium is stored with
Operating system and computer-readable instruction, the built-in storage are the operating system and computer-readable in non-volatile memory medium
The operation of instruction provides environment.Processor 12 can be a central processing unit (Central in some embodiments
Processing Unit, CPU), controller, microcontroller, microprocessor or other data processing chips, mentioned for electronic equipment
For calculating and control ability.
On the basis of the above embodiments, preferably, referring to Fig. 6, the electronic equipment further include:
Input interface 13 is connected with processor 12, for obtaining computer program, parameter and the instruction of external importing, warp
The control of processor 12 is saved into memory 11.The input interface 13 can be connected with input unit, receive user and be manually entered
Parameter or instruction.The input unit can be the touch layer covered on display screen, be also possible to be arranged in terminal enclosure by
Key, trace ball or Trackpad are also possible to keyboard, Trackpad or mouse etc..
Display unit 14 is connected with processor 12, for the data of the processing of video-stream processor 12 and for showing visually
The user interface of change.The display unit 14 can be light-emitting diode display, liquid crystal display, touch-control liquid crystal display and OLED
(Organic Light-Emitting Diode, Organic Light Emitting Diode) touches device etc..
The network port 15 is connected with processor 12, for being communicatively coupled with external each terminal device.The communication connection
The used communication technology can be cable communicating technology or wireless communication technique, such as mobile high definition chained technology (MHL), general
Universal serial bus (USB), high-definition media interface (HDMI), adopting wireless fidelity technology (WiFi), Bluetooth Communication Technology, low-power consumption bluetooth
The communication technology, communication technology based on IEEE802.11s etc..
Fig. 6 illustrates only the electronic equipment with component 11-15, it will be appreciated by persons skilled in the art that Fig. 6 is shown
Structure do not constitute the restriction to electronic equipment, may include more certain than illustrating less perhaps more components or combination
Component or different component layouts.
Present invention also provides a kind of computer readable storage medium, the storage medium may include: USB flash disk, mobile hard disk,
Read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic
The various media that can store program code such as dish or CD.Computer program, the calculating are stored on the storage medium
Machine program realizes step provided by above-described embodiment when being executed by processor.
The application determines unit in the unit time using the corresponding cycle count of data packet and frame count that are transmitted
Volume of transmitted data obtains the first transmission performance indicators for characterizing FPGA accelerator card transmission performance, realizes and accelerates to FPGA
The test of card transmission performance.
Each embodiment is described in a progressive manner in specification, the highlights of each of the examples are with other realities
The difference of example is applied, the same or similar parts in each embodiment may refer to each other.For system disclosed in embodiment
Speech, since it is corresponded to the methods disclosed in the examples, so being described relatively simple, related place is referring to method part illustration
?.It should be pointed out that for those skilled in the art, under the premise of not departing from the application principle, also
Can to the application, some improvement and modification can also be carried out, these improvement and modification also fall into the protection scope of the claim of this application
It is interior.
It should also be noted that, in the present specification, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes that
A little elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in the process, method, article or apparatus that includes the element.
Claims (10)
1. a kind of FPGA accelerator card transmission performance test method characterized by comprising
Obtain the first data packet and the second data packet after being transmitted；
Determine the period 1 counting of first data packet, the second round meter of the first frame count and second data packet
Number, the second frame count；Wherein, the cycle count is the clock cycle count of corresponding FPGA when data packet is sent, the frame
It is counted as the counting that mark current data packet sends sequence；
It is counted using period 1 counting, first frame count, the second round, second frame count, and
It the clock cycle of the unit data size of every frame, FPGA, determines the unit data transfer amount in the unit time, obtains the first transmission
Performance indicator.
2. FPGA accelerator card transmission performance test method according to claim 1, which is characterized in that described to utilize described the
One cycle count, first frame count, the second round count, the unit data of second frame count and every frame
The clock cycle of size, FPGA determines the unit data transfer amount in the unit time, comprising:
It is counted using the period 1, the second round counts and the clock cycle determines data transmission period；
Determine that data transmit total amount using first frame count, second frame count and the unit data size；
The unit data transfer amount is determined using the data transmission period and data transmission total amount.
3. FPGA accelerator card transmission performance test method according to claim 2, which is characterized in that described to utilize described the
One cycle count, the second round count and the clock cycle determines data transmission period, comprising:
It is counted using the clock cycle, the period 1 and the second round counts, determined based on time calculation formula
Data transmission period；Wherein, the time calculation formula are as follows:
Transfer_time=(dma_cntnow-dma_cntpre)*T；
Wherein, transfer_time is the data transmission period；dma_cntnowFor period 1 counting；dma_
cntpreFor second round counting；T is the clock cycle.
4. FPGA accelerator card transmission performance test method according to claim 3, which is characterized in that described to utilize described the
One frame count, second frame count and the unit data size determine that data transmit total amount, comprising:
It is true based on transmission calculation formula using first frame count, second frame count and the unit data size
Fixed number is according to transmission total amount；Wherein, the transmission calculation formula are as follows:
Transfer_data=(frame_cntnow-frame_cntpre)*frame_len；
Wherein, transfer_data is that the data transmit total amount；frame_cntnowFor first frame count；frame_
cntpreFor second frame count；Frame_len is the unit data size.
5. FPGA accelerator card transmission performance test method according to any one of claims 1 to 4, which is characterized in that also wrap
It includes:
Obtain third data packet corresponding with the adjacent target frame count of first frame count；
The period 1 based on first data packet counts and the period 3 of the third data packet counts, and determines real
Border transmission time；
When determining the Preset Transfer time of the unit data size, and being based on the actual transmissions time and the Preset Transfer
Between determine transmission delay, obtain the second transmission performance indicators.
6. a kind of FPGA accelerator card transmission performance test device characterized by comprising
Data acquisition module, for obtaining the first data packet after being transmitted and the second data packet；
Determining module is counted, for determining that the period 1 of first data packet counts, the first frame count and described second counts
It is counted according to the second round of packet, the second frame count；Wherein, the cycle count is the clock of corresponding FPGA when data packet is sent
Cycle count, the frame count are the counting for identifying current data packet and sending sequence；
Performance determining module, for utilizing period 1 counting, first frame count, second round counting, institute
The unit data size of the second frame count and every frame, the clock cycle of FPGA are stated, determines that the unit data in the unit time passes
Throughput rate obtains the first transmission performance indicators.
7. FPGA accelerator card transmission performance test device according to claim 6, which is characterized in that the performance determines mould
Block, comprising:
Time determination unit, for being counted using the period 1, the second round counts and the clock cycle is true
Determine data transmission period；
Total amount determination unit, for true using first frame count, second frame count and the unit data size
Fixed number is according to transmission total amount；
Unit determining module, for determining that the unit data passes using the data transmission period and data transmission total amount
Throughput rate.
8. FPGA accelerator card transmission performance test device according to claim 6 or 7, which is characterized in that further include:
Adjacent acquisition module, for obtaining the corresponding third data packet of the target frame count adjacent with first frame count；
Practical determining module, counted for the period 1 based on first data packet and the third data packet the
Three cycle counts determine the actual transmissions time；
Be delayed determining module, for determining the Preset Transfer time of the unit data size, and when being based on the actual transmissions
Between and the Preset Transfer time determine transmission delay, obtain the second transmission performance indicators.
9. a kind of electronic equipment characterized by comprising
Memory, for storing computer program；
Processor realizes that FPGA accelerator card transmits as described in any one of claim 1 to 5 when for executing the computer program
The step of performance test methods.
10. a kind of computer readable storage medium, which is characterized in that be stored with computer on the computer readable storage medium
Program realizes the FPGA accelerator card transporting as described in any one of claim 1 to 5 when the computer program is executed by processor
The step of energy test method.
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| CN110413461A (en) * | 2019-06-28 | 2019-11-05 | 苏州浪潮智能科技有限公司 | Measure system, method and the accelerator card of transmission delay between accelerator card and host |
| CN113609056A (en) * | 2021-06-25 | 2021-11-05 | 曙光信息产业(北京)有限公司 | Data transmission test method, device, equipment and storage medium |
| CN116302756A (en) * | 2023-03-22 | 2023-06-23 | 无锡市软测认证有限公司 | Performance test system and method based on FPGA (field programmable Gate array) accelerator card |
| CN117081960A (en) * | 2023-10-16 | 2023-11-17 | 深圳华云信息系统科技股份有限公司 | Data transmission performance testing method and device, electronic equipment and storage medium |
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