CN109728814A - Can elastic handoff candidate capacitor operational amplifier - Google Patents

Can elastic handoff candidate capacitor operational amplifier Download PDF

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CN109728814A
CN109728814A CN201711056837.8A CN201711056837A CN109728814A CN 109728814 A CN109728814 A CN 109728814A CN 201711056837 A CN201711056837 A CN 201711056837A CN 109728814 A CN109728814 A CN 109728814A
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capacitor
coupled
candidate
switch
signal
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CN109728814B (en
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赖杰帆
陈志龙
黄诗雄
吴健铭
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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Abstract

The present invention proposes a kind of operational amplifier, includes: one first gain stage, is arranged to one first signal transmitted according to a front stage circuits and generates a second signal；One second gain stage is arranged to generate an output signal according to the second signal；Multiple candidate's capacitors；And capacitance selection circuit, the size for being arranged to the input signal according to the front stage circuits switches the coupling mode of multiple candidate capacitor, so that only some candidate capacitor can be coupled to second gain stage to multiple candidate's capacitor in the same time.

Description

Can elastic handoff candidate capacitor operational amplifier
Technical field
The present invention relates to operational amplifier, in particular to it is a kind of can elastic handoff candidate capacitor operational amplifier.
Background technique
Operational amplifier is widely used in many circuits, but the overall efficiency of these circuits or service speed are past Toward the response speed for being limited to operational amplifier.It is well known that needed for feedback capacity charge or discharge inside operational amplifier Length of time have a significant impact to the response speed of operational amplifier.If cannot substantially shorten anti-inside operational amplifier The charge or discharge time held is fed, is just difficult to be effectively improved the response speed of operational amplifier.
Summary of the invention
In view of this, the charge or discharge time needed for how shortening the feedback capacity inside operational amplifier, with effective Improve the response speed of operational amplifier, actually problem to be solved.
This specification provides a kind of embodiment of operational amplifier, it includes: one first gain stage is arranged to according to the fortune Calculate one first signal, one second signal of generation that a front stage circuits of amplifier transmit；One second gain stage, be coupled to this first Gain stage is arranged to generate an output signal according to the second signal；One first candidate capacitor；One second candidate capacitor；One Three candidate capacitors；One first switch is coupled to a first end of the first candidate capacitor, is used for the first candidate capacitance selection It is coupled to one first predetermined voltage or an input terminal of second gain stage to property；One second switch is coupled to first candidate One second end of capacitor, for the first candidate capacitance selection to be coupled to the one of a first voltage or second gain stage Output end；One third switch is coupled to a first end of the second candidate capacitor, for by the second candidate capacitance selection It is coupled to first predetermined voltage or the input terminal of second gain stage；One the 4th switch is coupled to the second candidate capacitor A second end, for the second candidate capacitance selection to be coupled to a second voltage or the output of second gain stage End；One the 5th switch, is coupled to a first end of third candidate's capacitor, for coupling third candidate's capacitance selection To first predetermined voltage or the input terminal of second gain stage；One the 6th switch, is coupled to the one of third candidate's capacitor Second end, for third candidate's capacitance selection to be coupled to a tertiary voltage or the output end of second gain stage； And a capacitance selection circuit, the front stage circuits and first to the 6th switch are coupled to, are arranged to according to the front stage circuits An input signal size control this first to the 6th switch so that this first to third candidate capacitor in the same time In only some candidate capacitor can be coupled to second gain stage.
This manual also provides a kind of embodiment of operational amplifier, it includes one first gain stage, it is arranged to according to should One first signal that one front stage circuits of operational amplifier transmit generates a second signal；One second gain stage, be coupled to this One gain stage is arranged to generate an output signal according to the second signal；One first candidate capacitor；One second candidate capacitor；One Third candidate's capacitor；One first switch is coupled to a first end of the first candidate capacitor, for selecting the first candidate capacitor Selecting property it is coupled to one first predetermined voltage or an input terminal of second gain stage；One second switch is coupled to first time The second end for selecting capacitor, for the first candidate capacitance selection to be coupled to a first voltage or second gain stage One output end；One third switch is coupled to a first end of the second candidate capacitor, is used for the second candidate capacitance selection Ground is coupled to first predetermined voltage or the input terminal of second gain stage；One the 4th switch is coupled to the second candidate electricity The second end held, for the second candidate capacitance selection is coupled to a second voltage or second gain stage this is defeated Outlet；One the 5th switch, is coupled to a first end of third candidate's capacitor, for by third candidate's capacitance selection coupling It is connected to first predetermined voltage or the input terminal of second gain stage；One the 6th switch, is coupled to third candidate's capacitor One second end, for third candidate's capacitance selection to be coupled to a tertiary voltage or the output of second gain stage End；One the 4th candidate capacitor；One the 5th candidate capacitor；One the 6th candidate capacitor；One the 7th switch is coupled to the 4th candidate electricity The first end held, for the 4th candidate capacitance selection to be coupled to first predetermined voltage or second gain stage The input terminal；One the 8th switch is coupled to a second end of the 4th candidate capacitor, is used for the 4th candidate capacitance selection Ground is coupled to the first voltage or the output end of second gain stage；One the 9th switch is coupled to the 5th candidate capacitor One first end, for the 5th candidate capacitance selection is coupled to first predetermined voltage or second gain stage this is defeated Enter end；The tenth switch is coupled to a second end of the 5th candidate capacitor, for by the 5th candidate capacitance selection coupling It is connected to the second voltage or the output end of second gain stage；The 11st switch is coupled to the one of the 6th candidate capacitor First end, for the 6th candidate capacitance selection to be coupled to first predetermined voltage or the input of second gain stage End；The 12nd switch is coupled to a second end of the 6th candidate capacitor, for by the 6th candidate capacitance selection coupling It is connected to the tertiary voltage or the output end of second gain stage；And a capacitance selection circuit, be coupled to the front stage circuits with This first to the 12nd switch, be arranged to the input signal according to the front stage circuits size control this first to the tenth Two switches so that first to the 6th candidate capacitor in the same time only some candidate capacitor can be coupled to this Two gain stages；Wherein, which is divided into a first capacitor group and one second capacitance group, and work as this first When part candidate's capacitor in capacitance group is coupled to second gain stage, all candidate capacitors in second capacitance group can divide It is not charged to different cross-pressure values.
One of the advantages of above-described embodiment is before the selection that operational amplifier carries out candidate capacitor, in operational amplifier Multiple candidate capacitors can be precharged to respectively can shorten whereby with different cross-pressure values after chosen capacitor institute The charge or discharge time needed.
Another advantage of above-described embodiment, be using the dynamic select mechanism of aforesaid plurality of candidate capacitor, it is equivalent on can contract The charge or discharge time needed for the feedback capacity of short operational amplifier, therefore can effectively improve the response speed of operational amplifier.
Other advantages of the invention will arrange in pairs or groups following explanation and drawings provide more detailed explanation.
Detailed description of the invention
Fig. 1 is the simplified functional block diagram of operational amplifier of one embodiment of the invention.
Fig. 2 is the simplified schematic diagram of an embodiment of the capacitance selection circuit in Fig. 1.
Fig. 3 is the simplified functional block diagram of pipeline system analog-digital converter of first embodiment of the invention.
Fig. 4 is the simplified local function block diagram of an embodiment of the pipeline system analog-digital converter of Fig. 3.
Fig. 5 is the simplified functional block diagram of pipeline system analog-digital converter of second embodiment of the invention.
Fig. 6 is the simplified local function block diagram of an embodiment of the pipeline system analog-digital converter of Fig. 5.
Fig. 7 is the simplified functional block diagram of sample and hold of one embodiment of the invention.
Description of symbols:
100 operational amplifiers
102 front stage circuits
110,120 gain stage
131,133,135,151,153,155 candidate capacitor
141-146,161-166,425-429,445-449,645-649 switch
170 capacitance selection circuits
210-230 comparator
240 selection logics
300 single channel pipeline system analog-digital converters
301-304,501-504 circuit-level
305,505 rear end analog-digital converter
306, the adjustment of 506 timing and error correction circuit
310,330,530 analog-digital converter
320,340,540 multiplication formula digital analog converter
322,342,542 samplings and holding circuit
324,344,544 digital analog converter
326,346,546 subtracter
328,348,548 operational amplifier
420,440,640 switching type capacitor network
421,423,441,443,641,643 capacitor
480 output switches
490 input switches
500 binary channels pipeline system analog-digital converters
700 sample and holds
702 switching type capacitor networks
710 sampling capacitors
720,730 sampling switch
740 sequential control circuits
Specific embodiment
Illustrate the embodiment of the present invention below in conjunction with relevant drawings.In the accompanying drawings, identical label indicate it is identical or Similar element or method flow.
Fig. 1 is the simplified functional block diagram of operational amplifier 100 of one embodiment of the invention.Operational amplifier 100 wraps Containing the first gain stage 110, the second gain stage 120, multiple candidate capacitors, multiple switch and capacitance selection circuit 170.
Candidate capacitor 131,133 and 135 is depicted for the sake of for convenience of explanation, in Fig. 1 (is referred to as first individually below To third candidate capacitor), candidate capacitor 151,153, with 155 (being referred to as the 4th to the 6th candidate capacitors individually below), switch 141-146 (individually below be referred to as first to the 6th switch) and switch 161-166 the (individually below the referred to as the 7th to the 12 switches) it is used as exemplary elements.
In operational amplifier 100, the first gain stage 110 is arranged to pass according to the front stage circuits 102 of operational amplifier 100 The the first signal N1 come generates second signal N2.Front stage circuits 102 above-mentioned can be with including one or more switching type capacitor networks Various appropriate circuitries realize.
Second gain stage 120 is coupled to the first gain stage 110, and is arranged to generate operational amplifier according to second signal N2 100 output signal Vout.
As shown, first switch 141 is coupled to the first end of the first candidate capacitor 131, it is used for the first candidate capacitor 131 are selectively coupled to the input terminal of the first predetermined voltage Vcm or the second gain stage 120.
Second switch 142 is coupled to the second end of the first candidate capacitor 131, for the first candidate capacitor 131 is selective Ground is coupled to the output end of first voltage V1 or the second gain stage 120.
Third switch 143 is coupled to the first end of the second candidate capacitor 133, for the second candidate capacitor 133 is selective Ground is coupled to the input terminal of the first predetermined voltage Vcm or the second gain stage 120.
4th switch 144 is coupled to the second end of the second candidate capacitor 133, for the second candidate capacitor 133 is selective Ground is coupled to the output end of second voltage V2 or the second gain stage 120.
5th switch 145 is coupled to the first end of third candidate capacitor 135, for third candidate capacitor 135 is selective Ground is coupled to the input terminal of the first predetermined voltage Vcm or the second gain stage 120.
6th switch 146 is coupled to the second end of third candidate capacitor 135, for third candidate capacitor 135 is selective Ground is coupled to the output end of tertiary voltage V3 or the second gain stage 120.
7th switch 161 is coupled to the first end of the 4th candidate capacitor 151, for the 4th candidate capacitor 151 is selective Ground is coupled to the input terminal of the first predetermined voltage Vcm or the second gain stage 120.
8th switch 162 is coupled to the second end of the 4th candidate capacitor 151, for the 4th candidate capacitor 151 is selective Ground is coupled to the output end of first voltage V1 or the second gain stage 120.
9th switch 163 is coupled to the first end of the 5th candidate capacitor 153, for the 5th candidate capacitor 153 is selective Ground is coupled to the input terminal of the first predetermined voltage Vcm or the second gain stage 120.
Tenth switch 164 is coupled to the second end of the 5th candidate capacitor 153, for the 5th candidate capacitor 153 is selective Ground is coupled to the output end of second voltage V2 or the second gain stage 120.
11st switch 165 is coupled to the first end of the 6th candidate capacitor 155, for selecting the 6th candidate capacitor 155 Property it is coupled to the input terminal of the first predetermined voltage Vcm or the second gain stage 120.
12nd switch 166 is coupled to the second end of the 6th candidate capacitor 155, for selecting the 6th candidate capacitor 155 Property it is coupled to the output end of tertiary voltage V3 or the second gain stage 120.
Capacitance selection circuit 170 is coupled to front stage circuits 102 and the first to the 12nd switch 141-146 and 161-166, and It is arranged to the size of the input signal Vin according to front stage circuits 102, controls the first to the 12nd switch 141-146 and 161- 166, to cause the first to the 6th candidate capacitor 131-135 and 151-155 only some candidate capacitor meeting in the same time It is coupled to the second gain stage 120.
By preceding description it is found that input signal Vin is the input signal of front stage circuits 102, and operational amplifier 100 is defeated Entering signal then is the first signal N1.The input signal Vin of the front stage circuits 102 and output signal Vout two of operational amplifier 100 Size relation between person, and the first gain stage 110 are related with the yield value design of both the second gain stages 120.
In implementation, above-mentioned first to tertiary voltage V1-V3 can be different size of voltage, and above-mentioned first is predetermined Voltage Vcm can be the common-mode voltage (common mode voltage) of a fixed voltage or the second gain stage 120.
It note that in Fig. 1 and the first gain stage 110 and the second gain stage 120 be schematically shown as monofocal circuit framework, be only Simplified drawing complexity, not limits to actual implementation mode of the invention.In implementation, first in operational amplifier 100 increases Beneficial grade 110 can all be realized with the second gain stage 120 with differential circuit framework.
Running when, capacitance selection circuit 170 can synchronism switching particular candidate capacitor both ends switch, by the specific time Capacitor is selected to be couple to the second gain stage 120 to participate in the generation of output signal Vout running, or by the particular candidate capacitor coupling Corresponding charging voltage is connected to charge.
For example, the first end of first candidate capacitor 131 is coupled to when capacitance selection circuit 170 controls first switch 141 When the input terminal of the second gain stage 120, capacitance selection circuit 170 can control second switch 142 for the of the first candidate capacitor 131 Two ends are coupled to the output end of the second gain stage 120.At this point, the first candidate capacitor 131 can participate in the production of output signal Vout Raw running.On the other hand, the first end of first candidate capacitor 131 is coupled when capacitance selection circuit 170 controls first switch 141 When to the first predetermined voltage Vcm, capacitance selection circuit 170 can then control second switch 142 for the second of the first candidate capacitor 131 End is coupled to first voltage V1.At this point, the first candidate capacitor 131 can be switched to charge mode and be charged to predetermined with one Cross-pressure value (in this case, it is the voltage differences between first voltage V1 and the first predetermined voltage Vcm).
In another example the first end of second candidate capacitor 133 is coupled when capacitance selection circuit 170 controls third switch 143 To the second gain stage 120 input terminal when, capacitance selection circuit 170 can control the 4th switch 144 for the second candidate capacitor 133 Second end is coupled to the output end of the second gain stage 120.At this point, the second candidate capacitor 133 can participate in output signal Vout's Generate running.On the other hand, when capacitance selection circuit 170 controls third switch 143 for the first end coupling of the second candidate capacitor 133 When being connected to the first predetermined voltage Vcm, capacitance selection circuit 170 can then control the 4th switch 144 for the of the second candidate capacitor 133 Two ends are coupled to second voltage V2.At this point, the second candidate capacitor 133 can be switched to charge mode and be charged to pre- with one Determine cross-pressure value (in this case, it is the voltage differences between second voltage V2 and the first predetermined voltage Vcm).
In another example when capacitance selection circuit 170 controls the 11st switch 165 for the first end coupling of the 6th candidate capacitor 155 When being connected to the input terminal of the second gain stage 120, capacitance selection circuit 170 can control the 12nd switch 166 for the 6th candidate capacitor 155 second end is coupled to the output end of the second gain stage 120.At this point, the 6th candidate capacitor 155 can participate in output signal The generation of Vout operates.On the other hand, when capacitance selection circuit 170 controls the 11st switch 165 for the 6th candidate capacitor 155 When first end is coupled to the first predetermined voltage Vcm, capacitance selection circuit 170 can then control the 12nd switch 166 for the 6th candidate The second end of capacitor 155 is coupled to tertiary voltage V3.At this point, the 6th candidate capacitor 155 can be switched to charge mode and be filled Electricity is to a predetermined cross-pressure value (in this case, it is the voltage differences between tertiary voltage V3 and the first predetermined voltage Vcm).
The mode that capacitance selection circuit 170 controls the switch at other candidate capacitor both ends is identical as previous cases, is succinct For the sake of, details are not described herein.
In implementation, aforementioned first voltage V1, second voltage V2, the size of tertiary voltage V3 be not identical, in other words, different Candidate capacitor charging after can have different cross-pressures.
Each of operational amplifier 100 candidate's capacitor can all be realized with a Single Capacitance element, can also use parallel connection Two or more capacity cells combine to realize.In addition, the above-mentioned first to the 12nd switch 141-146 and 161- 166 can all be realized with the combination of multiple transistors, and the combination for the logic gate appropriate that can also be arranged in pairs or groups with multiple transistors is come real It is existing.
In certain embodiments, multiple candidate capacitor 131-135 in operational amplifier 100 and 151-155 can be divided into two A capacitance group charges in turn, and capacitance selection circuit 170 can then be selected to participate in exporting from two capacitance groups in turn and believe The selected capacitor of the generation running of number Vout, and selected capacitor is coupled to the second gain stage 120.
For example, in one embodiment, first capacitor can be set by first in Fig. 1 to third candidate's capacitor 131-135 Group, and the second capacitance group is set by the 4th to the 6th candidate capacitor 151-155.In running, when capacitance selection circuit 170 selects When selecting generation running of the part candidate's capacitor in one of capacitance group as selected capacitor to participate in output signal Vout, electricity Hold the respective switch that selection circuit 170 can control another capacitance group, so that all candidate capacitors one in another capacitance group It rises and is switched to charge mode and is charged to respectively with different cross-pressure values.
For example, when capacitance selection circuit 170 controls related switch, by first capacitor group, (in this case, it is first to third to be waited Select capacitor 131-135) in the candidate capacitor in part when being coupled to the second gain stage 120, capacitance selection circuit 170 controllable second Capacitance group (in this case, it is the 4th to the 6th candidate capacitor 151-155) to inductive switch 161-166, by the 4th to the 6th candidate Capacitor 151-155 switches to charge mode, so that the 4th to the 6th candidate capacitor 151-155 charges together, and is electrically charged respectively To with different cross-pressure values.
In another example when capacitance selection circuit 170 controls related switch, by the second capacitance group, (in this case, it is the 4th to the 6th Candidate capacitor 151-155) in the candidate capacitor in part when being coupled to the second gain stage 120, capacitance selection circuit 170 controllable the One capacitance group (in this case, it is first to third candidate capacitor 131-135) to inductive switch 141-146, first to third is waited It selects capacitor 131-135 to switch to charge mode, so that first to third candidate's capacitor 131-135 charges together, and is filled respectively Electricity is to different cross-pressure values.
Therefore, capacitance selection circuit 170 can select part from aforementioned first capacitor group in one first operation time period T1 Candidate capacitor is electric by aforementioned second as the selected capacitor that be coupled to the second gain stage 120, and in the first operation time period T1 All candidate capacitors (also that is, the 4th to the 6th candidate capacitor 151-155) of Rong Zuzhong switch to charge mode together and are filled Electricity.
In one second operation time period T2 after the first operation time period T1, capacitance selection circuit 170 can change from being completed Part candidate's capacitor is selected as the selected capacitor that be coupled to the second gain stage 120 in aforementioned second capacitance group of charging, and By all candidate capacitors in aforementioned first capacitor group (also that is, first to third candidate's capacitor in the second operation time period T2 131-135) charge mode is switched to together to charge.
Next, capacitance selection circuit 170 can reelect in the third operation time period T3 after the second operation time period T2 It selects and first part candidate's capacitor into third candidate's capacitor 131-135 of charging is completed as being coupled to the second gain stage 120 selected capacitor, and the 4th to the 6th candidate capacitor 151-155 is switched into charge mode one in third operation time period T3 It rises and charges.
In subsequent operation time period, capacitance selection circuit 170, which can be repeated, aforementioned to be divided multiple candidate capacitors Group wheel current charge, and the suitable operating mode for selecting capacitor is selected from the capacitance group of charging complete.
In implementation, capacitance selection circuit 170, can be from the capacitance group precharged in each operation time period above-mentioned Selected in (precharged capacitor group) with can reduce be coupled to the second gain stage 120 after needed for charging Or part candidate's capacitor of the appropriate cross-pressure of discharge time is as selected capacitor, and switch relevant switch so that aforementioned first to 6th candidate capacitor 131-135 and 151-155 only selected capacitor in the same time is coupled to the second gain stage 120.
For example, Fig. 2 is the simplified schematic diagram of an embodiment of capacitance selection circuit 170.In the embodiment of fig. 2, electric Holding selection circuit 170 includes multiple comparators (for example, the exemplary comparator 210,220 and 230 being painted in figure), and Select logic 240.
In capacitance selection circuit 170, each comparator is arranged to the input signal Vin of front stage circuits 102 and a pair Reference signal is answered to be compared.For example, first comparator 210 is arranged to input signal Vin and the first reference signal Vref_1 It is compared, to generate one first comparison signal C1.Second comparator 220 is arranged to input signal Vin and second with reference to letter Number Vref_2 is compared, to generate one second comparison signal C2.Third comparator 230 is arranged to input signal Vin and Three reference signal Vref_n are compared, and to generate a third comparison signal Cn, the rest may be inferred for remaining.In one embodiment, preceding The signal value for stating third reference signal Vref_n is greater than the signal value of the second reference signal Vref_2, and the second reference signal The signal value of Vref_2 is greater than the signal value of the first reference signal Vref_1.
Selection logic 240 is coupled to multiple comparator 210-230 above-mentioned, and is arranged to according to comparator 210-230's Comparison result selects part candidate's capacitor with appropriate cross-pressure as selected capacitor from the capacitance group precharged.This Outside, selection logic 240 can also generate the multiple control signal for controlling the first to the 6th switch 141-146, all to be arranged The coupling mode of candidate capacitor, so that the aforementioned first to the 6th candidate capacitor 131-135 and 151-155 only has in the same time Selected capacitor can be coupled to the second gain stage 120, and other candidate capacitors then will not all be coupled to the second gain stage 120.In other words, only selected capacitor can participate in the operation that the second gain stage 120 generates output signal Vout next time, His candidate capacitor then all cannot participate in the generation running of output signal Vout next time.
As long as being suitably set the signal value of aforesaid plurality of reference signal Vref_1-Vref_n, select logic 240 can root According to multiple comparison signal C1-Cn that comparator 210-230 is exported, the signal value magnitude range of input signal Vin is judged.
For example, if the first comparison signal C1 shows that the signal value of input signal Vin is greater than the first reference signal Vref_1 Signal value, the second comparison signal C2 show input signal Vin signal value of the signal value less than the second reference signal Vref_2, And third comparison signal Cn shows that the signal value of input signal Vin is less than the signal value of third reference signal Vref_n, then selects Logic 240 can determine the size of input signal Vin accordingly, between the first reference signal Vref_1 and the second reference signal Vref_2 Between the two.
In another example if the first comparison signal C1 shows that the signal value of input signal Vin is greater than the first reference signal Vref_ 1 signal value, the second comparison signal C2 show that the signal value of input signal Vin is greater than the signal of the second reference signal Vref_2 Value and third comparison signal Cn show that the signal value of input signal Vin is less than the signal value of third reference signal Vref_n, then select The size of input signal Vin can be determined accordingly by selecting logic 240, between the second reference signal Vref_2 and third reference signal Vref_n is between the two.
Since the size of first voltage V1 above-mentioned, second voltage V2, tertiary voltage V3 and the first predetermined voltage Vcm exist It is all given value (given value) when circuit design, so cross-pressure of each candidate's capacitor after precharge is also Given value.
As previously mentioned, input signal Vin and the size relation of output signal Vout between the two, depend primarily on the first increasing The yield value of 120 the two of beneficial grade 110 and the second gain stage.It therefore, can be according to the ideal of output signal Vout in circuit design Matching relationship between size and the most suitable cross-pressure value of candidate capacitor derives the size and candidate's capacitor of input signal Vin Enantiomorphic relationship between most suitable cross-pressure value.It in implementation, selects logic 240 that can realize using the combination of various logic lock, and selects The actual implementation mode for selecting logic 240 can be according between the size of input signal Vin and the ideal cross-pressure value of candidate capacitor Enantiomorphic relationship is appropriately designed to do, and enables that logic 240 is selected to select the choosing with appropriate cross-pressure value from multiple candidate capacitors Capacitor is determined, to reduce the charge or discharge time needed for selected capacitor is coupled to after the second gain stage 120.
For example, in one embodiment, the operational logic that select logic 240 can be designed in input signal Vin less than the When one reference signal Vref_1, select cross-pressure close to candidate's electricity of the voltage difference of first voltage V1 and the first predetermined voltage Vcm Hold as selected capacitor；When input signal Vin is between the first reference signal Vref_1 and the second reference signal Vref_2, Select cross-pressure close to the candidate capacitor of the voltage difference of second voltage V2 and the first predetermined voltage Vcm as selected capacitor；And When input signal Vin is between the second reference signal Vref_2 and third reference signal Vref_n, select cross-pressure close to third The candidate capacitor of the voltage difference of voltage V3 and the first predetermined voltage Vcm is as selected capacitor.
In another example in another embodiment, the operational logic that select logic 240 can be designed to be situated between in input signal Vin When between the first reference signal Vref_1 and the second reference signal Vref_2, select cross-pressure pre- close to first voltage V1 and first The candidate capacitor of the voltage difference of constant voltage Vcm is as selected capacitor；In input signal Vin between the second reference signal Vref_2 When between third reference signal Vref_n, select cross-pressure close to the voltage difference of second voltage V2 and the first predetermined voltage Vcm Candidate capacitor as selected capacitor；And when input signal Vin is greater than third reference signal Vref_n, select cross-pressure close to the The candidate capacitor of the voltage difference of three voltage V3 and the first predetermined voltage Vcm is as selected capacitor.
As previously mentioned, first capacitor group above-mentioned can charge in turn with the second capacitance group.Select logic 240 in each Principle can be selected according to aforementioned in operation time period, the candidate with appropriate cross-pressure value is picked out from the capacitance group of charging complete Capacitor is as the selected capacitor that be coupled to the second gain stage 120.
For example, selecting logic 240 can be according to the ratio of comparator 210-230 at that time in the first operation time period T1 above-mentioned Compared with as a result, from being selected in first capacitor group (in this case, it is first to third candidate capacitor 131-135) with after capable of reducing The part candidate's capacitor for continuing the appropriate cross-pressure value of required charge or discharge time, as being coupled to the second gain stage 120 Selected capacitor, and the multiple control signal for controlling the first to the 6th switch 141-146 is generated, selected capacitor is coupled to Second gain stage 120.In the first operation time period T1, select logic 240 that can also generate for controlling the 7th to the 12nd switch The multiple control signal of 161-166, will be in the second capacitance group (in this case, it is the 4th to the 6th candidate capacitor 151-155) Candidate capacitor all switches to charge mode, without coupling with the second gain stage 120.
In the second operation time period T2 later, select logic 240 then can be according to the comparison knot of comparator 210-230 at that time Fruit, the appropriate of subsequent required charge or discharge time can be reduced by changing to select to have from the second capacitance group that charging is completed Part candidate's capacitor of cross-pressure value, as the selected capacitor that be coupled to the second gain stage 120, and generate for control the 7th to Selected capacitor is coupled to the second gain stage 120 by the multiple control signal of the 12nd switch 161-166.In the second operation In section T2, select logic 240 that can also generate the multiple control signal for controlling the first to the 6th switch 141-146, by the Candidate capacitor in one capacitance group all switches to charge mode, without coupling with the second gain stage 120.
In subsequent operation time period, select logic 240 can be according to the comparison result of comparator 210-230 at that time, from Again suitable candidate capacitor is selected in the capacitance group of charging complete as selected capacitor.
Therefore, in capacitance selection circuit 170, from first capacitor group, (in this case, it is first to third candidate's capacitor 131- 135) it is selected in front of being coupled to the suitable candidate capacitor of the second gain stage 120, first to third candidate's capacitor 131-135 just It has been precharged to respectively with different cross-pressure values.Similarly, capacitance selection circuit 170 from the second capacitance group (this Example in be the 4th to the 6th candidate capacitor 151-155) in select to be coupled to the second gain stage 120 suitable candidate capacitor it Before, the 4th to the 6th candidate capacitor 151-155 has just been precharged to respectively with different cross-pressure values.
By preceding description it is found that being coupled to the choosing of the second gain stage 120 by capacitance selection circuit 170 in each operation time period Determine capacitor, has been precharged to appropriate cross-pressure value.Therefore, selected capacitor is coupled to institute after the second gain stage 120 The charge or discharge time needed can substantially shorten.In this way, just can effectively promote the response speed of operational amplifier 100 Degree, and then improve the overall operation efficiency or service speed of the circuit using operational amplifier 100.
In addition, using aforementioned by multiple candidate capacitor 131-135 and 151-155 grouping wheel current charge and provide in turn will quilt Be coupled to the mechanism of the feedback capacity of the second gain stage 120, can more shorten selected capacitor be coupled to the second gain stage 120 it The charge or discharge time needed for afterwards, therefore the response speed of operational amplifier 100 can be further speeded up, and further promoted and used The overall operation efficiency or service speed of the circuit of operational amplifier 100.
It, can also alternately the circuit different from two be arranged in pairs or groups fortune in turn by aforementioned opamp 100 in practical application Make, so that the same operational amplifier 100 can allow two different circuits to share, and then reduces the area of integrated circuit.
For example, operational amplifier 100 can be applied in all kinds of pipeline system analog-digital converter (pipelined Analog-to-digital converter, pipelined ADC) in, and two different circuit-levels is allowed to share.
Referring to FIG. 3, its depicted pipeline system analog-digital converter 300 for a first embodiment of the invention simplifies Functional block diagram afterwards.Fig. 4 is the simplified local function square of an embodiment of pipeline system analog-digital converter 300 Figure.
Pipeline system analog-digital converter 300 is used to an analog input signal Sin being converted into a digital output signal Dout, and include the circuit-level (for example, exemplary circuit grade 301-304 depicted in Fig. 3) of multiple connectings, rear end simulation Digital quantizer 305 and timing adjustment and error correction circuit 306.In the fig. 3 embodiment, pipeline system simulates number Word converter 300 is to belong to single channel pipeline system analog-digital converter.
Circuit-level 301-304 in pipeline system analog-digital converter 300 has similar circuit framework.For side Just it for the sake of illustrating, is only said below with the circuit-level 302 for belonging to N grades and belonging to for N+1 grades of circuit-level 303 It is bright.
As shown in figure 3, circuit-level 302 includes one first analog-digital converter 310 and one first multiplication formula number mould Quasi- converter 320.First analog-digital converter 310 is used for input signal (the referred to here as first input letter to circuit-level 302 Number Vin_1) simulation is carried out to digital conversion process.First multiplication formula digital analog converter 320 is used to simulate according to first The digital value that digital quantizer 310 generates carries out a number to analog-converted processing, to produce to the first input signal Vin_1 It gives birth to and transmits an analog signal Vin_2 to next circuit-level 303.
First multiplication formula digital analog converter 320 includes one first sampling and holding circuit 322, one first digital simulation Converter 324, one first subtracter 326 and one first operational amplifier 328.
First sampling is arranged to be sampled the first input signal Vin_1 and keeps operating with holding circuit 322.First One number of digital value progress to the simulation that digital analog converter 324 is arranged to generate the first analog-digital converter 310 turns Processing is changed, to generate one first analog signal corresponding with the first input signal Vin_1.First sampling with holding circuit 322 with The output of both first digital analog converters 324 will form one first subtracted signal after the processing of the first subtracter 326 S1.First operational amplifier 328 can then amplify the first subtracted signal S1, to generate analog signal Vin_2.
Similarly, circuit-level 303 includes that one second analog-digital converter 330 and one second multiplication formula digital simulation turn Parallel operation 340.Second analog-digital converter 330 is used for the input signal of circuit-level 303 (that is, analog signal Vin_ above-mentioned 2, hereon referred to as the second input signal Vin_2) simulation is carried out to digital conversion process.Second multiplication formula digital analog converter 340 digital value for generating according to the second analog-digital converter 330 carries out a number to the second input signal Vin_2 To analog-converted processing, to generate and transmit an analog signal to next circuit-level.
Second multiplication formula digital analog converter 340 includes one second sampling and holding circuit 342, one second digital simulation Converter 344, one second subtracter 346 and a second operational amplifier 348.
Second sampling is arranged to be sampled the second input signal Vin_2 and keeps operating with holding circuit 342.Second One number of digital value progress to the simulation that digital analog converter 344 is arranged to generate the second analog-digital converter 330 turns Processing is changed, to generate one second analog signal corresponding with the second input signal Vin_2.Second sampling with holding circuit 342 with The output of both second digital analog converters 344 will form one second subtracted signal after the processing of the second subtracter 346 S2.Second operational amplifier 348 can then amplify the second subtracted signal S2, to generate the simulation letter that be transferred to next circuit-level Number.
The circuit framework and function mode of other circuit-levels 301 and 304 in pipeline system analog-digital converter 300 are all Identical as 303 as circuit-level 302 above-mentioned, therefore, the aforementioned circuit framework description in relation to circuit-level 302 and 303 is also suitable for Other circuit-levels 301 and 304.
Digital value caused by each circuit-level can be sent to timing adjustment and error correction circuit 306.In addition to this, The analog signal that its previous circuit-level 304 transmits can be converted into a digital value by rear end analog-digital converter 305, and be transmitted To timing adjustment and error correction circuit 306.
According to multiple digital values that all circuit-levels and rear end analog-digital converter 305 transmit, timing adjustment and error Correcting circuit 306 will do it timing adjustment grade error correction running, defeated to generate number corresponding with analog input signal Sin Signal Dout out.
By preceding description it is found that requiring to utilize operation in each circuit-level of pipeline system analog-digital converter 300 Amplifier amplifies coherent signal.
In running, the operational amplifier in each circuit-level does not need to carry out signal amplification running always.For example, working as The first operational amplifier 328 in N grades of circuit-level 302 is when carrying out signal amplification running, N+1 grades of circuit-level 303 In second operational amplifier 348 can because second sampling with holding circuit 342 be sampled running without progress signal Amplification running.In another example when the second operational amplifier 348 in N+1 grades of circuit-level 303 is carrying out signal amplification running When, the first operational amplifier 328 in N grades of circuit-level 302 can be sampled and be sampled with holding circuit 322 because of first Running is without carrying out signal amplification running.
Therefore, in pipeline system analog-digital converter 300, the circuit-level of an odd level can be with another even number The circuit-level of grade shares the same operational amplifier above-mentioned 100.
For example, Fig. 4 is the simplified local function side of an embodiment of the pipeline system analog-digital converter 300 of Fig. 3 Block figure.
The first switching type capacitor network 420 in Fig. 4 be arranged to be sampled the first input signal Vin_1 above-mentioned with Running is kept, can be used to realize the function of the first sampling and holding circuit 322 in aforementioned circuit grade 302.Second in Fig. 4 cuts It changes formula capacitance network 440 to be then arranged to be sampled the second input signal Vin_2 and keep operating, can be used to realize aforementioned electricity The function of the second sampling and holding circuit 342 in road grade 303.
In the fig. 4 embodiment, the first switching type capacitor network 420 include a first capacitor 421, one second capacitor 423, The 13rd switch 425,1 the 14th switch 427 and 1 the 15th switch 429.Second switching type capacitor network 440 then wraps 445,1 the 17th switch 447 and an eighteenmo are closed containing a third capacitor 441, one the 4th capacitor 443, a sixteenmo Close 449.13rd switch 425 above-mentioned, the 14th switch 427, the 15th switch 429, sixteenmo, which close the 445, the 17th, to be opened The switching running of 447 and eighteenmo pass 449 is closed, can be simulated by timing adjustment and error correction circuit 306 or pipeline system Other sequential control circuits (not being painted) in digital quantizer 300 are controlled.
In the first switching type capacitor network 420, the 13rd switch 425 is coupled to the first end of first capacitor 421, is used for By first capacitor 421 be selectively coupled to circuit-level 302 input signal (in this case, it is the first input signal Vin_1) or The output signal Vout of operational amplifier 100.14th switch 427 is coupled to the first end of the second capacitor 423, is used for second Capacitor 423 is selectively coupled to a first input signal Vin_1 or predetermined voltage Vr1.15th switch 429 is coupled to first The second end of the second end of capacitor 421 and the second capacitor 423, for first capacitor 421 and the second capacitor 423 is selective together Ground is coupled to the first subtracter 326 or another predetermined voltage Vcmi.In implementation, predetermined voltage Vr1 can be a fixed voltage, or It is the common-mode voltage of the first digital analog converter 324, and predetermined voltage Vcmi can be a fixed voltage or the first switching The common-mode voltage of formula capacitance network 420.
In the second switching type capacitor network 440, sixteenmo closes 445 first ends for being coupled to third capacitor 441, is used for By third capacitor 441 be selectively coupled to circuit-level 303 input signal (in this case, it is the second input signal Vin_2) or The output signal Vout of operational amplifier 100.17th switch 447 is coupled to the first end of the 4th capacitor 443, is used for the 4th Capacitor 443 is selectively coupled to a second input signal Vin_2 or predetermined voltage Vr2.Eighteenmo closes 449 and is coupled to third The second end of the second end of capacitor 441 and the 4th capacitor 443, for third capacitor 441 and the 4th capacitor 443 is selective together Ground is coupled to the second subtracter 346 or predetermined voltage Vcmi.In implementation, predetermined voltage Vr2 can be a fixed voltage or The common-mode voltage of two digital analog converters 344.
In implementation, switch 425,427,429,445,447 and 449 above-mentioned all can be with the combination of multiple transistors come real Existing, the combination of the logic gate appropriate that can also be arranged in pairs or groups with multiple transistors is realized.
Function block 324 in Fig. 4,326,344, with 346 function mode then respectively with the corresponding function in earlier figures 3 Square is identical.
It note that in the pipeline system analog-digital converter 300 of Fig. 4, the first operational amplifier in earlier figures 3 328 and the functions of both second operational amplifiers 348 are realized using the same operational amplifier 100.Specifically, operation Amplifier 100 can play the part of the first operational amplifier 328 and second operational amplifier in Fig. 3 in different operation time periods respectively Both 348 role.
For example, when the operational amplifier 100 in Fig. 4 will realize the function of the first operational amplifier 328 in Fig. 3, fortune Amplifier 100 is calculated using the first subtracted signal S1 as the first signal N1, and makees input letter using the first input signal Vin_1 Number Vin.Similarly, when the operational amplifier 100 in Fig. 4 will realize the function of the second operational amplifier 348 in Fig. 3, fortune Amplifier 100 is calculated using the second subtracted signal S2 as the first signal N1, and makees input letter using the second input signal Vin_2 Number Vin.
In one embodiment, first is coupled to as shown in figure 4, can be arranged in pipeline system analog-digital converter 300 Subtracter 326, the second subtracter 346, the output switch 480 with the first gain stage 110, and it is coupled to capacitance selection circuit 170 input switch 490.Output switch 480 can be set to selectivity and export the first subtracted signal S1 or the second subtracted signal S2 is to the first gain stage 110 as the first signal N1 above-mentioned.Input switch 490 can be set to selectivity and export the first input Signal Vin_1 or the second input signal Vin_2 is to capacitance selection circuit 170 as input signal Vin above-mentioned.
It is identical as the embodiment of Fig. 1, meeting foundation the first signal N1 generation output signal Vout of operational amplifier 100, and according to The coupling mode for switching multiple candidate capacitor 131-135 and 151-155 according to the size of input signal Vin, so that above-mentioned multiple Only some candidate capacitor can be used to participate in output signal candidate capacitor 131-135 and 151-155 in the same time The generation of Vout operates.
In running, operational amplifier 100 can play the part of the first operational amplifier 328 and the second operation in Fig. 3 in turn The role of both amplifiers 348.For example, operational amplifier 100 can need to carry out the first subtracted signal S1 in circuit-level 302 In the specific operation period (for example, first operation time period T1 above-mentioned) for amplifying running, play the part of the first operation amplifier in Fig. 3 The role of device 328.Later, need to amplify the second subtracted signal S2 next operation time period of running in circuit-level 303 In (for example, second operation time period T2 above-mentioned), operational amplifier 100 can disguise oneself as to drill the second operational amplifier in Fig. 3 again 348 role.
Need to amplify the first subtracted signal S1 in circuit-level 302 the of running in aforementioned opamp 100 In one operation time period T1, timing adjustment and controllable 13rd switch of error correction circuit 306 (or other sequential control circuits) 425 are coupled to the first end of first capacitor 421 the output signal Vout of operational amplifier 100, and synchronously control the 14th is opened It closes 427 and the first end of second capacitor 423 is coupled to predetermined voltage Vr1, and the 15th switch 429 of synchronously control is by first capacitor 421 second end is coupled to the first subtracter 326 together with the second end of the second capacitor 423.In the first operation time period T1, when Sequence adjustment and error correction circuit 306 (or other sequential control circuits) can control sixteenmo to close 445 for third capacitor 441 First end is coupled to the second input signal Vin_2, and the 17th switch 447 of synchronously control is by the first end coupling of the 4th capacitor 443 It is connected to the second input signal Vin_2, and synchronously control eighteenmo closes 449 for the second end of third capacitor 441 and the 4th capacitor 443 second end is coupled to predetermined voltage Vcmi together.At this point, timing adjustment and (or other timing controls of error correction circuit 306 Circuit processed) it can control output switch 480 to export the first subtracted signal S1 to the first gain stage 110, and it is defeated to control input switch 490 The first input signal Vin_1 is to capacitance selection circuit 170 out.
Later, it needs to amplify running to the second subtracted signal S2 in circuit-level 303 in aforementioned opamp 100 The second operation time period T2 in, timing adjustment and error correction circuit 306 (or other sequential control circuits) the controllable 13rd The first end of first capacitor 421 is coupled to the first input signal Vin_1 by switch 425, and the 14th switch 427 of synchronously control will The first end of second capacitor 423 is coupled to the first input signal Vin_1, and the 15th switch 429 of synchronously control is by first capacitor 421 second end is coupled to predetermined voltage Vcmi together with the second end of the second capacitor 423.In the second operation time period T2, when Sequence adjustment and error correction circuit 306 (or other sequential control circuits) can control sixteenmo to close 445 for third capacitor 441 First end is coupled to the output signal Vout of operational amplifier 100, and the 17th switch 447 of synchronously control is by the 4th capacitor 443 First end be coupled to predetermined voltage Vr2, and synchronously control eighteenmo closes 449 for the second end of third capacitor 441 and the 4th The second end of capacitor 443 is coupled to the second subtracter 346 together.At this point, timing adjustment and error correction circuit 306 (or other Sequential control circuit) it can control output switch 480 to export the second subtracted signal S2 to the first gain stage 110, and control input and open 490 the second input signal Vin_2 of output are closed to capacitance selection circuit 170.
In this way, which operational amplifier 100 only can subtract each other letter to first in circuit-level 302 in the first operation time period T1 Number S1 amplifies running, and can only put to the second subtracted signal S2 in circuit-level 303 in the second operation time period T2 Big running.
As long as timing adjustment and error correction circuit 306 (or other sequential control circuits) are suitably set aforementioned switches 425,427,429,445,447,449,480, the switching sequence with 490, operational amplifier 100 just can in turn with pipeline system mould Other circuits in the different circuit-levels of quasi- digital quantizer 300 are arranged in pairs or groups running so that different circuit-levels be able to share it is same A operational amplifier 100.
By preceding description it is found that the function block 420 in Fig. 4,440,324,326,344, the combination with 346, are equivalent to It is one of the embodiment of the front stage circuits 102 in earlier figures 1.
It is coupled to the selected capacitor of the second gain stage 120 in each operation time period, being precharged to has suitably Cross-pressure value.Therefore, the required charge or discharge time can substantially contract after selected capacitor is coupled to the second gain stage 120 It is short.In this way, just can effectively promote the response speed of operational amplifier 100, and then improve pipeline system Analog-digital Converter The overall operation efficiency or service speed of device 300.
In addition, using aforementioned by multiple candidate capacitor 131-135 and 151-155 grouping wheel current charge and provide in turn will quilt Be coupled to the mechanism of the feedback capacity of the second gain stage 120, can more shorten selected capacitor be coupled to the second gain stage 120 it The charge or discharge time needed for afterwards, therefore the response speed of operational amplifier 100 can be further speeded up, and further promote flowing water The overall operation efficiency or service speed of wire type analog-digital converter 300.
Aforementioned element connection relationship, embodiment, function mode and correlation in relation to the operational amplifier 100 in Fig. 1 The explanation such as advantage, is also suitable for the embodiment of Fig. 4.For brevity, not repeated description herein.
Due to other circuits in the same operational amplifier 100 circuit-level 302 and 303 alternately different from two Element is arranged in pairs or groups running in turn, so two different circuit-levels 302 and 303 need to only share the same operational amplifier when operating 100.In this way, the operational amplifier that required setting in pipeline system analog-digital converter 300 will can be greatly decreased Quantity, thus reduce pipeline system analog-digital converter 300 integrated circuit area.
It note that the circuit-level 302 and 303 for sharing the same operational amplifier 100 in the aforementioned embodiment is same logical Two adjacent circuit grades in road, but this is a demonstration example, rather than limit to actual implementation mode of the invention.In implementation, to be total to It is not limited to be two adjacent circuit grades with two circuit-levels of the same operational amplifier 100.
Referring to FIG. 5, its depicted pipeline system analog-digital converter 500 for a second embodiment of the invention simplifies Functional block diagram afterwards.Fig. 6 is the simplified local function square of an embodiment of pipeline system analog-digital converter 500 Figure.
Pipeline system analog-digital converter 500 is binary channels pipeline system analog-digital converter, can be by simulation input Signal Sin is converted into two digital output signals Dout1 and Dout2.
Pipeline system analog-digital converter 500 is in addition to the aforementioned multiple circuit-level 301-304 for belonging to same channel, rear end Except analog-digital converter 305 and timing adjustment and error correction circuit 306, further comprises and belong to another channel Multiple connecting circuit grades (for example, exemplary circuit grade 501-504 depicted in Fig. 5), a rear end analog-digital converter 505 and one timing adjustment and error correction circuit 506.
The circuit framework in two channels of pipeline system analog-digital converter 500 is all identical, only in two channels Circuit time sequences are different.The electricity of circuit-level 301-304 and 501-504 in pipeline system analog-digital converter 500 Road framework and function mode are all identical as 303 as circuit-level 302 above-mentioned.For example, N grades of second channel (also that is, circuit 502) grade includes one second analog-digital converter 530 and one second multiplication formula digital analog converter 540.Second simulation Digital quantizer 530 is used to carry out a simulation extremely to the input signal (referred to here as the second input signal Vin_2) of circuit-level 502 Digital conversion process.Second multiplication formula digital analog converter 540 is used for one according to the generation of the second analog-digital converter 530 Digital value carries out a number to analog-converted processing, to generate and transmit an analog signal under to the second input signal Vin_2 One circuit-level.
It is identical as the second multiplication formula digital analog converter 340 above-mentioned, the second multiplication formula digital analog converter 540 packet Containing one second sampling and holding circuit 542, one second digital analog converter 544, one second subtracter 546 and one second Operational amplifier 548.Second sampling is arranged to be sampled the second input signal Vin_2 and keeps transporting with holding circuit 542 Make.Second digital analog converter 544 is arranged to carry out a number extremely to the digital value that the second analog-digital converter 530 generates Analog-converted processing, to generate one second analog signal.Second sampling and holding circuit 542 and the second digital analog converter Both 544 output will form one second subtracted signal S2 after the processing of the second subtracter 546.Second operational amplifier 548 can amplify the second subtracted signal S2, to generate the analog signal that be transferred to next circuit-level.
It is aforementioned in relation to circuit-level 302 and 303 circuit framework description, also the circuit-level 301-304 suitable for Fig. 5 and 501-504。
It is identical as the embodiment of earlier figures 3, benefit is required in each circuit-level of pipeline system analog-digital converter 500 Amplify coherent signal with operational amplifier, but the operational amplifier in each circuit-level does not need to carry out signal amplification always Running.
For example, when the first operational amplifier 328 in N grades (also that is, circuit-levels 302) of first passage is carrying out signal When amplification running, second operational amplifier 548 in N grade (also that is, the circuit-levels 502) of second channel can sample because of second and Holding circuit 542 is being sampled running without carrying out signal amplification running.In another example when second in circuit-level 502 For operational amplifier 548 when carrying out signal amplification running, the first operational amplifier 328 in circuit-level 302 can be because of the first sampling Running is being sampled with holding circuit 322 to operate without carrying out signal amplification.
Therefore, in pipeline system analog-digital converter 500, an odd level circuit in first passage can be with Some odd level circuit in second channel shares the same operational amplifier 100.Similarly, an idol in first passage Several levels circuit can also share the same operational amplifier 100 with the even level circuit of some in second channel.
For example, Fig. 6 is the simplified local function side of an embodiment of the pipeline system analog-digital converter 500 of Fig. 5 Block figure.
The second switching type capacitor network 640 in Fig. 6 is arranged to be sampled the second input signal Vin_2 and keeps transporting Make, can be used to realize the function of the second sampling and holding circuit 542 in aforementioned circuit grade 502.
In the second switching type capacitor network 640, sixteenmo closes 645 first ends for being coupled to third capacitor 641, is used for By third capacitor 641 be selectively coupled to circuit-level 502 input signal (in this case, it is the second input signal Vin_2) or The output signal Vout of operational amplifier 100.17th switch 647 is coupled to the first end of the 4th capacitor 643, is used for the 4th Capacitor 643 is selectively coupled to the second input signal Vin_2 or predetermined voltage Vr2.Eighteenmo closes 649 and is coupled to third electricity Hold 641 second end and the second end of the 4th capacitor 643, for by third capacitor 641 and the 4th capacitor 643 together selectively It is coupled to the second subtracter 546 or predetermined voltage Vcmi.Sixteenmo above-mentioned closes the 645, the 17th switch 647 and the tenth The switching of eight switches 649 operates, can be by timing adjustment and error correction circuit 506 or pipeline system analog-digital converter 500 In other sequential control circuits (not being painted) controlled.In implementation, predetermined voltage Vr2 can be a fixed voltage, or It is the common-mode voltage of the second digital analog converter 544.
In implementation, switch above-mentioned 645,647, can all be realized with the combination of multiple transistors with 649, can also use more The arrange in pairs or groups combination of logic gate appropriate of a transistor is realized.
It note that in the pipeline system analog-digital converter 500 of Fig. 6, the first operational amplifier in earlier figures 5 328 and the functions of both second operational amplifiers 548 are realized using the same operational amplifier 100.Specifically, operation Amplifier 100 can play the part of the first operational amplifier 328 and second operational amplifier in Fig. 5 in different operation time periods respectively Both 548 role.
For example, when the operational amplifier 100 in Fig. 6 will realize the function of the first operational amplifier 328 in Fig. 5, fortune Amplifier 100 is calculated using the first subtracted signal S1 as the first signal N1, and makees input letter using the first input signal Vin_1 Number Vin.Similarly, when the operational amplifier 100 in Fig. 6 will realize the function of the second operational amplifier 548 in Fig. 5, fortune Amplifier 100 is calculated using the second subtracted signal S2 as the first signal N1, and makees input letter using the second input signal Vin_2 Number Vin.
Identical as the embodiment of Fig. 4, output switch 480 can be set to selectivity and export the first subtracted signal S1 or the second phase Cut signal S2 is to the first gain stage 110 as the first signal N1 above-mentioned.Input switch 490 can be set to selectivity and export the One input signal Vin_1 or the second input signal Vin_2 is to capacitance selection circuit 170 as input signal Vin above-mentioned.? In the present embodiment, when exporting output the first subtracted signal S1 to the first gain stage 110 of switch 480, input switch 490 can be exported First input signal Vin_1 is to capacitance selection circuit 170, and when output switch 480 exports the second subtracted signal S2 to first increasing When beneficial grade 110, input switch 490 can export the second input signal Vin_2 to capacitance selection circuit 170.
Framework and the function mode of function block 420,324,326,544 and 546 in Fig. 6, all and in earlier figures 4 Corresponding function square is identical.
It is identical as the embodiment of Fig. 1, meeting foundation the first signal N1 generation output signal Vout of operational amplifier 100, and according to The coupling mode for switching multiple candidate capacitor 131-135 and 151-155 according to the size of input signal Vin, so that above-mentioned multiple Only some candidate capacitor can be used to participate in output signal candidate capacitor 131-135 and 151-155 in the same time The generation of Vout operates.
In running, operational amplifier 100 can play the part of the first operational amplifier 328 and the second operation in Fig. 5 in turn The role of both amplifiers 548.For example, operational amplifier 100 can need to carry out the first subtracted signal S1 in circuit-level 302 In the specific operation period (for example, first operation time period T1 above-mentioned) for amplifying running, play the part of the first operation amplifier in Fig. 5 The role of device 328.Later, need to amplify the second subtracted signal S2 next operation time period of running in circuit-level 502 In (for example, second operation time period T2 above-mentioned), operational amplifier 100 can disguise oneself as to drill the second operational amplifier in Fig. 5 again 548 role.
Need to amplify the first subtracted signal S1 in circuit-level 302 the of running in aforementioned opamp 100 In one operation time period T1, timing adjustment and controllable 13rd switch of error correction circuit 306 (or other sequential control circuits) 425 are coupled to the first end of first capacitor 421 the output signal Vout of operational amplifier 100, and synchronously control the 14th is opened It closes 427 and the first end of second capacitor 423 is coupled to predetermined voltage Vr1, and the 15th switch 429 of synchronously control is by first capacitor 421 second end is coupled to the first subtracter 326 together with the second end of the second capacitor 423.In the first operation time period T1, when Sequence adjustment and error correction circuit 506 (or other sequential control circuits) can control sixteenmo to close 645 for third capacitor 641 First end is coupled to the second input signal Vin_2, and the 17th switch 647 of synchronously control is by the first end coupling of the 4th capacitor 643 It is connected to the second input signal Vin_2, and synchronously control eighteenmo closes 649 for the second end of third capacitor 641 and the 4th capacitor 643 second end is coupled to predetermined voltage Vcmi together.At this point, timing adjustment and error correction circuit 306,506 or other when The controllable output switch 480 of sequence control circuit exports the first subtracted signal S1 to the first gain stage 110, and controls input switch 490 export the first input signal Vin_1 to capacitance selection circuit 170.
Later, it needs to amplify running to the second subtracted signal S2 in circuit-level 502 in aforementioned opamp 100 The second operation time period T2 in, timing adjustment and error correction circuit 306 (or other sequential control circuits) the controllable 13rd The first end of first capacitor 421 is coupled to the first input signal Vin_1 by switch 425, and the 14th switch 427 of synchronously control will The first end of second capacitor 423 is coupled to the first input signal Vin_1, and the 15th switch 429 of synchronously control is by first capacitor 421 second end is coupled to predetermined voltage Vcmi together with the second end of the second capacitor 423.In the second operation time period T2, when Sequence adjustment and error correction circuit 506 (or other sequential control circuits) can control sixteenmo to close 645 for third capacitor 641 First end is coupled to the output signal Vout of operational amplifier 100, and the 17th switch 647 of synchronously control is by the 4th capacitor 643 First end be coupled to predetermined voltage Vr2, and synchronously control eighteenmo closes 649 for the second end of third capacitor 641 and the 4th The second end of capacitor 643 is coupled to the second subtracter 546 together.At this point, timing adjustment and error correction circuit 306,506 or The controllable output switch 480 of other sequential control circuits exports the second subtracted signal S2 to the first gain stage 110, and controls input Switch 490 exports the second input signal Vin_2 to capacitance selection circuit 170.
In this way, which operational amplifier 100 only can subtract each other letter to first in circuit-level 302 in the first operation time period T1 Number S1 amplifies running, and can only put to the second subtracted signal S2 in circuit-level 502 in the second operation time period T2 Big running.
As long as timing adjustment and error correction circuit 306,506 or other sequential control circuits are suitably set aforementioned open Close 425,427,429,645,647,649,480, with 490 switching sequence, operational amplifier 100 just can in turn with pipeline system Other circuits in the different circuit-levels of analog-digital converter 500, which are arranged in pairs or groups, to be operated, so that different circuit-levels is able to share together One operational amplifier 100.
By preceding description it is found that the function block 420 in Fig. 6,640,324,326,544, the combination with 546, are equivalent to It is another embodiment of the front stage circuits 102 in earlier figures 1.
It is coupled to the selected capacitor of the second gain stage 120 in each operation time period, being precharged to has suitably Cross-pressure value.Therefore, the required charge or discharge time can substantially contract after selected capacitor is coupled to the second gain stage 120 It is short.In this way, just can effectively promote the response speed of operational amplifier 100, and then improve pipeline system Analog-digital Converter The overall operation efficiency or service speed of device 500.
In addition, using aforementioned by multiple candidate capacitor 131-135 and 151-155 grouping wheel current charge and provide in turn will quilt Be coupled to the mechanism of the feedback capacity of the second gain stage 120, can more shorten selected capacitor be coupled to the second gain stage 120 it The charge or discharge time needed for afterwards, therefore the response speed of operational amplifier 100 can be further speeded up, and further promote flowing water The overall operation efficiency or service speed of wire type analog-digital converter 500.
Aforementioned element connection relationship, embodiment, function mode and correlation in relation to the operational amplifier 100 in Fig. 1 The explanation such as advantage, is also suitable for the embodiment of Fig. 6.For brevity, not repeated description herein.
Due to other in the same the operational amplifier 100 alternately circuit-level 302 and 502 in channels different from adhering to separately Circuit element is arranged in pairs or groups running in turn, so circuit-level 302 and 502 need to only share the same operational amplifier 100 i.e. in running It can.In this way, the number that the operational amplifier of required setting in pipeline system analog-digital converter 500 will can be greatly decreased Amount, thus reduce the integrated circuit area of pipeline system analog-digital converter 500.
In implementation, operational amplifier 100 above-mentioned can also be applied in the framework of sample and hold.For example, Fig. 7 The depicted simplified functional block diagram of sample and hold 700 for one embodiment of the invention.
Sample and hold 700 includes a suitching type capacitance network 702 and operational amplifier above-mentioned 100, wherein Switching type capacitor network 702 is arranged to be sampled an input signal Vin and keeps operating, to generate a sampled signal, and By the sampled signal as the first signal N1 for wanting input operational amplifier 100.
In the present embodiment, switching type capacitor network 702 includes a sampling capacitor 710, one first sampling switch 720, one Second sampling switch 730 and a sequential control circuit 740.
First sampling switch 720 is coupled to a first end of sampling capacitor 710, is used for sampling capacitor 710 selectively It is coupled to input signal Vin or output signal Vout.
Second sampling switch 730 is coupled to a second end of sampling capacitor 710, is used for sampling capacitor 710 selectively It is coupled to an input terminal of a predetermined voltage Vcmi or the first gain stage 110.In implementation, it is fixed that predetermined voltage Vcmi can be one The common-mode voltage of voltage or switching type capacitor network 702.
In implementation, switch 720 and 730 above-mentioned can all be realized with the combination of multiple transistors, can also use multiple crystalline substances The arrange in pairs or groups combination of logic gate appropriate of body pipe is realized.
Sequential control circuit 740 is coupled to the first sampling switch 720 and the second sampling switch 730, and is arranged to control The switching sequence of one sampling switch 720 and the second sampling switch 730.
For example, sampling capacitor 710 is coupled to input signal when sequential control circuit 740 controls the first sampling switch 720 When Vin, sequential control circuit 740 can control the second sampling switch 730 and sampling capacitor 710 is coupled to predetermined voltage Vcmi.When When sampling capacitor 710 is coupled to output signal Vout by the first sampling switch 720 of control of sequential control circuit 740, timing control Circuit 740 can then control the input terminal that sampling capacitor 710 is coupled to the first gain stage 110 by the second sampling switch 730.
Operational amplifier 100 is coupled to switching type capacitor network 702, is arranged to export according to switching type capacitor network 702 The first signal N1 generate output signal Vout, and the input signal Vin according to switching type capacitor network 702 size switching it is more The coupling mode of a candidate's capacitor 131-135 and 151-155, so that multiple candidate capacitor 131-135 and 151-155 above-mentioned exist Only some candidate capacitor can be used to participate in the generation running of output signal Vout in the same time.
By preceding description it is found that switching type capacitor network 702 in Fig. 7, is the equal of the front stage circuits in earlier figures 1 102 another embodiment.
It is coupled to the selected capacitor of the second gain stage 120 every time, has been precharged to appropriate cross-pressure value.Cause This, the required charge or discharge time can substantially shorten after selected capacitor is coupled to the second gain stage 120.Such one Come, just can effectively promote the response speed of operational amplifier 100, and then improves the overall operation effect of sample and hold 700 Energy or service speed.
In addition, using aforementioned by multiple candidate capacitor 131-135 and 151-155 grouping wheel current charge and provide in turn will quilt Be coupled to the mechanism of the feedback capacity of the second gain stage 120, can more shorten selected capacitor be coupled to the second gain stage 120 it The charge or discharge time needed for afterwards, therefore the response speed of operational amplifier 100 can be further speeded up, and further promote sampling The overall operation efficiency or service speed of hold amplifier 700.
Aforementioned element connection relationship, embodiment, function mode and correlation in relation to the operational amplifier 100 in Fig. 1 The explanation such as advantage, is also suitable for the embodiment of Fig. 7.For brevity, not repeated description herein.
It note that the number of elements in previous embodiment is an exemplary embodiment, not limit to reality of the invention Border embodiment.For example, the also number of comparators in extendible capacitance selection circuit 170 in certain embodiments, so that selection Logic 240 can more precisely grasp the magnitude range of input signal Vin.For example, in certain embodiments also can be by capacitance selection electricity It is two that number of comparators in road 170, which is deleted, to reduce the circuit complexity of selection logic 240.
In addition, the response speed in certain pairs of operational amplifiers 100 requires in slightly lower embodiment, also can will before The second capacitance group stated and relevant switch omit, and only arrange in pairs or groups the with the Single Capacitance group comprising at least three candidate capacitors Two gain stages 120 are operated.
It in certain embodiments, also can be by the defeated of the first digital analog converter 324 in earlier figures 4 or Fig. 6 embodiment The 14th switch 427 is terminated to, out to provide predetermined voltage Vr1 above-mentioned.Under this framework, when the 13rd switch 425 is by The first end of one capacitor 421 is coupled to the output signal Vout of operational amplifier 100 and the 14th switch 427 is by the second capacitor When 423 first end is coupled to predetermined voltage Vr1, the coupling of the second end of the second end of first capacitor 421 and the second capacitor 423 Place will form the first subtracted signal S1 above-mentioned.In the case, when the first gain stage 110 needs to couple the first subtracted signal When S1, the second end of first capacitor 421 can be coupled to first together with the second end of the second capacitor 423 by the 15th switch 429 The input terminal of gain stage 110, and the first subtracter 326 is omitted.
It similarly, also can be by the output of the second digital analog converter 344 (or 544) in earlier figures 4 or Fig. 6 embodiment The 17th switch 447 (or 647) is terminated to, to provide predetermined voltage Vr2 above-mentioned.Under this framework, when sixteenmo closes 445 The first end of third capacitor 441 (or 641) is coupled to the output signal Vout and the 17th of operational amplifier 100 by (or 645) When the first end of 4th capacitor 443 (or 643) is coupled to predetermined voltage Vr2 by switch 447 (or 647), third capacitor 441 (or 641) the second subtracted signal S2 above-mentioned will be formed at the coupling of the second end of second end and the 4th capacitor 443 (or 643). In the case, when the first gain stage 110 needs to couple the second subtracted signal S2, eighteenmo closes 449 (or 649) can be by the The second end of three capacitors 441 (or 641) is coupled to the first gain stage 110 together with the second end of the 4th capacitor 443 (or 643) Input terminal, and the second subtracter 346 (or 546) is omitted.
In certain embodiments, the output switch 480 in earlier figures 4 and Fig. 6 can also be omitted with input switch 490.This When, it, can be by another circuit-level during operational amplifier 100 will amplify running to the signal of some circuit-level Digital analog converter in multiplication formula digital analog converter suspends running, receives mistake to avoid the first gain stage 110 Subtracted signal.
Some vocabulary is used in specification and claim to censure specific element, and technology people in the art Member may call same element with different nouns.This specification and claims not with the difference of title as The mode of element is distinguished, but with the difference of element functionally as the benchmark of differentiation.In specification and claim Mentioned "comprising" is open term, should be construed to " including but not limited to ".In addition, " coupling " word includes herein Any direct and indirect connection means.Therefore, if it is described herein that first element is coupled to second element, then first element is represented It can be attached directly to second element by being electrically connected or being wirelessly transferred, and the signals connection type such as optical delivery, or passed through Electrical property or signal are connected to second element indirectly for other elements or connection means.
The describing mode of used "and/or" in the description includes cited one of project or multiple items Purpose any combination.In addition, unless specified in the instructions, otherwise the term of any singular lattice all includes multiple grid simultaneously Meaning.
" voltage signal " in specification and claim, can be used voltage form on the implementation or current forms are come in fact It is existing." current signal " in specification and claim, also voltage available form or current forms are realized on the implementation.
The foregoing is merely a prefered embodiment of the invention, all equivalence changes and modification made according to the claims in the present invention, all It should belong to the scope of the present invention.

Claims (10)

1. a kind of operational amplifier (100), includes:
One first gain stage (110) is arranged to transmit according to a front stage circuits (102) for the operational amplifier (100) 1 One signal generates a second signal；
One second gain stage (120) is coupled to first gain stage (110), is arranged to generate an output according to the second signal Signal；
One first candidate capacitor (131)；
One second candidate capacitor (133)；
One third candidate capacitor (135)；
One first switch (141) is coupled to a first end of the first candidate capacitor (131), is used for the first candidate capacitor (131) it is selectively coupled to an input terminal of one first predetermined voltage or second gain stage (120)；
One second switch (142) is coupled to a second end of the first candidate capacitor (131), is used for the first candidate capacitor (131) it is selectively coupled to an output end of a first voltage or second gain stage (120)；
One third switchs (143), is coupled to a first end of the second candidate capacitor (133), is used for the second candidate capacitor (133) it is selectively coupled to the input terminal of first predetermined voltage or second gain stage (120)；
One the 4th switch (144) is coupled to a second end of the second candidate capacitor (133), is used for the second candidate capacitor (133) it is selectively coupled to the output end of a second voltage or second gain stage (120)；
One the 5th switch (145), is coupled to a first end of third candidate capacitor (135), is used for third candidate's capacitor (135) it is selectively coupled to the input terminal of first predetermined voltage or second gain stage (120)；
One the 6th switch (146), is coupled to a second end of third candidate capacitor (135), is used for third candidate's capacitor (135) it is selectively coupled to the output end of a tertiary voltage or second gain stage (120)；And
One capacitance selection circuit (170) is coupled to the front stage circuits (102) and first to the 6th switch (141-146), if It is set to and controls first to the 6th switch (141-146) according to the size of an input signal of the front stage circuits (102), so that This first to third candidate capacitor (131-135) in the same time only some candidate capacitor can be coupled to this second Gain stage (120).
2. operational amplifier (100) as described in claim 1, wherein the front stage circuits (102) include one or more suitching types Capacitance network, and second increasing is coupled in first part candidate's capacitor into third candidate capacitor (131-135) Before beneficial grade (120), this first can be charged to different cross-pressure values to third candidate capacitor (131-135) respectively.
3. operational amplifier (100) as claimed in claim 2, wherein the front stage circuits (102) include:
One first switching type capacitor network (420) is arranged to be sampled one first input signal and keeps operating；
One first digital analog converter (324) is arranged to generate one first analog signal corresponding with first input signal, And the output of the first switching type capacitor network (420) and both first digital analog converters (324) forms one first phase Cut signal；
One second switching type capacitor network (440；640), it is arranged to be sampled one second input signal and keeps operating；With And
One second digital analog converter (344；544), it is arranged to generate one second simulation corresponding with second input signal Signal, and the second switching type capacitor network (440；640) with second digital analog converter (344；544) output of the two Form one second subtracted signal；
Wherein, when first gain stage (110) utilizes first subtracted signal as first signal, the capacitance selection circuit (170) input signal can be done using first input signal, and when first gain stage (110) utilizes second subtracted signal When as first signal, which can do the input signal using second input signal.
4. operational amplifier (100) as claimed in claim 2, wherein the front stage circuits (102) include:
One sampling capacitor (710)；
One first sampling switch (720), is coupled to a first end of the sampling capacitor (710), is used for the sampling capacitor (710) It is selectively coupled to the input signal or the output signal；
One second sampling switch (730), is coupled to a second end of the sampling capacitor (710), is used for the sampling capacitor (710) It is selectively coupled to an input terminal of one second predetermined voltage or first gain stage (110)；And
One sequential control circuit (740) is coupled to first sampling switch (720) and second sampling switch (730), is arranged to Control the switching sequence of first sampling switch (720) and second sampling switch (730)；
Wherein, when the sampling capacitor (710) is coupled to the input signal by first sampling switch (720), second sampling The sampling capacitor (710) can be coupled to second predetermined voltage by switch (730), and when first sampling switch (720) should When sampling capacitor (710) is coupled to the output signal, which can be coupled to the sampling capacitor (710) The input terminal of first gain stage (110).
5. the operational amplifier (100) as described in any in claim 2 to 4, wherein the capacitance selection circuit (170) includes:
Multiple comparators (210,220) are arranged to for the input signal being compared with multiple corresponding reference signals respectively；And
One selection logic (240), be coupled to multiple comparator (210,220), be arranged to according to multiple comparator (210, 220) comparison result, select this first to third candidate capacitor (131-135) a portion as selected capacitor, and The multiple control signal for controlling first to the 6th switch (141-146) is generated, which is coupled to this Second gain stage (120).
6. a kind of operational amplifier (100), includes:
One first gain stage (110) is arranged to transmit according to a front stage circuits (102) for the operational amplifier (100) 1 One signal generates a second signal；
One second gain stage (120) is coupled to first gain stage (110), is arranged to generate an output according to the second signal Signal；
One first candidate capacitor (131)；
One second candidate capacitor (133)；
One third candidate capacitor (135)；
One first switch (141) is coupled to a first end of the first candidate capacitor (131), is used for the first candidate capacitor (131) it is selectively coupled to an input terminal of one first predetermined voltage or second gain stage (120)；
One second switch (142) is coupled to a second end of the first candidate capacitor (131), is used for the first candidate capacitor (131) it is selectively coupled to an output end of a first voltage or second gain stage (120)；
One third switchs (143), is coupled to a first end of the second candidate capacitor (133), is used for the second candidate capacitor (133) it is selectively coupled to the input terminal of first predetermined voltage or second gain stage (120)；
One the 4th switch (144) is coupled to a second end of the second candidate capacitor (133), is used for the second candidate capacitor (133) it is selectively coupled to the output end of a second voltage or second gain stage (120)；
One the 5th switch (145), is coupled to a first end of third candidate capacitor (135), is used for third candidate's capacitor (135) it is selectively coupled to the input terminal of first predetermined voltage or second gain stage (120)；
One the 6th switch (146), is coupled to a second end of third candidate capacitor (135), is used for third candidate's capacitor (135) it is selectively coupled to the output end of a tertiary voltage or second gain stage (120)；
One the 4th candidate capacitor (151)；
One the 5th candidate capacitor (153)；
One the 6th candidate capacitor (155)；
One the 7th switch (161) is coupled to a first end of the 4th candidate capacitor (151), is used for the 4th candidate capacitor (151) it is selectively coupled to the input terminal of first predetermined voltage or second gain stage (120)；
One the 8th switch (162) is coupled to a second end of the 4th candidate capacitor (151), is used for the 4th candidate capacitor (151) it is selectively coupled to the output end of the first voltage or second gain stage (120)；
One the 9th switch (163) is coupled to a first end of the 5th candidate capacitor (153), is used for the 5th candidate capacitor (153) it is selectively coupled to the input terminal of first predetermined voltage or second gain stage (120)；
The tenth switch (164) is coupled to a second end of the 5th candidate capacitor (153), is used for the 5th candidate capacitor (153) it is selectively coupled to the output end of the second voltage or second gain stage (120)；
The 11st switch (165) is coupled to a first end of the 6th candidate capacitor (155), for candidate electric by the 6th Hold the input terminal that (155) are selectively coupled to first predetermined voltage or second gain stage (120)；
The 12nd switch (166) is coupled to a second end of the 6th candidate capacitor (155), for candidate electric by the 6th Hold the output end that (155) are selectively coupled to the tertiary voltage or second gain stage (120)；And
One capacitance selection circuit (170), be coupled to the front stage circuits (102) and this first to the 12nd switch (141-146, 161-166), it is arranged to control first to the 12nd switch according to the size of an input signal of the front stage circuits (102) (141-146,161-166), so that first to the 6th candidate capacitor (131-135,151-155) only has in the same time A part of candidate's capacitor can be coupled to second gain stage (120)；
Wherein, which is divided into a first capacitor group (131-135) and one Second capacitance group (151-155), and when part candidate's capacitor in the first capacitor group (131-135) is coupled to second increasing When beneficial grade (120), all candidate capacitors in second capacitance group (151-155) can be charged to respectively with different cross-pressures Value.
7. operational amplifier (100) as claimed in claim 6, wherein the front stage circuits (102) include one or more suitching types Capacitance network, and the capacitance selection circuit (170) is also configured to the first capacitor group (131- in one first operation time period 135) the candidate capacitor in part in is coupled to second gain stage (120), and one second behaviour after first operation time period Make in the period, changes and the candidate capacitor in part in second capacitance group (151-155) is coupled to second gain stage (120).
8. operational amplifier (100) as claimed in claim 7, wherein the front stage circuits (102) include:
One first switching type capacitor network (420) is arranged to be sampled one first input signal and keeps operating；
One first digital analog converter (324) is arranged to generate one first analog signal corresponding with first input signal, And the output of the first switching type capacitor network (420) and both first digital analog converters (324) forms one first phase Cut signal；
One second switching type capacitor network (440；640), it is arranged to be sampled one second input signal and keeps operating；With And
One second digital analog converter (344；544), it is arranged to generate one second simulation corresponding with second input signal Signal, and the second switching type capacitor network (440；640) with second digital analog converter (344；544) output of the two Form one second subtracted signal；
Wherein, when first gain stage (110) utilizes first subtracted signal as first signal, the capacitance selection circuit (170) input signal can be done using first input signal, and when first gain stage (110) utilizes second subtracted signal When as first signal, which can do the input signal using second input signal.
9. operational amplifier (100) as claimed in claim 7, wherein the front stage circuits (102) include:
One sampling capacitor (710)；
One first sampling switch (720), is coupled to a first end of the sampling capacitor (710), is used for the sampling capacitor (710) It is selectively coupled to the input signal or the output signal；
One second sampling switch (730), is coupled to a second end of the sampling capacitor (710), is used for the sampling capacitor (710) It is selectively coupled to an input terminal of one second predetermined voltage or first gain stage (110)；And
One sequential control circuit (740) is coupled to first sampling switch (720) and second sampling switch (730), is arranged to Control the switching sequence of first sampling switch (720) and second sampling switch (730)；
Wherein, when the sampling capacitor (710) is coupled to the input signal by first sampling switch (720), second sampling The sampling capacitor (710) can be coupled to second predetermined voltage by switch (730), and when first sampling switch (720) should When sampling capacitor (710) is coupled to the output signal, which can be coupled to the sampling capacitor (710) The input terminal of first gain stage (110).
10. the operational amplifier (100) as described in any in claim 7 to 9, wherein the capacitance selection circuit (170) packet Contain:
Multiple comparators (210,220) are arranged to for the input signal being compared with multiple corresponding reference signals respectively；And
One selection logic (240), is coupled to multiple comparator (210,220), is arranged to the foundation in first operation time period The comparison result of multiple comparator (210,220) selects this first one of to third candidate capacitor (131-135) As selected capacitor, and the multiple control signal for controlling first to the 6th switch (141-146) is generated, by the choosing Determine capacitor and is coupled to second gain stage (120).
CN201711056837.8A 2017-10-27 2017-10-27 Operational amplifier capable of flexibly switching candidate capacitor Active CN109728814B (en)

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CN101487863A (en) * 2008-01-15 2009-07-22 财团法人交大思源基金会 Apparatus for accurately measuring open circuit gain of amplifier by utilizing digital excitation signal
CN101931413A (en) * 2009-06-25 2010-12-29 联发科技股份有限公司 Pipeline analog-to-digital converter and multiplying digital-to-analog converter
CN104426374A (en) * 2013-09-06 2015-03-18 立锜科技股份有限公司 Power conversion device and multiplication and division circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070035432A1 (en) * 2004-09-17 2007-02-15 Kush Gulati Analog-to-digital converter without track-and-hold
CN101132177A (en) * 2006-08-24 2008-02-27 凌阳科技股份有限公司 Programmable gain amplifier
CN101487863A (en) * 2008-01-15 2009-07-22 财团法人交大思源基金会 Apparatus for accurately measuring open circuit gain of amplifier by utilizing digital excitation signal
CN101931413A (en) * 2009-06-25 2010-12-29 联发科技股份有限公司 Pipeline analog-to-digital converter and multiplying digital-to-analog converter
CN104426374A (en) * 2013-09-06 2015-03-18 立锜科技股份有限公司 Power conversion device and multiplication and division circuit

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