CN109728808A - Mitigate the method and relevant signal system of injection pulling effect - Google Patents
Mitigate the method and relevant signal system of injection pulling effect Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C3/00—Angle modulation
- H03C3/02—Details
- H03C3/09—Modifications of modulator for regulating the mean frequency
- H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/50—All digital phase-locked loop
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Abstract
The present invention provides the method and relevant signal system of a kind of injection pulling effect that can reduce oscillator, which generates output clock under control of the control signal.This method comprises: being filtered by loop filter to deviation signal, to form filtering signal；By self injection locking (SIL) controller formation auxiliary signal, the auxiliary signal tracing deviation signal or track reference clock and due to the phase difference between the output signal of the output clock；And by forming the control signal to the filtering signal and auxiliary signal summation.
Description
Technical field
The present invention relates to the method for mitigating injection pulling effect (injection-pulling effect) and relevant letters
Number system, and method and relevant signal system more particularly, to the injection pulling effect for reducing oscillator.
Background technique
Signal system with oscillator be for modern electronic equipment it is essential, the oscillator for generate when
Clock and/or oscillator signal.For example, electrical requirements wireless communication ability needs the signal system with oscillator to realize radio frequency
(radio frequency, RF) transmitter, receiver and/or transceiver.
Referring to FIG. 1, Fig. 1 shows conventional signal system 100, such as the RF transmitter of direct converting structure.System
100 include phase detecting circuit (phase detection circuitry) 110, loop filter (loop filter) 140,
Oscillator 160, quadrature modulator (quadrature modulator) 165 and power amplifier (power amplifier, PA)
174.Oscillator 160 is vibrated under the control of control signal sf1, with generation (generate) or forms (form) RF clock
CKv1.Quadrature modulator 165 is modulated base-band data signal I_data and Q_data using clock CKv1, to form RF letter
Number ss1, and, power amplifier 174 amplifies signal ss1, to generate amplified RF signal so1.In order to generate use
To control the signal sf1 of oscillator 160, phase detecting circuit 110 detects the phase between reference clock CKref and clock CKv1
Difference, to form signal se1, and, loop filter 140 is filtered signal se1, to generate signal sf1.As shown in Figure 1,
Loop filter 140 is the low-pass filter with the frequency response of bandwidth f0.
The noise of influence system 100 includes: reference noise relevant to phase detecting circuit 110, by its intrinsic jitter
Can the determining generator noise of resonator design, and injection noise, the injection noise with due to (resulting
From the equivalent phase for) injecting pulling effect interferes correlation.For example, the non-linear of amplifier 174 will cause unexpected harmonic wave,
And the frequency that the harmonic wave will lead to clock CKv1 is pulled away from expected frequence, and/or the frequency spectrum of clock CKv1 is caused to deviate expected frequency
Spectrum.Injection pulling effect be for direct conversion signal system it is vital because the frequency of signal ss1 and so1 and when
The frequency of clock CKv1 is essentially identical (or very close).The bandwidth f0 of loop filter 140 is generally designed to for the reference
Compromise between noise and the generator noise, but such bandwidth f0 will be influenced by sizable injection noise.
There are several prior arts that can mitigate injection pulling effect.A kind of prior art attempts by improving amplifier 174
Isolation between oscillator 160 mitigates injection pulling effect, but is influenced by high hardware cost and layout complexity.Separately
A kind of prior art attempts to mitigate injection pulling effect by the bandwidth f0 of extension loop filter 140, but can be to original
Circuit layout strategy adversely affects, it means that how designer cannot be concerned only with according to reference noise and generator noise
Realize optimal inhibition.Another prior art attempts to mitigate injection pulling effect by application Adaptive interference cancellation, still
It must be required to be influenced by complicated digital calibration and stringent compensation precision.
Summary of the invention
In view of this, one of the objects of the present invention is to provide a kind of methods and correlation that can reduce injection pulling effect
Signal system, to solve the above problems.
In a first aspect, the present invention provides a kind of method of injection pulling effect for mitigating oscillator, which is being controlled
Output clock is generated under the control of signal processed, and, this method comprises: deviation signal is filtered by loop filter,
To form filtering signal；Auxiliary signal is formed by self injecting locking (SIL) controller, which tracks deviation letter
Phase number between (transient change of such as deviation signal) or track reference clock and the output signal due to the output clock
Potential difference (transient change of such as phase difference)；And by forming the control to the filtering signal and auxiliary signal summation
Signal.
Second aspect, the present invention provides a kind of signal system for mitigating injection pulling effect, which includes vibration
Swing device, loop filter, SIL controller and the first summation unit.Oscillator is defeated for generating under control of the control signal
Clock out；Loop filter is for being filtered deviation signal, to form filtering signal；SIL controller is used to form auxiliary
Signal, the auxiliary signal track reference clock (transient change of such as deviation signal) or track reference clock with it is defeated due to this
Phase difference between the output signal of clock (transient change of such as phase difference) out；And first summation unit be coupled in this
Loop filter, between the SIL controller and the oscillator, for by summing the filtering signal and the auxiliary signal come shape
At the control signal.
The third aspect, the present invention provides a kind of signal system for mitigating injection pulling effect, which includes vibration
Swing device, loop filter, SIL controller and the first summation unit.Oscillator is defeated for generating under control of the control signal
Clock out；Loop filter is for being filtered deviation signal, to form filtering signal；SIL controller is used for by this
It exports clock and executes frequency identification to form auxiliary signal；And first summation unit be coupled in the loop filter, the SIL
Between controller and the oscillator, for by forming the control signal to the filtering signal and auxiliary signal summation.
Those skilled in the art, can be beyond all doubt after the following detailed descriptions for reading preferred embodiment shown in attached drawing
Ground understands object of the present invention and other purposes.Detailed description will provide in the following embodiments with reference to attached drawing.
Detailed description of the invention
By reading subsequent detailed description and referring to attached drawing the examples given, the present invention can be more fully understood.
Fig. 1 shows conventional signal system.
Fig. 2 to Fig. 5 shows signal system according to embodiments of the present invention.
Fig. 6 shows self a kind of injection locking (SIL) controller according to embodiments of the present invention.
Fig. 7 shows the operation of system shown in Fig. 2 to Fig. 5.
Fig. 8 shows a kind of signal system according to embodiments of the present invention.
In the following detailed description, for illustrative purposes, numerous specific details are set forth, so as to those skilled in the art
Member can thoroughly understand the embodiment of the present invention.It will be apparent, however, that can there is no the case where these details
The one or more embodiments of lower implementation, different embodiments can combine according to demand, and should not be only limitted to listed by attached drawing
For embodiment.
Specific embodiment
It is depicted below as the preferred embodiment that the present invention is implemented, is only used to enumerate and illustrates technical characteristic of the invention, and
The scope being not intended to limit the invention.Use some vocabulary specific to censure in specification and claims in the whole text
Element, one of ordinary skill in the art should be appreciated that manufacturer may call same element using different titles.Cause
This, in a manner of present specification and claims are not using the difference of title as distinct elements, but functionally with element
Difference make diacritical benchmark.Term used in the present invention " element ", " system " and " device " can be and computer phase
The entity of pass, wherein the computer can be the combination of hardware, software or hardware and software.It is described below and claim
Term "comprising" and " comprising " of the book mentioned in are open language, therefore should be construed to " including, but are not limited to ... "
The meaning.In addition, term " coupling " means directly or indirectly to be electrically connected.Therefore, if it is described herein that a device is coupled to separately
One device, then another device can be directly electrically connected in by representing the device, or indirect through other devices or connection means
Ground is electrically connected to another device.
Wherein, unless otherwise directed, corresponding numbers and symbols is usually directed to corresponding portion in the different attached drawings of each attached drawing
Point.The attached drawing drawn clearly illustrates the relevant portion of embodiment and is not drawn necessarily to scale.
Term " basic " used herein " substantially " refers to that within the acceptable range, those skilled in the art are able to solve
Technical problem to be solved basically reaches technical effect to be achieved.For example, it " is substantially equal to " and refers to and do not influencing
As a result when correctness, the acceptable mode for having certain error with " being equal to " of technical staff.
Referring to FIG. 2, Fig. 2 shows signal system 200 according to embodiments of the present invention.Signal system 200 includes accumulator
(accumulator) 210, measuring circuit (measuring circuit) 220 is (for example, time-to-digital converter (time-
To-digital converter, TDC)), summation unit (sum block) 230, loop filter 240 and oscillator 260；For
Mitigate injection pulling effect, signal system 200 further includes self injection locking (self-injection locked, SIL) control
Device 250 processed and another summation unit 255.Oscillator 260 is vibrated under the control of control signal sc2, to generate output
Clock CKv2, thus, the frequency of clock CKv2 changes with the variation of control signal sc2.Accumulator 210 is coupled to or receives frequency
Rate control word (frequency command word)/frequency control command FCW and reference clock CKref, in reference
Cumulative frequency control word FCW in each period of clock CKref, to form reference signal sr2.Measuring circuit 220 is coupled to oscillation
Device 260, for measuring reference clock CKref and exporting the phase difference between clock CKv2, to form distinguishing signal
(distinction signal)sd2.Summation unit 230 is coupled in measuring circuit 220, accumulator 210 and loop filter 240
Between, for forming deviation signal according to the difference (such as phase difference) between reference signal sr2 and distinguishing signal sd2
(deviation signal)se2.Loop filter 240 is filtered deviation signal se2, to form filtering signal sf2.When
When signal system 200 reaches stable locking phase (phase lock), the frequency fv of output clock CKv2 is substantially equal to frequency control
The product of the frequency fr of word FCW and reference clock CKref, i.e. fv=FCW*fr.For example, reference clock CKref is the amount of MHz
Grade, and export clock CKv2 and can be the magnitude of GHz.Loop filter 240 can be low-pass filter.
SIL controller 250 has input port i2 and output port p2；Input port i2 is coupled to summation unit 230, and
Output port p2 is coupled to summation unit 255.In order to mitigate injection pulling effect, SIL controller 250 is used to form auxiliary signal
Sa2, wherein the transient change (instantaneous varying) of auxiliary signal sa2 tracking (track) deviation signal se2.
Summation unit 255 is coupled in loop filter 240, between SIL controller 250 and oscillator 260, for by filtering signal
Sf2 and auxiliary signal sa2 summation controls signal sc2 to be formed.Due to distinguishing signal sd2 be by output clock CKv2 and reference when
What the phase difference between clock CKref was formed, therefore, distinguishing signal sd2 (and deviation signal se2 comprising distinguishing signal sd2)
Transient change be able to reflect injection pulling effect to output clock CKv2 transient effects.
SIL controller 250 according to the present invention is by enabled auxiliary signal sa2 and controls signal sc2 (wherein, control
Signal sc2 is by obtaining to filtering signal sf2 and auxiliary signal sa2 summation) continue (keep) tracing deviation signal se2
Transient change, thus, oscillator 260 can offset rapidly the real-time of injection pulling effect under the control of control signal sc2
(immediate) it influences, therefore, the reduction (efficiently reducing injection pulling effect) of injection pulling effect can be improved.?
In some embodiments, SIL controller 250 can also be enabled according to specific design choice and exports auxiliary signal sa2, for example,
When the transient change amount of deviation signal se2 is greater than predetermined threshold, enables SIL controller 250 and export auxiliary signal sa2, with fast
Speed correction se2, to reduce deterioration of the injection pulling effect to system effectiveness.In general, phaselocked loop (Phase Locking
Loop, PLL) in loop filter include two kinds of lock states, for example, slightly locking (coarse locking) state, can
A mode filter (Type-I filter) is shown as, with lesser settling time (settling time)；Essence locking
(fine locking) state can behave as two mode filters (Type-II filter), with lesser stable state
Error, two kinds of lock states are respectively provided with respective advantage.However, when loop filter is switched to smart locking from thick lock state
When state, filtering signal sf2 can not reflect the transient change in deviation signal 230, if at this time PLL by injection pulling effect,
The ability that self injection locking means provided by the invention will can provide signal system and quickly correct se2, imitates system with reducing
The deterioration of energy.That is, in some embodiments of the invention, auxiliary signal sa2 and deviation signal se2 are deviation signals
The se2 circuit revise signal after type I filter and type II filter respectively, to have better performance.
In one embodiment, accumulator 210, measuring circuit 220, loop filter 240, SIL controller 250 and summation
Unit 230,255 can be the digital circuit in the numeric field driven by reference clock CKref, and, oscillator 260 can
To be numerically-controlled oscillator.For example, loop filter 240 can be wave digital lowpass filter, and, measuring circuit 220 can
To be time-to-digital converter (TDC)；Measuring circuit 220 will export clock in each period of reference clock CKref
The effective edge of CKv2 is converted to digital value along time difference of the effective edge of (for example, rising edge) and reference clock CKref between,
To form the sample sd2 [n] of distinguishing signal sd2.In n-th of period, when measurement obtains sample sd2 [n] and by summation list
When member 230 forms sample se2 [n] of deviation signal se2, SIL controller 250 is by the real-time sample of enabled auxiliary signal sa2
(immediate sample) sa2 [n] tracks the value of sample se2 [n], thus, control the real-time sample sc2 [n] of signal sc2
By the instantaneous value of reflected sample se2 [n].It should be noted that due to the digital filtering of loop filter 240, filtering signal sf2
Real-time sample sf2 [n] on n-th of period will not reflected sample se2 [n] instantaneous value；The instantaneous value of sample se2 [n] will
It is reflected by filtering signal sf2 in subsequent (n+1) or subsequent samples sf2 [n+1] on (n+2) a period or sf [n+2].
In one embodiment, SIL controller 250 is according to the time delay (latency) of measuring circuit 220 and SIL controller 250
Adjust the value of sample sa2 [n], and so that sample sa2 [n] substantially with reference clock CKref and output clock CKv2
Between phase difference be in 180 degree reverse phase (out of phase), thus, pass through the enabled oscillation of the obtained control signal sc2 of summation
Device 260 is vibrated with the trend opposite with injection pulling effect, for example, when injection pulling effect makes output clock CKv2 slow down
It is vibrated faster when (slow down).Since measuring circuit 220 is digital circuit, it can estimate well in design level
The time delay of meter and compensation measuring circuit 220.
SIL controller 250 can the SIL controller 650 as shown in Fig. 6 realize.As shown in fig. 6, SIL controller 650
The data conversion between input port i6 and output port p6 is associated in input port i6 and output port p6, and including grade
Device (data converter) 652 and internal amplifier (internal amplifier) 654.Data converter 652 is from input
Port i6 receiving phase difference signal spd6, and phase signal spd6 is converted into frequency difference signal sfd6.For example, phase
Difference signal spd6 and frequency difference signal sfd6 has different dynamic ranges, data format, coding and/or unit, and, data
Converter 652 executes Different Dynamic range, data format, the conversion between coding and/or unit.In one embodiment, it vibrates
Device 260 can be numerically-controlled oscillator, receive the digital controlled signal sc2 of frequency control format；In order to pass through this implementation
The SIL controller 650 of example realizes SIL controller 250, and the data converter 652 in SIL controller 650 can be by phase difference
Signal spd6 is converted to the frequency difference signal sfd6 of the frequency control format.In one embodiment, oscillator 260 can be reception
The voltage-controlled oscillator of voltage control signal sc2；In order to which SIL controller 650 through this embodiment realizes SIL controller
Phase signal spd6 can be converted to the difference on the frequency letter of voltage format by the data converter 652 in 250, SIL controllers 650
Number sfd6.
In SIL controller 650, amplifier 654 amplifies frequency difference signal sfd6, with the shape at output port p6
At signal sa6.Amplifier 654 may include amplifier (or amplifier unit) 656a and amplifier (or amplifier unit)
656b, amplifier 656a be used for using oscillator tuning sensitivity (oscillator tuning sensitivity) Kdco into
Row amplification, amplifier 656b using SIL loop gain Gsil for being amplified, wherein oscillator tuning sensitivity Kdco is
Constant relevant to oscillator, and SIL loop gain Gsil is programmable (variable) to obtain flexibility.In order to pass through figure
SIL controller 650 in 6 realizes that the SIL controller 250 in Fig. 2, port i2 and p2 can be realized by port i6 and p6 respectively,
Therefore the deviation signal se2 (Fig. 2) at the i2 of port is received as the phase signal spd6 (Fig. 6) at the i6 of port, and port
Signal sa6 at p6 is exported as the auxiliary signal sa2 (Fig. 2) at the p2 of port.
Referring to FIG. 3, Fig. 3 shows signal system 300 according to embodiments of the present invention.System 300 includes accumulator 310,
Measuring circuit 320, summation unit 330, loop filter 340, oscillator 360, quadrature modulator 365 and main amplifier 370；For
Mitigate injection pulling effect, system 300 further includes SIL controller 350 and measuring circuit 380 and another summation unit 355.
Oscillator 360 generates output clock CKv3 under the control of control signal sc3.Quadrature modulator 365 is coupled to oscillator 360,
For executing orthogonal modulation using output clock CKv3, to form modulated signal sm3.Main amplifier 370 is coupled to orthogonal modulation
Device 365, for being amplified to modulated signal sm3, to form output signal so3.Main amplifier 370 may include programmable increasing
Beneficial amplifier (programmable-gain amplifier, PGA) 372 and power amplifier (PA) 374.
Accumulator 310 is coupled to or receives frequency control word FCW and reference clock CKref, in reference clock CKref
Each period in cumulative frequency control word FCW, to form reference signal sr3.Measuring circuit 320 is coupled to oscillator 360, uses
In measurement reference clock CKref and the phase difference between clock CKv3 is exported, to form distinguishing signal sd3.330 coupling of summation unit
It connects between measuring circuit 320, accumulator 310 and loop filter 340, for according to reference signal sr3 and distinguishing signal sd3
Between difference form deviation signal se3.Loop filter 340 is for being filtered deviation signal se3, to form filtering
Signal sf3.Measuring circuit 380 is coupled between main amplifier 370 and SIL controller 350, for measuring reference clock CKref
Phase difference between output signal so3, to form distinguishing signal sdd3.
SIL controller 350 has input port i3 and output port p3, and input port i3 is coupled to measuring circuit 380, defeated
Exit port p3 is coupled to summation unit 355.In order to mitigate injection pulling effect, SIL controller 350 forms auxiliary signal sa3, should
Transient change of the auxiliary signal sa3 to track distinguishing signal sdd3.Summation unit 355 is coupled in loop filter 340, SIL
Between controller 350 and oscillator 360, for by forming control signal to filtering signal sf3 and auxiliary signal sa3 summation
sc3.Since distinguishing signal sdd3 is formed by the phase difference between reference clock CKref and output signal so3, area
The transient change of level signal sdd3 (and auxiliary signal sa3) is able to reflect injection pulling effect to the instantaneous of output signal so3
It influences.SIL controller 350 will make auxiliary signal sa3 and control signal sc3 persistently track the transient change of distinguishing signal sdd3,
To which oscillator 360 can offset rapidly the Real Time Effect of injection pulling effect under the control of control signal sc3, and therefore
Mitigate injection pulling effect.
In one embodiment, accumulator 310, measuring circuit 320,380, loop filter 340, SIL controller 350 and
Summation unit 330,355 can realize by operating the digital circuit in the numeric field of reference clock CKref driving, and,
Oscillator 360 can be numerically-controlled oscillator.For example, each of measuring circuit 320 and 380 can be the time to number
Converter (TDC)；In each period of reference clock CKref, measuring circuit 320 by export clock CKv3 effective edge edge and
Time difference of the effective edge of reference clock CKref between is converted to digital value, to form the sample sd3 of distinguishing signal sd3
[n]；On the other hand, measuring circuit 380 is by the effective edge of output signal so3 along between the effective edge of reference clock CKref edge
Time difference be converted to digital value, to form the sample sdd3 [n] of distinguishing signal sdd3.
In n-th of period, when measurement obtains sample sd3 [n] and sdd3 [n] and forms deviation letter by summation unit 330
When sample se3 [n] of number se3, SIL controller 350 enables real-time sample sa3 [n] the tracking sample sdd3 of auxiliary signal sa3
The value of [n], therefore, the real-time sample sc3 [n] of the control signal sc3 after summation is by the instantaneous value of reflected sample sdd3 [n].?
In one embodiment, SIL controller 350 makes sample sa3 [n] substantially between reference clock CKref and output signal so3
Phase difference is in 180 degree reverse phase (in other words, the phase difference between reference clock CKref and output signal so3 and sample sa3 [n] base
Originally it is 180 degree reverse phase), therefore the control signal sc3 that summation obtains makes oscillator 360 offset the shadow for injecting pulling effect
It rings.
Similar to the SIL controller 250 in Fig. 2, the SIL controller 350 in Fig. 3 can the control of the SIL as shown in Fig. 6
Device 650 realizes that port i3 and p3 are realized by port i6 and p6 respectively, therefore distinguishing signal sdd3 (Fig. 3) conduct at the i3 of port
Phase signal spd6 (Fig. 6) at the i6 of port is received, and the signal sa6 at output port p6 is as the auxiliary at the p3 of port
Signal sa3 (Fig. 3) is exported.
Signal system 200 or 300 in Fig. 2 or Fig. 3 can be applied to various transmitters and realize.For example, by by frequency control
Word FCW processed is set as changing based on baseband signal (not shown), and signal system 200 or 300 can be implemented as direct frequency modulated
(direct frequency modulation, DFM) or transmitter is directly converted, there is the injection pulling effect mitigated.This
Outside, present invention could apply to the signal systems of other modulation, such as polarization modulation.Referring to FIG. 4, Fig. 4 is real according to the present invention
It applies and is illustrated signal system 400.
As shown in figure 4, system 400 includes accumulator 410, measuring circuit 420, summation unit 403,430, loop filter
440, oscillator 460, frequency divider (frequency divider, referred to as LO DIV in figure) 463, frequency mixer (mixer) 465
With main amplifier 470；In order to mitigate injection pulling effect, system 400 can also include SIL controller 450 and summation unit
455.Oscillator 460 generates output clock CKv4 under the control of control signal sc4.Frequency divider 463 is coupled to oscillator 460,
For being divided to output clock CKv4, to form local oscillated signal LO4.Frequency mixer 465 is coupled to the second source signal
(source signal) sAM and frequency divider 463, it is mixed to be formed for mixing local oscillated signal LO4 and the second source signal sAM
Frequency signal sm4.Main amplifier 470 is coupled to frequency mixer 465, for amplifying to mixed frequency signal sm4, to form output signal
so4.Main amplifier 470 may include programmable gain amplifier (PGA) 472 and power amplifier (PA) 474.
Summation unit 403 sums to the first source signal sPM and frequency control word FCW, to form the word (summed that sums
word)sw4.Accumulator 410 is coupled to summation unit 403 and reference clock CKref, in each of reference clock CKref
Add up summation word sw4 in period, to form reference signal sr4.Measuring circuit 420 is coupled to oscillator 360, for measuring reference
Phase difference between clock CKref and output clock CKv4, to form distinguishing signal sd4.Summation unit 430 is coupled in measurement electricity
Road 420, between accumulator 410 and loop filter 440, for by reference to the difference between signal sr4 and distinguishing signal sd4
To form deviation signal se4.Loop filter 440 is filtered deviation signal se4, to form filtering signal sf4.
SIL controller 450 has input port i4 and output port p4, and input port i4 is coupled to summation unit 430, defeated
Exit port p4 is coupled to summation unit 455.In order to mitigate injection pulling effect, SIL controller 450 forms auxiliary signal sa4,
In, the transient change of auxiliary signal sa4 tracing deviation signal se4.Summation unit 455 is coupled in loop filter 440, SIL control
Between device 450 and oscillator 460 processed, for by summing to the first source signal sPM, filtering signal sf4 and auxiliary signal sa4
To form control signal sc4.Since distinguishing signal sd4 is by the phase difference between reference clock CKref and output clock CKv4
It is formed, therefore, the transient change of distinguishing signal sd4 (and deviation signal se4) is able to reflect injection pulling effect to output
The transient effects of clock CKv4.SIL controller 450 will be so that signal sa4 and control signal sc4 persistently track distinguishing signal
The transient change of sd4, therefore oscillator 460 can offset rapidly the reality of injection pulling effect under the control of control signal sc4
When influence, to mitigate injection pulling effect.
In one embodiment, accumulator 410, measuring circuit 420, loop filter 440, SIL controller 450 and summation
Unit 403,430 and 455 can be by the digital circuit in numeric field that reference clock CKref drives, and oscillator 460 can be with
It is numerically-controlled oscillator.For example, measuring circuit 420 can be time-to-digital converter (TDC)；In reference clock CKref
Each period in, measuring circuit 420 will export clock CKv4 effective edge edge and reference clock CKref effective edge along between
Time difference be converted to digital value, to form the sample sd4 [n] of distinguishing signal sd4.
In n-th of period, when measurement obtains sample sd4 [n] and forms deviation signal se4's by summation unit 430
When sample se4 [n], SIL controller 450 makes the value of real-time sample sa4 [n] the reflected sample se4 [n] of auxiliary signal sa4, because
This, the real-time sample sc4 [n] of the control signal sc4 after summation is by the instantaneous value of reflected sample sd4 [n].In one embodiment,
SIL controller 450 makes phase difference of the sample sa4 [n] substantially between reference clock CKref and output clock CKv4 in 180
Reverse phase is spent, therefore, the control signal sc4 to sum enables oscillator 460 to offset the influence for injecting pulling effect.
Similar to the SIL controller 250 and 350 in Fig. 2 and Fig. 3, the SIL controller 450 in Fig. 4 can be as shown in Figure 6
SIL controller 650 realize that port i4 and p4 are realized by port i6 and p6 respectively, therefore the deviation signal se4 at the i4 of port
(Fig. 4) can be used as the phase signal spd6 (Fig. 6) at the i6 of port and be received, and, the signal sa6 at the p6 of port can make
It is exported for the auxiliary signal sa4 (Fig. 4) at the p4 of port.
Referring to FIG. 5, Fig. 5 shows signal system 500 according to embodiments of the present invention.Signal system 500 includes accumulator
510, measuring circuit 520, summation unit 503,530, loop filter 540, oscillator 560, frequency divider (in figure be referred to as LO
DIV) 563, frequency mixer 565 and main amplifier 570；In order to mitigate injection pulling effect, system 500 can also include measuring circuit
580, SIL controller 550 and summation unit 555.
Oscillator 560 generates output clock CKv5 under the control of control signal sc5.Frequency divider 563 is coupled to oscillator
560, for being divided to output clock CKv5, to form local oscillated signal LO5.Frequency mixer 565 is coupled to source signal sAM
With frequency divider 563, for mixing local oscillated signal LO5 and source signal sAM, to form mixed frequency signal sm5.Main amplifier 570
It is coupled to frequency mixer 565, for amplifying to mixed frequency signal sm5, to form output signal so5.Main amplifier 570 can wrap
Include programmable gain amplifier (PGA) 572 and power amplifier (PA) 574.
Summation unit 503 sums to source signal sPM and frequency control word FCW, to form the word sw5 that sums.510 coupling of accumulator
Be connected to summation unit 503 and reference clock CKref, in each period of reference clock CKref add up summation word sw5,
To form reference signal sr5.Measuring circuit 520 is coupled to oscillator 560, for measuring reference clock CKref and output clock
Phase difference between CKv5, to form distinguishing signal sd5.Summation unit 530 is coupled in measuring circuit 520, accumulator 510 and returns
Between path filter 540, for forming deviation signal se5 according to the difference between reference signal sr5 and distinguishing signal sd5.
Loop filter 540 is filtered deviation signal se5, to form filtering signal sf5.
Measuring circuit 580 is coupled between main amplifier 570 and SIL controller 550, for measuring reference clock CKref
Phase difference between output signal so5, to form distinguishing signal sdd5.SIL controller 550 has input port i5 and output
Port p5, input port i5 are coupled to measuring circuit 580, and output port p5 is coupled to summation unit 555.It is led to mitigate injection
Draw effect, SIL controller 550 forms auxiliary signal sa5, and auxiliary signal sa5 tracks the transient change of distinguishing signal sdd5.Summation
Unit 555 is coupled in loop filter 540, between SIL controller 550 and oscillator 560, for by source signal sPM, filter
Wave signal sf5 and auxiliary signal sa5 summation controls signal sc5 to be formed.Since distinguishing signal sdd5 is by reference clock CKref
What the phase difference between output signal so5 was formed, therefore, the transient change of distinguishing signal sdd5 is able to reflect injection traction effect
Cope with the transient effects of output signal so5.SIL controller 550 will so that auxiliary signal sa5 and control signal sc5 persistently with
The transient change of track distinguishing signal sdd5 therefore can be rapid under the control of control signal sc5 of the oscillator 560 after summation
The Real Time Effect for offsetting injection pulling effect, to mitigate injection pulling effect.
In one embodiment, accumulator 510, measuring circuit 520 and 580, loop filter 540, SIL controller 550 with
And summation unit 503,530 and 555 can by the digital circuit in numeric field that reference clock CKref drives, and, vibration
Swinging device 560 can be numerically-controlled oscillator.Turn for example, each of measuring circuit 520 and 580 can be time to number
Parallel operation (TDC)；In each period of reference clock CKref, measuring circuit 520 will export effective edge edge and the ginseng of clock CKv5
The time difference examined between the effective edge edge of clock CKref is converted to digital value, to form the sample sd5 [n] of distinguishing signal sd5；
Similarly, time of the measuring circuit 580 by the effective edge of the effective edge edge of reference clock CKref and output signal so5 between
Difference is converted to digital value, to form the sample sdd5 [n] of distinguishing signal sdd5.
In n-th of period, when measurement obtains sample sdd5 [n] and forms deviation signal se5's by summation unit 530
When sample se5 [n], SIL controller 550 makes the value of real-time sample sa5 [n] tracking sample sdd5 [n] of auxiliary signal sa5,
Therefore, the real-time sample sc5 [n] of the control signal sc5 after summation is by the instantaneous value of reflected sample sdd5 [n].In an embodiment
In, SIL controller 550 can make phase difference of the sample sa5 [n] substantially between reference clock CKref and output signal so5
In 180 degree reverse phase, therefore, the control signal sc5 to sum can control the shadow that oscillator 560 offsets injection pulling effect
It rings.
Similar to the SIL controller 250,350 and 450 in Fig. 2, Fig. 3 and Fig. 4, SIL controller 550 in Fig. 5 can be by
SIL controller 650 shown in fig. 6 realizes that port i5 and p5 are realized by port i6 and p6 respectively, therefore the difference letter at the i5 of port
Number sdd5 (Fig. 5) can be used as the phase signal spd6 (Fig. 6) at the i6 of port and be received, and, the signal sa6 at the p6 of port
It can be used as the auxiliary signal sa5 (Fig. 5) at the p5 of port to be exported.
Fig. 7 is referred to incorporated by reference to Fig. 2 to Fig. 5, Fig. 7 shows the operation of system 200,300,400 and 500, wherein main step
Suddenly it can be described as follows.
Step 702: in system 200,300,400 or 500, oscillator (260,360,460 or 560) control signal
It is vibrated under the control of (sc2, sc3, sc4 or sc5), exports clock (CKv2, CKv3, CKv4 or CKv5) to generate.It is being
In system 300, quadrature modulator 365 executes orthogonal modulation by output clock CKv3, to form modulated signal sm3, and, master is put
Big device 370 amplifies modulated signal sm3, to form output signal so3.In system 400 or 500, frequency divider (463 or
563) to output clock (CKv4 or CKv5) execute frequency dividing, to be formed local oscillated signal (LO4 or LO5), frequency mixer (465 or
565) local oscillated signal and source signal sAM are mixed, to be formed mixed frequency signal (sm4 or sm5), and, main amplifier (470
Or 570) mixed frequency signal (sm4 or sm5) is amplified, to form output signal (so4 or so5).
Step 704: in system 200,300,400 or 500, measuring circuit (220,320,420 or 520) measurement reference when
Clock CKref and output clock (CKv2, CKv3, CKv4 or CKv5) between phase difference, with formed distinguishing signal (sd2, sd3,
Sd4 or sd5).In system 200 or 300, accumulator (210 or 310) adds up frequently in each period of reference clock CKref
Rate control word FCW, to form reference signal (sr2 or sr3).In system 400 or 500, summation unit (403 or 503) is to frequency
Rate control word FCW and source signal sPM summation, is summed word (sw4 or sw5) with being formed, and, accumulator (410 or 510) is referring to
Add up the summation word (sw4 or sw5) in each period of clock CKref, to form reference signal (sr4 or sr5).In system
In 200,300,400 or 500, summation unit (230,330,430 or 530) according to reference signal (sr2, sr3, sr4 or sr5) with
Difference between distinguishing signal (sd2, sd3, sd4 or sd5) forms deviation signal (se2, se3, se4 or se5).
Step 706: in system 200,300,400 or 500, loop filter (240,340,440 or 540) to deviation believe
Number (se2, se3, se4 or se5) is filtered, to form filtering signal (sf2, sf3, sf4 or sf5).
Step 708: in system 200 or 400, SIL controller (250 or 450) forms auxiliary signal (sa2 or sa4), should
The transient change of auxiliary signal (sa2 or sa4) tracing deviation signal (se2 or se4).In system 300 or 500, SIL controller
(350 or 550) form auxiliary signal (sa3 or sa5), the auxiliary signal (sa3 or sa5) track reference clock CKref and output
The transient change of phase difference between signal (so3 or so5).SIL controller 250 in system 200,300,400 or 500,
350,450 or 550 can be realized by the SIL controller 650 in Fig. 6.In system 200 or 400, SIL controller 250 or 450
Deviation signal (se2 or se4) is converted into required auxiliary signal (for example, sa2 or sa4), is drawn with correction injection pulling effect
The oscillator distortion risen.In system 300 or 500, by distinguishing signal, (sdd3 or sdd5 are ginsengs to SIL controller 350 or 550
Examine clock CKref and due to the phase difference between the output signal (so3 or so5) of oscillator (360 or 560)) be converted to institute
The auxiliary signal (for example, sa3 or sa5) needed is injected oscillator caused by pulling effect with correction and is distorted.Fig. 2, Fig. 3, Fig. 4 or
SIL controller 250,350,450 or 550 in Fig. 5 can realize that SIL controller 650 can by the SIL controller 650 in Fig. 6
It is optimal from note to be realized by data converter (for example, 652 in Fig. 6) and internal amplifier (for example, 654 in Fig. 6)
Enter condition (optimal self-injection condition).
Step 710: in system 200 or 300, summation unit 255 or 355 is according to filtering signal (sf2 or sf3) and auxiliary
Signal (sa2 or sa3) summation is helped to form control signal sc2 or sc3.In system 400 or 500, summation unit 455 or 555
Control signal (sc4 is formed by summing to filtering signal (sf4 or sf5), auxiliary signal (sa4 or sa5) and source signal sPM
Or sc5).
Referring to FIG. 8, Fig. 8 shows signal system 900 according to embodiments of the present invention.Signal system 900 is examined including phase
Survey device 920, charge pump (charge pump) 930, loop filter 940, oscillator 960, frequency divider 994 and integral difference
(sigma-delta) modulator 992；In order to mitigate oscillator 960 injection pulling effect influence, signal system 900 may be used also
To include SIL controller 950 and summation unit 955.Oscillator 960 generates output clock under the control of control signal sc9
CKv9.992 modulating frequency control word FCW of difference modulator is integrated, and, frequency divider 994 can be coupled to 960 He of oscillator
The multi-modulus frequency divider for integrating difference modulator 992, for the modulation result based on integral difference modulator 992 to output clock
CKv9 executes frequency dividing to form frequency-dividing clock CKd9.
Phase detectors 920 are coupled to frequency divider 994, for measuring between reference clock CKref and frequency-dividing clock CKd9
Phase difference, to form preliminary deviation signal sp9.Charge pump 930 be coupled in phase detectors 920 and loop filter 940 it
Between, preliminary deviation signal sp9 is converted into deviation signal se9 for converting using electric current to voltage.Loop filter 940 can be with
The low-pass filter being coupled between charge pump 930 and summation unit 955, for being filtered to deviation signal se9, with shape
At filtering signal sf9.In order to mitigate injection pulling effect, SIL controller 950 be coupled in oscillator 960 and summation unit 955 it
Between, for forming auxiliary signal by executing frequency identification (frequency discriminating) to output clock CKv9
sa9.For example, can be gone using a delay line (delay line) as frequency discriminator if SIL technology is realized when simulating PLL
The transient change of VCO output (such as CKv9) is detected, principle, that is, CKv9 self be mixed with the signal after its own delay
(self-mixing), and output signal of its low frequency signal as SIL controller is filtered out.Summation unit 955 is coupled in oscillator
Between 960, SIL controllers 950 and loop filter 940, for by filtering signal sf9 and auxiliary signal sa9 summation come
Form control signal sc9.
As shown in figure 8, SIL controller 950 include delay circuit (delay circuit) 952, internal summation unit 953,
Internal amplifier (for example, variable gain amplifier (Variable-Gain Amplifier, VGA)) 954 and data converter
956.Delay circuit 952 is coupled to oscillator 960, for forming delayed clock sy9 by delayed output clock sy9.It is internal
Summation unit 953 is coupled in oscillator 960, between delay circuit 952 and internal amplifier 954, for utilizing output clock
Difference between CKv9 and delayed clock sy9 forms distinguishing signal sd9.Internal amplifier 954 is coupled in internal summation unit
Between 953 and data converter 956, for being amplified to distinguishing signal sd9, to form amplified distinguishing signal sg9.Number
It is coupled between summation unit 955 and internal amplifier 954 according to converter 956, for converting amplified distinguishing signal sg9
For difference on the frequency (or frequency difference signal) and as auxiliary signal sa9.
In conclusion the present invention provides a kind of method of injection pulling effect for mitigating oscillator, oscillator (for example,
Fig. 2 into Fig. 5 260,360,460 or 560) in control signal (for example, sc2, sc3, sc4 or the sc5 of Fig. 2 into Fig. 5)
Control is lower to generate output clock (for example, CKv2 of the Fig. 2 into Fig. 5, CKv3, CKv4 or CKv5).This method may include: to pass through
Loop filter (for example, Fig. 2 into Fig. 5 240,340,440 or 540) to deviation signal (for example, se2 of the Fig. 2 into Fig. 5,
Se3, se4 or se5) it is filtered, to form filtering signal (for example, sf2, sf3, sf4 or the sf5 of Fig. 2 into Fig. 5)；Pass through
Self injection locking (SIL) controller (for example, Fig. 2 into Fig. 5 250,350,450 or 550) formed auxiliary signal (for example,
Sa2, sa3, sa4 or sa5 of the Fig. 2 into Fig. 5), the auxiliary signal tracing deviation signal (for example, se2 in Fig. 2 or Fig. 4 or
Se4 transient change) or track reference clock (for example, such as CKref in Fig. 3 or Fig. 5) with due to exporting the defeated of clock
The phase difference between signal (for example, most suspicious interference signal, such as the so3 or so5 in Fig. 3 or Fig. 5) is (for example, Fig. 3 or Fig. 5 out
In sdd3 or sdd5) transient change；And by filtering signal (for example, Fig. 2 sf2 into Fig. 5, sf3, sf4 or
Sf5 it) sums with auxiliary signal (for example, sa2, sa3, sa4 or the sa5 of Fig. 2 into Fig. 5) to form control signal (for example, Fig. 2
Sc2, sc3, sc4 or sc5 into Fig. 5).
(for example, Fig. 2 or Fig. 3) in one embodiment, this method can also include: by measuring circuit (for example, Fig. 2 or
In Fig. 3 220 or 320) measure reference clock and export clock between phase difference, with formed distinguishing signal (for example, Fig. 2 or
Sd2 or sd3 in Fig. 3)；Through accumulator (for example, 210 in Fig. 2 or Fig. 3 or 310) in each period of reference clock
Cumulative frequency control word (for example, FCW in Fig. 2 or Fig. 3), with formed reference signal (for example, sr2 in Fig. 2 or Fig. 3 or
sr3)；And deviation signal is formed according to the difference between the reference signal and the distinguishing signal.
(for example, Fig. 3) in one embodiment, this method can also include: by quadrature modulator (for example, in Fig. 3
365) orthogonal modulation is executed using output clock (for example, CKv3 in Fig. 3), to form modulated signal (for example, in Fig. 3
sm3)；And modulated signal is amplified to by required power level and therefore shape by main amplifier (for example, 370 in Fig. 3)
At output signal (for example, so3 in Fig. 3).
(for example, Fig. 4 or Fig. 5) in one embodiment, this method can also include: by measuring circuit (for example, Fig. 4 or
In Fig. 5 420 or 520) measure reference clock and export clock between phase difference, with formed distinguishing signal (for example, Fig. 4 or
Sd4 or sd5 in Fig. 5)；To frequency control word (for example, FCW in Fig. 4 or Fig. 5) and the first source signal (for example, Fig. 4 or Fig. 5
In sPM) summation, with formed sum word (for example, sw4 or sw5 in Fig. 4 or Fig. 5)；By accumulator (for example, Fig. 4 or Fig. 5
In 410 or the summation word that 510) adds up in each period of reference clock, to form reference signal (for example, Fig. 4 or Fig. 5
In sr4 or sr5)；And deviation signal is formed according to the difference between the reference signal and the distinguishing signal, wherein the control
Signal processed is by obtaining to filtering signal, auxiliary signal and the summation of the first source signal.
(for example, Fig. 4 or Fig. 5) in one embodiment, this method can also include: by frequency divider (for example, Fig. 4 or Fig. 5
In 463 or frequency dividing 563) is executed to output clock, with formed local oscillated signal (for example, LO4 in Fig. 4 or Fig. 5 or
LO5)；Mix local oscillated signal and the second source signal (for example, sAM in Fig. 4 or Fig. 5), with formed mixed frequency signal (for example,
Sm4 or sm5 in Fig. 4 or Fig. 5)；And by main amplifier (for example, 470 in Fig. 4 or Fig. 5 or 570) to mixed frequency signal
It amplifies, to form output signal.
(for example, Fig. 6) in one embodiment, it may include: logical for forming the mode of auxiliary signal (for example, sa6 in Fig. 6)
SIL controller (for example, 650 in Fig. 6) is crossed by the phase difference or above-mentioned deviation signal turn between reference clock and output signal
It is changed to required auxiliary signal (for example, sa6 in Fig. 6), oscillator caused by pulling effect is injected with correction and is distorted；And
It is realized by data converter (for example, 652 in Fig. 6) and internal amplifier (for example, 654 in Fig. 6) optimal from note
Enter condition.
The present invention also provides it is a kind of mitigate injection pulling effect signal system (for example, Fig. 2 into Fig. 5 200,
300,400 or 500).The signal system include oscillator (for example, Fig. 2 into Fig. 5 260,360,460 or 560), circuit filter
Wave device (for example, Fig. 2 into Fig. 5 240,340,440 or 540), SIL controller (for example, Fig. 2 into Fig. 5 250,350,
450 or 550) and the first summation unit (for example, Fig. 2 into Fig. 5 255,355,455 or 555).Oscillator is in control signal
Output clock is generated under the control of (for example, sc2, sc3, sc4 or the sc5 of Fig. 2 into Fig. 5) (for example, Fig. 2 is into Fig. 5
CKv2, CKv3, CKv4 or CKv5).Loop filter is to deviation signal (for example, se2, se3, se4 or the se5 of Fig. 2 into Fig. 5)
It is filtered, to form filtering signal (for example, sf2, sf3, sf4 or the sf5 of Fig. 2 into Fig. 5).SIL controller forms auxiliary
Signal (for example, sa2, sa3, sa4 or the sa5 of Fig. 2 into Fig. 5), the auxiliary signal tracing deviation signal is (for example, Fig. 2 or Fig. 4
In se2 or se4) transient change or track reference clock (for example, CKref in Fig. 3 or Fig. 5) and due to output clock
Output signal (for example, so3 or so5 in Fig. 3 or Fig. 5) between phase difference transient change.The coupling of first summation unit
Between loop filter, SIL controller and oscillator, for by forming control to filtering signal and auxiliary signal summation
Signal.
(for example, Fig. 2 or Fig. 3) in one embodiment, signal system can also include the first measuring circuit (for example, Fig. 2 or
In Fig. 3 220 or 320), accumulator (for example, 210 in Fig. 2 or Fig. 3 or 310) and the second summation unit (for example, Fig. 2 or
In Fig. 3 230 or 330).First measuring circuit is coupled to oscillator, for measuring reference clock and exporting the phase between clock
Potential difference, to form distinguishing signal (for example, sd2 or sd3 in Fig. 2 or Fig. 3).Accumulator tires out in each period of reference clock
Add frequency control word (for example, FCW in Fig. 2 or Fig. 3), to form reference signal (for example, sr2 or sr3 in Fig. 2 or Fig. 3).
Second summation unit can be coupled in the first measuring circuit, between accumulator and loop filter, for according to reference signal and
Difference between distinguishing signal forms deviation signal.(for example, Fig. 2 or Fig. 3) in one embodiment, the first measuring circuit can be
Time-to-digital converter (TDC).In one embodiment, oscillator can be numerically-controlled oscillator.
(for example, Fig. 3) in one embodiment, signal system can also include quadrature modulator (for example, 365 in Fig. 3)
With main amplifier (for example, 370 in Fig. 3).Quadrature modulator is coupled to oscillator, for executing positive intermodulation using output clock
System, to form modulated signal (for example, sm3 in Fig. 3).Main amplifier is coupled to quadrature modulator, for modulated signal into
Row amplification, to form output signal.(for example, Fig. 3) in one embodiment, signal system can also include being coupled in main amplifier
The second measuring circuit (for example, 380 in Fig. 3) between SIL controller, for measuring between reference clock and output signal
Phase difference.(for example, Fig. 3) in one embodiment, main amplifier may include power amplifier (for example, 374 in Fig. 3) and
Programmable gain amplifier (for example, 372 in Fig. 3).
(for example, Fig. 3) in one embodiment, signal system can also include be coupled in main amplifier and SIL controller it
Between the second measuring circuit (for example, 380 in Fig. 3), for measuring the phase difference between reference clock and output signal.
(for example, Fig. 4 or Fig. 5) in one embodiment, signal system can also include measuring circuit (for example, Fig. 4 or Fig. 5
In 420 or 520), accumulator (for example, 410 in Fig. 4 or 510), the second summation unit is (for example, 430 in Fig. 4 or Fig. 5
Or 530) and third summation unit (for example, 403 in Fig. 4 or Fig. 5 or 503).Measuring circuit is coupled to oscillator, for surveying
It measures reference clock and exports the phase difference between clock, to form distinguishing signal (for example, sd4 or sd5 in Fig. 4 or Fig. 5).It is tired
Add device to add up in each period of reference clock to sum word (for example, sw4 or sw5 in Fig. 4 or Fig. 5), to be formed with reference to letter
Number (for example, sr4 or sr5 in Fig. 4 or Fig. 5).Second summation unit is coupled in measuring circuit, accumulator and loop filter it
Between, for forming deviation signal according to the difference between reference signal and distinguishing signal.Third summation unit is coupled to accumulator,
For summing to frequency control word (for example, FCW in Fig. 4 or Fig. 5) and the first source signal (for example, sPM in Fig. 4 or Fig. 5),
To form the summation word.First summation unit (for example, 455 in Fig. 4 or Fig. 5 or 555) be arranged to by filtering signal,
Auxiliary signal and the first source signal are summed to form control signal.
(for example, Fig. 4 or Fig. 5) in one embodiment, signal system can also include frequency divider (for example, in Fig. 4 or Fig. 5
463 or 563), frequency mixer (for example, 465 in Fig. 4 or Fig. 5 or 565) and main amplifier are (for example, 470 in Fig. 4 or Fig. 5
Or 570).Frequency divider is coupled to oscillator, for executing frequency dividing to output clock, to form local oscillated signal (for example, Fig. 4
Or LO4 or LO5 in Fig. 5).Frequency mixer is coupled to frequency divider, for mix local oscillated signal and the second source signal (for example,
SAM in Fig. 4 or Fig. 5), to form mixed frequency signal (for example, sm4 or sm5 in Fig. 4 or Fig. 5).Main amplifier is coupled to mixing
Device, for being amplified to mixed frequency signal, to form output signal.
(for example, Fig. 5) in one embodiment, signal system can also include be coupled in main amplifier and SIL controller it
Between the second measuring circuit (for example, 580 in Fig. 5), for measuring the phase difference between reference clock and output signal.
(for example, Fig. 6) in one embodiment, SIL controller (for example, 650 in Fig. 6) may include data converter
(for example, 652 in Fig. 6) and internal amplifier (for example, 654 in Fig. 6).SIL controller (for example, 650 in Fig. 6) will join
It examines the phase difference between clock and output signal or the deviation signal is converted to required auxiliary signal (for example, in Fig. 6
Sa6), oscillator caused by pulling effect is injected with correction to be distorted；And pass through data converter (for example, 652 in Fig. 6)
Optimal self seeding condition is realized with internal amplifier (for example, 654 in Fig. 6).
The present invention also provides a kind of signal systems (for example, 900 in Fig. 8) for mitigating injection pulling effect.The signal
System includes oscillator (for example, 960), loop filter (for example, 940), SIL controller (for example, 950) and summation unit
(for example, 955).Oscillator generates output clock (for example, CKv9) under the control of control signal (for example, sc9).Loop filter
Device is filtered deviation signal (for example, se9), to form filtering signal (for example, sf9).When SIL controller is by output
Clock executes frequency and identifies to form auxiliary signal (for example, sa9).Summation unit (for example, 955) is coupled in oscillator, SIL control
Between device and loop filter, for by forming control signal to filtering signal and auxiliary signal summation.
(for example, Fig. 8) in one embodiment, SIL controller may include delay circuit (for example, 952), and inside summation is single
First (for example, 953), internal amplifier (for example, 954) and data converter (for example, 956).Delay circuit is coupled to oscillator,
For forming delayed clock (for example, sy9) by delayed output clock.Internal summation unit is coupled to delay circuit, is used for
Distinguishing signal (for example, sd9) is formed according to the difference between output clock and delayed clock.Internal amplifier is coupled to inside
Summation unit, for being amplified to distinguishing signal, to form amplified distinguishing signal (for example, sg9).Data converter
(for example, 956) are used to amplified distinguishing signal being converted to auxiliary signal (for example, sa9), with correction due to injection traction effect
The distortion of oscillator caused by answering.
(for example, Fig. 8) in one embodiment, signal system can also include frequency divider (for example, 994), phase detectors
(for example, 920) and charge pump (for example, 930).Frequency divider is coupled to oscillator, for executing frequency dividing to output clock, to be formed
Frequency-dividing clock (for example, CKd9).Phase detectors are coupled to frequency divider, for measuring reference clock (for example, CKref) and frequency dividing
Phase difference between clock, to form preliminary deviation signal (for example, sp9).Charge pump is coupled in phase detectors and circuit filter
Between wave device, preliminary deviation signal is converted into deviation signal for converting using electric current to voltage.
In short, the present invention can make the control when oscillator vibrates export clock to generate under control of the control signal
Signal processed reflects the variation (instantaneous) immediately of the output clock or the output signal due to the output clock, due to shape of the present invention
At control signal it is not only related with the filtering signal of loop filter but also related with the auxiliary signal specially generated, should
Auxiliary signal tracks following transient change: { i } includes the wink of the deviation signal of the phase difference between reference clock and output clock
Shi Bianhua；The transient change of the phase difference of { ii } between reference clock and output signal, or { iii } execute frequency to output clock
The transient change of the result of identification.Therefore, oscillator can offset rapidly the influence of injection pulling effect, lead to mitigate injection
Draw effect.The signal system that the composite can be widely applied to have all-digital phase-locked loop (for example, Fig. 2 to Fig. 5), or has simulation
The signal system (for example, Fig. 8) of phaselocked loop.The present invention can be used to realize RF or wireless transmitter or transceiver, or require more preferable
Ground mitigates any other signal system that injection pulling effect influences.
Although the present invention is described by way of example and according to preferred embodiment, it should manage
Solution, the present invention is not limited to disclosed embodiments.On the contrary, it be intended to cover various modifications and similar structure (such as
Those skilled in the art will be apparent), for example, the combination or replacement of the different characteristic in different embodiments.Therefore, institute
Attached the scope of the claims should be endowed widest explanation, to cover all these modifications and similar structure.
Claims (19)
1. a kind of method for the injection pulling effect for mitigating oscillator, when which generates output under control of the control signal
Clock, and, this method comprises:
Deviation signal is filtered by loop filter, to form filtering signal；
By self injection lockout controller formed auxiliary signal, the auxiliary signal track the deviation signal transient change or with
Track reference clock and transient change due to the phase difference between the output signal of the output clock；And
By forming the control signal to the filtering signal and auxiliary signal summation.
2. the method according to claim 1, wherein this method further include:
The phase difference between the reference clock and the output clock is measured, to form distinguishing signal；
The cumulative frequency control word in each period of the reference clock, to form reference signal；And
The deviation signal is formed according to the difference between the reference signal and the distinguishing signal.
3. the method according to claim 1, wherein this method further include:
Orthogonal modulation is executed using the output clock, to form modulated signal；And
The modulated signal is amplified, to form the output signal.
4. the method according to claim 1, wherein this method further include:
The phase difference between the reference clock and the output clock is measured, to form distinguishing signal；
It sums to frequency control word and the first source signal, to form summation word；
Add up the summation word in each period of the reference clock, to form reference signal；And
The deviation signal is formed according to the difference between the reference signal and the distinguishing signal；
Wherein, which generated by summing to the filtering signal, the auxiliary signal and first source signal.
5. according to the method described in claim 4, it is characterized in that, this method further include:
The output clock is divided, to form local oscillated signal；
The local oscillated signal and the second source signal are mixed, to form mixed frequency signal；And
The mixed frequency signal is amplified, to form the output signal.
6. the method according to claim 1, wherein the step of forming the auxiliary signal includes:
By between the reference clock and the output signal phase difference or the deviation signal be converted to frequency difference signal；And
The frequency difference signal is amplified, to form the auxiliary signal.
7. a kind of signal system for mitigating injection pulling effect, comprising:
Oscillator, for generating output clock under control of the control signal；
Loop filter, for being filtered to deviation signal, to form filtering signal；
Self injection locking SIL controller, be used to form auxiliary signal, the transient change of the auxiliary signal track reference clock or
Track reference clock and transient change due to the phase difference between the output signal of the output clock；And
First summation unit is coupled in the loop filter, between the SIL controller and the oscillator, for by the filter
Wave signal and the auxiliary signal are summed to form the control signal.
8. signal system according to claim 7, which is characterized in that the signal system further include:
First measuring circuit is coupled to the oscillator, for measuring the phase difference between the reference clock and the output clock, with
Form distinguishing signal；
Accumulator, for the cumulative frequency control word in each period of the reference clock, to form reference signal；And
Second summation unit is coupled in the measuring circuit, between the accumulator and the loop filter, for according to the reference letter
Difference number between the distinguishing signal forms the deviation signal.
9. signal system according to claim 8, which is characterized in that the signal system further include:
Quadrature modulator is coupled to the oscillator, for executing orthogonal modulation using the output clock, to form modulated signal；
And
Main amplifier is coupled to the quadrature modulator, for amplifying to the modulated signal, to form the output signal.
10. signal system according to claim 9, which is characterized in that the signal system further include:
Second measuring circuit is coupled between the main amplifier and the SIL controller, for measuring the reference clock and the output
Phase difference between signal.
11. signal system according to claim 9, which is characterized in that the main amplifier includes power amplifier and can compile
Journey gain amplifier.
12. signal system according to claim 8, which is characterized in that first measuring circuit is that time to number is converted
Device.
13. signal system according to claim 7, which is characterized in that the signal system further include:
First measuring circuit is coupled to the oscillator, for measuring the phase difference between the reference clock and the output clock, with
Form distinguishing signal；
Second summation unit, for summing to frequency control word and the first source signal, to form summation word；
Accumulator, for the summation word that adds up in each period of the reference clock, to form reference signal；And
Third summation unit is coupled in the measuring circuit, between the accumulator and the loop filter, for according to the reference letter
Difference number between the distinguishing signal forms the deviation signal；
Wherein, which is used for by summing the filtering signal, the auxiliary signal and first source signal come shape
At the control signal.
14. signal system according to claim 13, which is characterized in that the signal system further include:
Frequency divider is coupled to the oscillator, for dividing to the output clock, to form local oscillated signal；
Frequency mixer is coupled to the frequency divider, for mixing the local oscillated signal and the second source signal, to form mixed frequency signal；
And
Main amplifier is coupled to the frequency mixer, for amplifying to the mixed frequency signal, to form the output signal.
15. signal system according to claim 14, which is characterized in that the signal system further include:
Second measuring circuit is coupled between the main amplifier and the SIL controller, for measuring the reference clock and the output
Phase difference between signal.
16. signal system according to claim 7, which is characterized in that the SIL controller includes:
Data converter, for by between the reference clock and the output signal phase difference or the deviation signal be converted to frequency
Difference signal；And
Internal amplifier, for being amplified to the frequency difference signal, to form the auxiliary signal.
17. a kind of signal system for mitigating injection pulling effect, comprising:
Oscillator, for generating output clock under control of the control signal；
Loop filter, for being filtered to deviation signal, to form filtering signal；
SIL controller, for forming auxiliary signal by executing frequency identification to the output clock；And
First summation unit is coupled in the loop filter, between the SIL controller and the oscillator, for by the filter
Wave signal and the auxiliary signal are summed to form the control signal.
18. signal system according to claim 17, which is characterized in that the SIL controller includes:
Delay circuit is coupled to the oscillator, for forming delayed clock by postponing the output clock；
Internal summation unit is coupled to the delay circuit, for coming according to the difference between the output clock and the delayed clock
Form distinguishing signal；
Internal amplifier is coupled to the inside summation unit, for amplifying to the distinguishing signal, to form amplified area
Level signal；And
Data converter, for the amplified distinguishing signal to be converted to difference on the frequency, wherein the difference on the frequency is believed as the auxiliary
Number.
19. signal system according to claim 17, which is characterized in that the signal system further include:
Frequency divider is coupled to the oscillator, for dividing to the output clock, to form frequency-dividing clock；
Phase detectors are coupled to the frequency divider, for measuring the phase difference between reference clock and the frequency-dividing clock, to be formed
Preliminary deviation signal；And
Charge pump is coupled between the phase detectors and the loop filter, for being converted using electric current to voltage that this is first
Step deviation signal is converted into the deviation signal.
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| Application Number | Priority Date | Filing Date | Title |
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| US201762577748P | 2017-10-27 | 2017-10-27 | |
| US62/577,748 | 2017-10-27 | ||
| US16/120,513 | 2018-09-04 | ||
| US16/120,513 US10680626B2 (en) | 2017-10-27 | 2018-09-04 | Method and associated signal system improving mitigation of injection-pulling effect |
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| CN109728808B CN109728808B (en) | 2023-08-29 |
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| TWI719893B (en) * | 2020-04-29 | 2021-02-21 | 國立中山大學 | Digital self-injection-locked radar |
| CN117728833B (en) * | 2024-02-08 | 2024-05-17 | 国仪量子技术(合肥)股份有限公司 | Signal synchronization system of phase-locked amplifier and phase-locked amplifier |
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| US20190131982A1 (en) | 2019-05-02 |
| TW201918030A (en) | 2019-05-01 |
| CN109728808B (en) | 2023-08-29 |
| TWI674760B (en) | 2019-10-11 |
| US10680626B2 (en) | 2020-06-09 |
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