CN109728069A - High-voltage metal oxide semiconductor element and its manufacturing method - Google Patents

High-voltage metal oxide semiconductor element and its manufacturing method Download PDF

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CN109728069A
CN109728069A CN201711020470.4A CN201711020470A CN109728069A CN 109728069 A CN109728069 A CN 109728069A CN 201711020470 A CN201711020470 A CN 201711020470A CN 109728069 A CN109728069 A CN 109728069A
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grid
conductive type
ontology
source electrode
longitudinal direction
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CN109728069B (en
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黄宗义
陈巨峰
叶昱廷
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Richtek Technology Corp
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Richtek Technology Corp
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Abstract

A kind of high-voltage metal oxide semiconductor element and its manufacturing method, which includes: well region, body zone, grid, source electrode, multiple ontology join domains and drain electrode.Multiple ontology join domains are formed in body zone, wherein each ontology join domain is on the longitudinal direction, below the upper surface and are contacted with the upper surface, and in grid is abutted or be not adjacent in transverse direction.Multiple ontology join domains in width direction between substantially parallel arrangement and each two neighbouring ontology join domains in connecing in non-conterminous in width direction.Grid has polysilicon layer, and as one and unique electric terminal of grid, and all parts of polysilicon layer all have the first conductive type.

Description

High-voltage metal oxide semiconductor element and its manufacturing method
Technical field
The present invention relates to a kind of high-voltage metal oxide semiconductor (Metal Oxide Semiconductor, MOS) members Part particularly relates to a kind of high-voltage metal oxide semiconductor element with multiple ontology join domains.The invention further relates to height Press the manufacturing method of metal oxide semiconductor device.
Background technique
Figure 1A and 1B shows a kind of high-voltage metal oxide semiconductor element (the N-type high-pressure MOS element of prior art respectively 1 and high-pressure MOS element 1 ') schematic top plan view and corresponding diagrammatic cross-section.As referring to figs. la and 1b, high-pressure MOS element 1 with Mirror arranges high-pressure MOS element 1 ' each other, is formed in semiconductor substrate 11, wherein the semiconductor substrate 11 has on longitudinal direction Opposite upper surface 11 ' and lower surface 11 ".Wherein, high-pressure MOS element 1 is separately included with high-pressure MOS element 1 ': N-type well region 12, grid 13, N-type source 14, p-type body zone 16, N-type drain 17 and p-type ontology join domain 18.Wherein N-type source 14 It is formed in p-type body zone 16, and in p-type body zone 16, there is ontology join domain 18, to as p-type body zone 16 Electric terminal.In general, as shown, N-type source 14 and p-type ontology join domain 18 are horizontally arranged in parallel, Middle N-type source 14 is horizontally abutted with grid 13, and p-type ontology join domain 18 is not adjacent to grid 13.High-pressure MOS element 1 with high-pressure MOS element 1 ' horizontally mirror arrangement and shared ontology join domain 18 each other, it is possible to reduce integrated circuit makes With space, the size of integrated circuit is reduced.Wherein, unit spacing d1 is the length of high-pressure MOS element 1 horizontally, with unit Spacing d1 calculates the size of the high-pressure MOS element 1 of multiple mirrors arrangement.
Fig. 2A and 2B shows high-voltage metal oxide semiconductor element (the N-type high-pressure MOS member of another prior art respectively Part 2 and high-pressure MOS element 2 ') schematic top plan view and corresponding diagrammatic cross-section.As shown in Fig. 2A and 2B, high-pressure MOS element 2 Mirror arranges each other with high-pressure MOS element 2 ', is formed in semiconductor substrate 11, and wherein the semiconductor substrate 11 has on longitudinal direction There are opposite upper surface 11 ' and lower surface 11 ".Wherein, high-pressure MOS element 2 is separately included with high-pressure MOS element 2 ': N-type well region 12, grid 23, N-type source 24, p-type body zone 16, N-type drain 17 and p-type ontology join domain 28.Wherein N-type source 24 It is formed in p-type body zone 16, and in p-type body zone 16, there is ontology join domain 28, to as p-type body zone 16 Electric terminal.
High-pressure MOS element 1 shown in high-pressure MOS element 2 and high-pressure MOS element 2 ' and Figure 1A and Figure 1B and high-pressure MOS member 1 ' difference of part, is: as shown in Figure 2 A, multiple N-type sources 24 and multiple p-type ontology join domains 28 are in the direction of the width It is arranged in parallel；Grid 23 includes multiple N-type area of grid 23 ' and P-type grid electrode region 23 "；And multiple N-type area of grid 23 ' and P Type area of grid 23 " is interlaced with each other arranged in parallel in the direction of the width, and respectively with corresponding multiple N-type sources 24 and multiple P Type ontology join domain 28 horizontally abuts.Compared to high-pressure MOS element 1 and high-pressure MOS element 1 ' horizontally mirror each other Penetrate arrangement, and shared ontology join domain 18, high-pressure MOS element 2 and high-pressure MOS element 2 ' horizontally each other mirror arrangement and Shared source electrode 24 and ontology join domain 18, can be further reduced the use space of integrated circuit, and further decrease entirety The size of circuit.
Compare the unit spacing d1 of high-pressure MOS element 1 and the unit spacing d2 of high-pressure MOS element 2, wherein because high pressure The unit spacing d1 of MOS element 1 includes horizontally complete spacing and ontology the join domain 18 horizontally half of source electrode 14 Spacing, i.e. spacing d1 '；And the unit spacing d2 of high-pressure MOS element 2 only include source electrode horizontally half spacing (and with Ontology join domain 18 horizontally overlaps), i.e. spacing d2 '；Under comparing, spacing d2 ' is about the one third of spacing d1 ', Therefore high-pressure MOS element 2 and high-pressure MOS element 2 ' shown in Fig. 2A and 2B be horizontally, hence it is evident that than Figure 1A with it is high shown in 1B It presses MOS element 1 and high-pressure MOS element 1 ' small, further reduces the size of element.
However, the prior art shown in Fig. 2A and 2B, its shortcoming is that, when the formation of ontology join domain 28, institute The ion implanting step region of definition, has usually contained P-type grid electrode region 23 ", this is because the prior art is always grid 23 It is considered as self-aligning shielding, the range of ontology join domain 28 can be automatically aligned to.However, in this way, p type impurity injects Grid 23, and form P-type grid electrode region 23 ".When high voltage device MOS, which is connected, to be operated, when N-type area of grid 23 ' is connected (as shown in Figure 2 D), channel region below P-type grid electrode region 23 " are simultaneously not turned on (as shown in Figure 2 E), this makes high-pressure MOS element 2 significantly increase with the conducting resistance value of high-pressure MOS element 2 '.
In view of this, the present invention is i.e. in view of the above shortcomings of the prior art, a kind of high-pressure MOS element and its manufacturer are proposed Method can improve transient response, increase the application range of high-pressure MOS element.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art and defect, propose a kind of high-voltage metal oxide semiconductor Element and its manufacturing method can improve transient response, increase the application range of high-pressure MOS element.
In order to achieve the above-mentioned object of the invention, one of viewpoint is sayed that the present invention provides a kind of high pressure metal oxides Semiconductor (Metal Oxide Semiconductor, MOS) element, is formed in semiconductor substrate, wherein the semiconductor substrate In on a longitudinal direction, have an opposite upper surface and a lower surface, include: a well region has a first conductive type, the well region shape At in the semiconductor substrate, and on the longitudinal direction, below the upper surface and it is connected to the upper surface；One body zone, tool There is a second conductive type, which is formed in the well region, and on the longitudinal direction, below the upper surface and is connected to this Upper surface；One grid is formed on the upper surface, and on the longitudinal direction, the part gate stack is simultaneously connected to the part body zone Surface；One source electrode has the first conductive type, which is formed in the body zone, and on the longitudinal direction, the source bit Below the upper surface and it is contacted with the upper surface, and in one first side for being adjacent to the grid in a transverse direction；Multiple ontologies connect Region is connect, there is the second conductive type, multiple ontology join domain is formed in the body zone, wherein the respectively ontology bonding pad Domain below the upper surface and is contacted with the upper surface on the longitudinal direction, and in the grid are abutted or be not adjacent in the transverse direction First side of pole, wherein multiple ontology join domain is in the substantially parallel arrangement of a width direction and each two neighbouring ontologies It connects between join domain in the width direction is non-conterminous；And a drain electrode, there is the first conductive type, which is formed in the trap Qu Zhong, and on the longitudinal direction below the upper surface and is contacted with the upper surface, and in the transverse direction, positioned at the grid Except one second side, and separated with the source electrode by the body zone and the well region；Wherein the grid has a polysilicon layer, as One and unique electric terminal of the grid, and all parts of the polysilicon layer all have the first conductive type.
In a preferred embodiment, which also includes a field oxide region, is formed on the upper surface, and heap The folded surface for being connected to the part well region, wherein, close to the part of the drain side grid, including the grid in the transverse direction The second side, stack and be connected to the surface of at least partly field oxide region.
In a preferred embodiment, multiple ontology join domain respectively at the grid adjacent in the transverse direction this first Side, and the source electrode is separated as multiple source electrode sub-districts, wherein multiple source electrode sub-district in the grid adjacent in the transverse direction this Side, wherein multiple source electrode sub-district is between the substantially parallel arrangement of the width direction and each two neighbouring source electrode sub-districts in this Width direction is non-conterminous to be connect.
In a preferred embodiment, multiple ontology join domain in be not adjacent in the transverse direction grid this first Side, and the ontology join domain between first side of the grid at least separating a default spacing in the transverse direction.
In a preferred embodiment, which is not less than 0.05 micron.
Another viewpoint is sayed that present invention provides a kind of metal-oxide semiconductor (MOS) (Metal Oxide Semiconductor, MOS) manufacturing method, include: semiconductor substrate is provided, on a longitudinal direction, has opposite one Upper surface and a lower surface；A well region is formed in the semiconductor substrate, which has a first conductive type, and in the longitudinal direction On, below the upper surface and it is connected to the upper surface；A body zone is formed in the first conductive type well region, the body zone With a second conductive type, and on the longitudinal direction, below the upper surface and it is connected to the upper surface；A grid is formed in this On upper surface, on the longitudinal direction, the part gate stack and the surface for being connected to the part body zone；A source electrode is formed in this In body zone, which has the first conductive type, and on the longitudinal direction, which is located at below the upper surface and is contacted with this Upper surface, and in one first side for being adjacent to the grid in a transverse direction；Multiple ontology join domains are formed in the body zone, it should Ontology join domain has the second conductive type, wherein respectively the ontology join domain is located at below the upper surface on the longitudinal direction And it is contacted with the upper surface, and in first side that the grid is abutted or be not adjacent in the transverse direction, wherein multiple ontology connects Region is connect between the substantially parallel arrangement of a width direction and each two neighbouring ontology join domains in the width direction not phase It is adjacent；And a drain electrode is formed in the well region, which has the first conductive type, and on the longitudinal direction, is located at table on this The upper surface is simultaneously contacted with below face, and in the transverse direction, except second side for the grid, and with the source electrode by this Body area and the well region separate；Wherein the grid has a polysilicon layer, as one and unique electric terminal of the grid, And all parts of the polysilicon layer all have the first conductive type.
In a preferred embodiment, which also comprises the steps of: to form a field oxide region on this On surface, and the surface for being connected to the well region is stacked, wherein in the transverse direction, close to the part of the drain side grid, packet The second side containing the grid, stacks and is connected to the surface of at least partly field oxide region.
In a preferred embodiment, multiple ontology join domain respectively at the grid adjacent in the transverse direction this first Side, and the source electrode is separated as multiple source electrode sub-districts, wherein multiple source electrode sub-district in the grid adjacent in the transverse direction this Side, wherein multiple source electrode sub-district is between the substantially parallel arrangement of the width direction and each two neighbouring source electrode sub-districts in this Width direction is non-conterminous to be connect.
In a preferred embodiment, multiple ontology join domain in be not adjacent in the transverse direction grid this first Side, and the ontology join domain between first side of the grid at least separating a default spacing in the transverse direction.
In a preferred embodiment, which is not less than 0.05 micron.
In a preferred embodiment, the step of formation grid, comprising: to form the same of the source electrode and/or the drain electrode The impurity of the first conductive type in the form of accelerated ion beam, is injected the polysilicon layer by one first ion implantation process step In；And a photoresist layer is formed to cover the grid, in the one second ion implanting work for forming multiple ontology join domain In skill step, the impurity of the second conductive type is prevented, in the form of accelerated ion beam, is injected in the polysilicon layer.
In a preferred embodiment, the step of formation grid, comprising: to form the same of the source electrode and/or the drain electrode The impurity of the first conductive type in the form of accelerated ion beam, is injected the polysilicon layer by one first ion implantation process step In；And with one second ion implantation process step, by the impurity of the first conductive type, in the form of accelerated ion beam, injection should In polysilicon layer, by the polysilicon layer, the region with the second conductive type, all compensation are reversed to the first conductive type, so that All parts of the polysilicon layer all have the first conductive type.
Below by way of specific embodiment elaborate, should be easier to understand the purpose of the present invention, technology contents, feature and The effect of it is realized.
Detailed description of the invention
Figure 1A and 1B shows that a kind of vertical view of high-voltage metal oxide semiconductor (MOS) element of prior art is illustrated respectively Scheme and corresponding diagrammatic cross-section；
Fig. 2A -2E shows the schematic top plan view and diagrammatic cross-section of another prior art；
Fig. 3 A-3C shows one embodiment of the invention；
Fig. 4 A-4C shows second embodiment of the invention；
Fig. 5 A-5C shows third embodiment of the invention；
Fig. 6 A-6C shows the 4th embodiment of the invention；
Fig. 7 A-7N shows the 5th embodiment of the invention；
Fig. 8 A-8Q shows the 6th embodiment of the invention；
Fig. 9 A-9F shows the 7th embodiment of the invention；
Figure 10 A-10N shows the 8th embodiment of the invention；
Figure 11 A-11Q shows the 9th embodiment of the invention；
Figure 12 A-12F shows the tenth embodiment of the invention.
Symbol description in figure
1,1 ', 2,2 ', 3,4,5,6 high-pressure MOS elements
11 semiconductor substrates
11 ' upper surfaces
11 " lower surfaces
12 well regions
13,23,33,53,83 grids
14,24,34,44 source electrodes
16 body zones
17 drain electrodes
18,28,38,48 ontology join domains
20,20 ' field oxide regions
16 ', 17 ', 34 ', 38 ', 44 ', 48 ', 83 ' photoresist layers
23 " P-type grid electrode regions
341 source electrode sub-districts
531,831 grid compensating basins
A-A ' hatching line
B-B ' hatching line
D1, d2 unit spacing
D1 ', d2 ' spacing
Dp presets spacing
The first side S1
S2 second side
Specific embodiment
Attached drawing in the present invention belongs to signal, is mostly intended to indicate that the order up and down between processing step and each layer closes System then and not according to ratio draws as shape, thickness and width.
It please refers to Fig. 3 A, 3B and 3C and shows one embodiment of the invention, show high pressure gold of the invention in figure respectively Belong to top view and corresponding first sectional view of a kind of embodiment (high-pressure MOS element 3) of oxide semiconductor (MOS) element (the hatching line A-A ' corresponding to top view) and the second sectional view (the hatching line B-B ' corresponding to top view).Such as Fig. 3 A, 3B and 3C institute Showing, high-pressure MOS element 3 is formed in semiconductor substrate 11, longitudinally gone up in one (the dotted arrow direction in such as Fig. 3 B or 3C, Similarly hereinafter), with an opposite upper surface 11 ' and a lower surface 11 "；High-pressure MOS element 3 includes: well region 12, body zone 16, leakage Pole 17, grid 33, source electrode 34 and ontology join domain 38.
Please continue to refer to Fig. 3 A, 3B and 3C, wherein well region 12 has the first conductive type, is formed in semiconductor substrate 11, And on longitudinal direction, it is located at below upper surface 11 ' and is connected to the upper surface 11 '.Body zone 16 has the second conductive type, is formed in In well region 12, and on longitudinal direction, it is located at below upper surface 11 ' and is connected to the upper surface 11 '.Grid 13 is formed in upper surface On 11 ', and on longitudinal direction, part of grid pole 33 stacks and is connected to the surface of body zone 16, it should be noted that, grid 33 is vertical It overlaps place to upright projection and the second conductive type body zone 16, is channel region (the dotted line side in such as Fig. 3 B of high-pressure MOS element 3 Frame is illustrated), and grid 33 includes conductive polysilicon layer, the dielectric layer connecting with upper surface 11 ' and has electric The wall of insulation characterisitic, this is well known to those skilled in the art, and it will not be described here.
Please continue to refer to Fig. 3 A, 3B and 3C, source electrode 34 has the first conductive type, is formed in body zone 16, on longitudinal direction, Source electrode 34 is located at 11 ' lower section of upper surface and is contacted with the upper surface 11 ', and in the laterally upper (solid arrow in such as Fig. 3 B or 3C Direction, similarly hereinafter) it is adjacent to the first side S1 of grid 33.Multiple ontology join domains 38 have the second conductive type, are formed in this In body area 16, each ontology join domain 38 is located at below upper surface 11 ' on longitudinal direction and is contacted with upper surface 11 ', and in this reality It applies in example, each ontology join domain 38 is in the first side S1 for being adjacent to grid 13 in transverse direction, and multiple ontology join domains 38 are in one The substantially parallel arrangement of width direction (as shown in the arrow of " width direction " in Fig. 3 A, similarly hereinafter) and each two neighbouring ontology bonding pads It connects between domain 38 in width direction is at least partly non-conterminous；As shown in Figure 3A, in a preferred embodiment, each two neighbouring ontologies It connects between join domain 38 in width direction is non-conterminous.In the present embodiment, multiple ontology join domains 38 are respectively in transverse direction First side S1 of adjacent grid 33, and source electrode 34 is separated as multiple source electrode sub-districts 341, plurality of source electrode sub-district 341 is in cross First side S1 of adjacent grid 13 upwards, plurality of source electrode sub-district 341 is in the substantially parallel arrangement of width direction and each neighbouring It connects between two source electrode sub-districts 341 in width direction is non-conterminous.Drain electrode 17 has the first conductive type, is formed in well region 12, and in On longitudinal direction, be located at the lower section of upper surface 11 ' and be contacted with upper surface 11 ', and in transverse direction, positioned at second side S2 of grid 13 it Outside, and with source electrode 34 by body zone 16 and well region 12 it separates.
It should be noted that " the first conductive type " above-mentioned and " the second conductive type " refers in high-pressure MOS element, with difference The impurity of conductivity type be doped in semiconductor compositing area (well region such as, but not limited to above-mentioned, body zone, ontology join domain, The regions such as source electrode, drain electrode and grid) in, so that semiconductor compositing area becomes first or second conductivity type (such as, but not limited to The first conductive type is N-type, and the second conductive type be p-type, or vice versa also can).
Furthermore it should be noted that, so-called high-pressure MOS element refers to when normal operating, and the voltage for being applied to drain electrode is high In a specific voltage, such as 5V；In the present embodiment, between the drain electrode 17 of high-pressure MOS element 3 and channel region, with well region 12 every Open, and when the lateral distance (drift region length) of body zone 16 and drain electrode 17 is according to normal operating the operation voltage that is born and adjust It is whole, thus it is operable in aforementioned higher specific voltage.Wherein, channel region is the area for being controlled by grid and being connected or being not turned on Domain, the length of drift region is to adjust operation voltage, this is all well known to those skilled in the art, and it will not be described here.
It is worth noting that, the present invention is better than one of technical characteristic of the prior art, it is: according to the present invention, with For embodiment shown in Fig. 3 A, 3B and 3C, when the formation of multiple ontology join domains 38, defined ion implanting step Region, any part not comprising grid 33 compared to the prior art because grid 23 is considered as self-aligning shielding, and make P type impurity is filled with grid 23, and forms P-type grid electrode region 23 ", the polysilicon layer of the grid 33 of the present embodiment, as grid 33 one and unique electric terminal, and all parts of polysilicon layer according to the present invention all have the first conductive type, no Include any the second conductive type part.When the operation of high-pressure MOS element conductive, high-pressure MOS element 3 according to the present invention, than existing Having the conducting resistance value of technology high-pressure MOS element 2 significantly reduces.In addition, field oxide region 20 ' is not limited to region as shown in the figure (local oxidation of silicon, LOCOS) structure is aoxidized, is also shallow trench isolation (shallow trench Isolation, STI) structure.
It please refers to Fig. 4 A to 4C and shows second embodiment of the invention, show high pressure gold according to the present invention in figure respectively (Fig. 4 B is corresponded to the top view (Fig. 4 A) and the first sectional view for belonging to a kind of embodiment (high-pressure MOS element 4) of oxide semiconductor In the hatching line A-A ' of top view Fig. 4 A) and the second sectional view (Fig. 4 C, the hatching line B-B ' corresponding to top view Fig. 4 A).High-pressure MOS Element 4 is similar to high-pressure MOS element 3 above-mentioned, in the present embodiment, multiple ontology join domains 48 of high-pressure MOS element 4 in The first side S1 of grid 33 is not adjacent in transverse direction, and ontology join domain 48 is gone up between the first side S1 of grid 33 extremely in lateral Default spacing dp is separated less.And in the present embodiment, source electrode 44 is not divided into multiple source electrodes by multiple ontology join domains 48 Sub-district, and it is a region being fully connected.
It is worth noting that, in the second embodiment, presetting spacing dp and being not less than 0.05 micron, this allows for design The error range of regular (design rule), in a kind of preferred embodiment, presetting spacing dp is 0.1 micron.
Fig. 5 A-5C shows third embodiment of the invention, shows high-pressure metal oxidation according to the present invention in figure respectively (Fig. 5 B corresponds to and overlooks for a kind of top view (Fig. 5 A) of embodiment (high-pressure MOS element 5) of object semiconductor and the first sectional view The hatching line A-A ' of figure Fig. 5 A) and the second sectional view (Fig. 5 C, the hatching line B-B ' corresponding to top view Fig. 5 A).5 phase of high-pressure MOS element It is similar to high-pressure MOS element 3 above-mentioned, but in the present embodiment, high-pressure MOS element 5 includes also field oxide region 20 ', is formed in On surface 11 ', and the surface for being connected to part well region 12 is stacked, wherein the part of grid pole in transverse direction, close to 17 sides of drain electrode 53, second side S2 comprising grid 53 stack and are connected to the surface of at least partly field oxide region 20 '.
It please refers to Fig. 6 A to 6C and shows the 4th embodiment of the invention, show high pressure gold according to the present invention in figure respectively (Fig. 6 B is corresponded to the top view (Fig. 6 A) and the first sectional view for belonging to a kind of embodiment (high-pressure MOS element 6) of oxide semiconductor In the hatching line A-A ' of top view Fig. 6 A) and the second sectional view (Fig. 6 C, the hatching line B-B ' corresponding to top view Fig. 6 A).High-pressure MOS Element 6 is similar to high-pressure MOS element 5 above-mentioned, in the present embodiment, multiple ontology join domains 48 of high-pressure MOS element 6 in The first side S1 of grid 53 is not adjacent in transverse direction, and ontology join domain 48 is gone up between the first side S1 of grid 53 extremely in lateral Default spacing dp is separated less.And in the present embodiment, source electrode 44 is not divided into multiple source electrodes by multiple ontology join domains 48 Sub-district, and it is a region being fully connected.
Fig. 7 A-7N shows the 5th embodiment of the invention.The present embodiment shows a kind of high-pressure MOS member according to the present invention Part manufacturing method.By taking one embodiment mesohigh MOS element 3 as an example, firstly, schematic top plan view as shown in Figure 7 A and Fig. 7 B Shown in diagrammatic cross-section (the hatching line A-A ' corresponding to top view Fig. 7 A), provide semiconductor substrate 11, wherein semiconductor substrate 11 are such as, but not limited to P-type silicon substrate, naturally it is also possible to be other semiconductor substrates.Semiconductor substrate 11 in one it is longitudinal (such as Dotted arrow direction in Fig. 7 B) on, with an opposite upper surface 11 ' and a lower surface 11 ".Then, such as Fig. 7 A and Fig. 7 B It is shown, the first conductive type well region 12 is formed in semiconductor substrate 11, and on longitudinal direction, is located at below upper surface 11 ' and is connected In the upper surface 11 '；Wherein, the method for forming the first conductive type well region 12, such as, but not limited to lithography process, ion implanting Technique is formed with thermal process, this is well known to those skilled in the art, and it will not be described here.
Then, schematic top plan view as seen in figure 7 c is with diagrammatic cross-section shown in Fig. 7 D (corresponding to top view Fig. 7 C's Hatching line A-A ') field oxide region 20 is formed, to define the active region of high-pressure MOS element 3.Next, vertical view as seen in figure 7e Schematic diagram and diagrammatic cross-section (the hatching line A-A ' corresponding to top view Fig. 7 E) shown in Fig. 7 F, as shown, with photoresist layer 16 ' As shielding, to define the ion implanted region of the second conductive type body zone 16, and with ion implantation process step, by the second conduction Type impurity is injected in the region of definition in the form of accelerating ion to form the second conductive type body zone 16 in the first conductive type In well region 12, and on longitudinal direction, it is located at below upper surface 11 ' and is connected to the upper surface 11 '.
Next, diagrammatic cross-section shown in schematic top plan view as shown in Figure 7 G and Fig. 7 H (corresponds to top view Fig. 7 G Hatching line A-A '), as shown, form still undoped grid 33 on upper surface 11 ', and on longitudinal direction, part of grid pole 33 Stack and be connected to the surface of part the second conductive type body zone 16.
Next, diagrammatic cross-section shown in schematic top plan view as shown in Figure 7 I, Fig. 7 J is (corresponding to top view Fig. 7 I's Hatching line A-A ') with Fig. 7 K shown in diagrammatic cross-section (the hatching line B-B ' corresponding to top view Fig. 7 I), as shown, with field oxidation Area 20, photoresist layer 34 ' and photoresist layer 17 ' as shielding, with define grid 33, multiple the first conductive type source electrode sub-districts 341 with The ion implanted region of drain electrode 17, and with ion implantation process step, by the first conductive type impurity, in the form of accelerating ion, note Enter in the region of definition to be respectively formed the first conductive type polysilicon layer of grid 33, the first conductive type source electrode 34 (comprising multiple The first conductive type source electrode sub-district 341) in the second conductive type body zone 16, with drain electrode 17 in well region 12, and on longitudinal direction, the One conductivity type source electrode 34 is all located at 11 ' lower section of upper surface with drain electrode 17 and is contacted with the upper surface 11 '.Wherein, to form source electrode 34 and drain 17 same ion implantation process step, in Fig. 7 J, downward dotted arrow is illustrated, by the first conductive type Impurity is injected in polysilicon layer in the form of accelerated ion beam.The first conductive type drain electrode 17 is located at upper surface 11 ' on longitudinal direction Lower section is simultaneously contacted with upper surface 11 ', and in transverse direction, between the first conductive type source region 34, by the second conductive type ontology Area 16 and the first conductive type well region 12 separate.
Next, diagrammatic cross-section shown in schematic top plan view as shown in fig. 7l, Fig. 7 M is (corresponding to top view Fig. 7 L's Hatching line A-A ') with Fig. 7 N shown in diagrammatic cross-section (the hatching line B-B ' corresponding to top view Fig. 7 L), using photoresist layer 38 ' as shield It covers, to define the ion implanted region of multiple the second conductive type ontology join domains 38, and with ion implantation process step, by second Conductive-type impurity is injected in the region of definition in the form of accelerating ion to form multiple the second conductive type ontology join domains 38 in the second conductive type body zone 16, and each ontology join domain 38 is located at below upper surface 11 ' and is contacted on longitudinal direction Surface 11 ', and in the present embodiment, each ontology join domain 38 is in the first side S1 for being adjacent to grid 33 in transverse direction, Duo Geben Body join domain 38 in width direction it is substantially parallel arrangement and each two neighbouring ontology join domains 38 between in width direction extremely Small part is non-conterminous to be connect.In the present embodiment, it connects between each two neighbouring ontology join domains 38 in width direction is non-conterminous.? In the present embodiment, multiple ontology join domains 38 and separate source electrode 34 respectively at the first side S1 of grid 33 adjacent in transverse direction For multiple source electrode sub-districts 341, plurality of source electrode sub-district 341 is in the first side S1 of grid 33 adjacent in transverse direction, plurality of source Pole sub-district 341 connects between the substantially parallel arrangement of width direction and each two neighbouring source electrode sub-districts 341 in width direction is non-conterminous. In the present embodiment, photoresist layer 38 ' is formed to cover grid 33, in the ion implanting work for forming multiple ontology join domains 38 In skill step, the impurity of the second conductive type is prevented, in the form of accelerated ion beam, in the polysilicon layer of injector grid 33.
It is worth noting that, the present invention is better than one of technical characteristic of the prior art, it is: according to the present invention, with For embodiment shown in Fig. 7 A-7N, when the formation of multiple ontology join domains 38, defined ion implanting step area Domain, any part not comprising grid 33, that is to say, that when the formation of multiple ontology join domains 38, grid 33 is completely by light Resistance layer 38 ' is covered, to avoid the second conductive type ion implanting grid 33.Compared to the prior art shown in Fig. 2A -2E, because For grid 23 is considered as self-aligning shielding, or in order to multiple ontology join domains 28 technique accuracy selection more Step is made in the lithographic of low accuracy, and p type impurity is made to be filled with grid 23, and forms P-type grid electrode region 23 ", the present embodiment Grid 33 polysilicon layer, as one and unique electric terminal of grid 33, and polysilicon layer according to the present invention All parts all have the first conductive type, do not include any the second conductive type part.When the operation of high-pressure MOS element conductive, root According to high-pressure MOS element 3 of the invention, the conducting resistance value than prior art high-pressure MOS element 2 is significantly reduced.
Fig. 8 A-8Q shows the 6th embodiment of the invention.The present embodiment shows a kind of high-pressure MOS member according to the present invention Part manufacturing method.By taking one embodiment mesohigh MOS element 3 as an example, firstly, schematic top plan view as shown in Figure 8 A and Fig. 8 B Shown in diagrammatic cross-section (the hatching line A-A ' corresponding to top view Fig. 8 A), provide semiconductor substrate 11, wherein semiconductor substrate 11 are such as, but not limited to P-type silicon substrate, naturally it is also possible to be other semiconductor substrates.Semiconductor substrate 11 in one it is longitudinal (such as Dotted arrow direction in Fig. 8 B) on, with an opposite upper surface 11 ' and a lower surface 11 ".Then, such as Fig. 8 A and Fig. 8 B It is shown, the first conductive type well region 12 is formed in semiconductor substrate 11, and on longitudinal direction, is located at below upper surface 11 ' and is connected In the upper surface 11 '；Wherein, the method for forming the first conductive type well region 12, such as, but not limited to lithography process, ion implanting Technique is formed with thermal process, this is well known to those skilled in the art, and it will not be described here.
Then, schematic top plan view as shown in Figure 8 C is with diagrammatic cross-section shown in Fig. 8 D (corresponding to top view Fig. 8 C's Hatching line A-A ') field oxide region 20 is formed, to define the active region of high-pressure MOS element 3.Next, vertical view as illustrated in fig. 8e Schematic diagram and diagrammatic cross-section (the hatching line A-A ' corresponding to top view Fig. 8 E) shown in Fig. 8 F, as shown, with photoresist layer 16 ' As shielding, to define the ion implanted region of the second conductive type body zone 16, and with ion implantation process step, by the second conduction Type impurity is injected in the region of definition in the form of accelerating ion to form the second conductive type body zone 16 in the first conductive type In well region 12, and on longitudinal direction, it is located at below upper surface 11 ' and is connected to the upper surface 11 '.
Next, schematic top plan view as shown in fig. 8g (corresponds to top view Fig. 8 G with diagrammatic cross-section shown in Fig. 8 H Hatching line A-A '), as shown, form still undoped grid 83 on upper surface 11 ', and on longitudinal direction, part of grid pole 83 Stack and be connected to the surface of part the second conductive type body zone 16.
Next, diagrammatic cross-section shown in schematic top plan view as shown in fig. 81, Fig. 8 J is (corresponding to top view Fig. 8 I's Hatching line A-A ') with Fig. 8 K shown in diagrammatic cross-section (the hatching line B-B ' corresponding to top view Fig. 8 I), as shown, with field oxidation Area 20, photoresist layer 34 ' and photoresist layer 17 ' as shielding, with define multiple the first conductive type source electrode sub-districts 341, drain electrode 17 with The ion implanted region of the first conductive type polysilicon layer in grid 83, and with ion implantation process step, by the first conductive type impurity, In the form of accelerating ion, inject in the region of definition to be respectively formed the first conductive type polysilicon layer of grid 83, first lead Electric type source electrode 34 (including multiple the first conductive type source electrode sub-districts 341) is in the second conductive type body zone 16, with drain electrode 17 in trap In area 12, and on longitudinal direction, the first conductive type source electrode 34 and drain electrode 17 are all located at 11 ' lower section of upper surface and are contacted with the upper surface 11'.Wherein, wherein to form the same ion implantation process step of source electrode 34 and drain electrode 17, in Fig. 7 J, downward dotted line Arrow is illustrated, and the impurity of the first conductive type in the form of accelerated ion beam, injects in polysilicon layer.The first conductive type leakage Pole 17 is located at 11 ' lower section of upper surface and is contacted with upper surface 11 ' on longitudinal direction, and in transverse direction, with the first conductive type source area Domain 34 is separated by the second conductive type body zone 16 and the first conductive type well region 12.
Next, the schematic top plan view as shown in Fig. 8 L, diagrammatic cross-section shown in Fig. 8 M are (corresponding to top view Fig. 8 L Hatching line A-A ') with Fig. 8 N shown in diagrammatic cross-section (the hatching line B-B ' corresponding to top view Fig. 8 L), using photoresist layer 38 ' as shield It covers, to define the ion implanting of multiple the second conductive type ontology join domains 38 and the second conductive type polysilicon layer in grid 83 Area, and with ion implantation process step, by the second conductive type impurity, in the form of accelerating ion, inject in the region of definition with The second conductive type polysilicon layer and multiple the second conductive type ontology join domains 38 are in the second conductive type ontology in formation grid 83 In area 16, each ontology join domain 38 is located at below upper surface 11 ' on longitudinal direction and is contacted with upper surface 11 ', and in this implementation In example, each ontology join domain 38 is in the first side S1 for being adjacent to grid 83 in transverse direction, and multiple ontology join domains 38 are in width It connects between the substantially parallel arrangement in direction and each two neighbouring ontology join domains 38 in width direction is at least partly non-conterminous.At this In embodiment, connect between each two neighbouring ontology join domains 38 in width direction is non-conterminous.In the present embodiment, multiple ontologies Join domain 38 and separates source electrode 34 for multiple source electrode sub-districts 341 respectively at the first side S1 of grid 83 adjacent in transverse direction, In multiple source electrode sub-districts 341 in the first side S1 of grid 83 adjacent in transverse direction, plurality of source electrode sub-district 341 is big in width direction It causes to connect between arranged in parallel and each two neighbouring source electrode sub-districts 341 in width direction is non-conterminous.In the present embodiment, it is led second Electric type impurity injects in the region of definition in the form of accelerating ion (dotted arrow as downward in figure is illustrated) to be formed When multiple the second conductive type ontology join domains 38, also by the second conductive type impurity, in the form of accelerating ion, part grid are injected In pole 83, as Fig. 8 M and Fig. 8 N illustrates.
Next, the schematic top plan view as shown in Fig. 8 O, diagrammatic cross-section shown in Fig. 8 P are (corresponding to top view Fig. 8 O Hatching line A-A ') with Fig. 8 Q shown in diagrammatic cross-section (the hatching line B-B ' corresponding to top view Fig. 8 O), using photoresist layer 83 ' as shield It covers, to define the ion implanted region of grid compensating basin 831, and with ion implantation process step, by the first conductive type impurity, to add The form of fast ion is injected in region defined in polysilicon layer, has second to lead the part of the polysilicon layer of grid 83 The region of electric type, all compensation are reversed to the first conductive type, so that all parts of polysilicon layer all have the first conductive type.
Fig. 9 A-9F shows the 7th embodiment of the invention.The present embodiment shows a kind of high-pressure MOS member according to the present invention Part manufacturing method.For second embodiment mesohigh MOS element 4 of the invention shown in Fig. 4 A-4C.The manufacturing method of front Step is identical as the 5th embodiment of the invention shown in Fig. 7 A-7H, please refers to Fig. 7 A-7H.
Next, diagrammatic cross-section shown in schematic top plan view as shown in Figure 9 A, Fig. 9 B is (corresponding to top view Fig. 9 A's Hatching line A-A ') with Fig. 9 C shown in diagrammatic cross-section (the hatching line B-B ' corresponding to top view Fig. 9 A), as shown, with field oxidation Area 20, photoresist layer 44 ' and photoresist layer 17 ' as shielding, with define grid 33, the first conductive type source electrode 44 and drain electrode 17 from Sub- injection region, and with ion implantation process step, by the first conductive type impurity, in the form of accelerating ion, inject the area of definition In domain be respectively formed grid 33 the first conductive type polysilicon layer, the first conductive type source electrode 44 is in the second conductive type body zone 16 In, with drain electrode 17 in well region 12, and on longitudinal direction, the first conductive type source electrode 44 and drain electrode 17 are all located at 11 ' lower section of upper surface And it is contacted with the upper surface 11 '.Wherein, with formed source electrode 44 and drain 17 same ion implantation process step, as Fig. 9 B with In 9C, downward dotted arrow is illustrated, and by the impurity of the first conductive type, in the form of accelerated ion beam, injects polysilicon layer In.The first conductive type drain electrode 17 is located at 11 ' lower section of upper surface and is contacted with upper surface 11 ' on longitudinal direction, and in transverse direction, with Between the first conductive type source electrode 44, separated by the second conductive type body zone 16 and the first conductive type well region 12.
Next, diagrammatic cross-section shown in schematic top plan view as shown in fig. 9d, Fig. 9 E is (corresponding to top view Fig. 9 D's Hatching line A-A ') with Fig. 9 F shown in diagrammatic cross-section (the hatching line B-B ' corresponding to top view Fig. 9 D), using photoresist layer 48 ' as shield It covers, to define the ion implanted region of multiple the second conductive type ontology join domains 48, and with ion implantation process step, by second Conductive-type impurity is injected in the region of definition in the form of accelerating ion to form multiple the second conductive type ontology join domains 48 in the second conductive type body zone 16, and each ontology join domain 48 is located at below upper surface 11 ' and is contacted on longitudinal direction Surface 11 ', and in the present embodiment, each ontology join domain 48 is multiple in the first side S1 for not being adjacent to grid 33 in transverse direction Ontology join domain 48 is between the substantially parallel arrangement of width direction and each two neighbouring ontology join domains 48 in width direction It is at least partly non-conterminous to connect.In the present embodiment, it connects between each two neighbouring ontology join domains 48 in width direction is non-conterminous. In the present embodiment, multiple ontology join domains 48 do not abut the first side S1 of grid 33 respectively in transverse direction, and make source electrode 44 In the first side S1 of grid 33 adjacent in transverse direction.In the present embodiment, photoresist layer 48 ' is formed to cover grid 33, to be formed In the ion implantation process step of multiple ontology join domains 48, the impurity of the second conductive type is prevented, with the shape of accelerated ion beam Formula, in the polysilicon layer of injector grid 33.
It is worth noting that, the 5th implementation difference shown in the present embodiment and Fig. 7 A-7N, is: in this implementation In example, multiple ontology join domains 48 of high-pressure MOS element 4 are in the first side S1 for not being adjacent to grid 33 in transverse direction, and ontology Join domain 48 at least separates default spacing dp in laterally upper between the first side S1 of grid 33.And in the present embodiment, source electrode 44 are not divided into multiple source electrode sub-districts by multiple ontology join domains 48, and are a region being fully connected.
Figure 10 A-10N shows the 8th embodiment of the invention.The present embodiment shows a kind of high-pressure MOS according to the present invention Manufacturing method.For the third embodiment high-pressure MOS element 5 of the invention shown in Fig. 5 A-5C, firstly, such as Figure 10 A institute Diagrammatic cross-section (the hatching line A-A ' corresponding to top view Figure 10 A) shown in the schematic top plan view and Figure 10 B shown, provides semiconductor Substrate 11, wherein semiconductor substrate 11 is such as, but not limited to P-type silicon substrate, naturally it is also possible to be other semiconductor substrates.Half Conductor substrate 11 has an opposite upper surface 11 ' and a lower surface on one longitudinal (the dotted arrow direction in such as Figure 10 B) 11".Then, as shown in Figure 10 A and Figure 10 B, the first conductive type well region 12 is formed in semiconductor substrate 11, and on longitudinal direction, Positioned at 11 ' lower section of upper surface and it is connected to the upper surface 11 '；Wherein, the method for forming the first conductive type well region 12, such as but not It is limited to be formed with lithography process, ion implantation technology, with thermal process, this is well known to those skilled in the art, not superfluous herein It states.
Then, schematic top plan view as illustrated in figure 10 c (corresponds to top view Figure 10 C with diagrammatic cross-section shown in Figure 10 D Hatching line A-A ') formed field oxide region 20, to define the active region of high-pressure MOS element 5；Be formed simultaneously field oxide region 20 ' in On 11 ' upper surfaces, and stack the surface for being connected to well region 12.Next, schematic top plan view and Figure 10 F as shown in figure 10e Shown in diagrammatic cross-section (the hatching line A-A ' corresponding to top view Figure 10 E), as shown, using photoresist layer 16 ' as shielding, with The ion implanted region of the second conductive type body zone 16 is defined, and with ion implantation process step, by the second conductive type impurity, to add The form of fast ion is injected to form the second conductive type body zone 16 in the first conductive type well region 12 in the region of definition, and In on longitudinal direction, it is located at below upper surface 11 ' and is connected to the upper surface 11 '.
Next, schematic top plan view as shown in figure 10g (corresponds to top view figure with diagrammatic cross-section shown in Figure 10 H The hatching line A-A ' of 10G), as shown, form still undoped grid 53 on upper surface 11 ', 20 ' Yu Heng of field oxide Upwards, close to the part of grid pole 53 of drain electrode 17 sides (please referring to Fig. 5 A-5C), second side S2 comprising grid 53 is stacked and is connected In the surface of at least partly field oxide region 20 ', and on longitudinal direction, part of grid pole 53 stacks and is connected to part the second conductive type The surface of body zone 16.
Next, diagrammatic cross-section shown in schematic top plan view as shown in figure 10i, Figure 10 J (corresponds to top view figure The hatching line A-A ' of 10I) with Figure 10 K shown in diagrammatic cross-section (the hatching line B-B ' corresponding to top view Figure 10 I), as shown, Using field oxide region 20 and photoresist layer 34 ' as shielding, to define grid 53, multiple the first conductive type source electrode sub-districts 341 and leakage The ion implanted region of pole 17, and with ion implantation process step, by the first conductive type impurity, in the form of accelerating ion, injection To be respectively formed the first conductive type polysilicon layer of grid 53, the first conductive type source electrode 34 (comprising multiple the in the region of definition One conductivity type source electrode sub-district 341) in the second conductive type body zone 16, with drain electrode 17 in well region 12, and on longitudinal direction, first Conductivity type source electrode 34 and drain electrode 17 are all located at 11 ' lower section of upper surface and are contacted with the upper surface 11 '.Wherein, to form source electrode 34 And the same ion implantation process step of drain electrode 17, in Figure 10 J and 10K, downward dotted arrow is illustrated, by the first conduction The impurity of type is injected in polysilicon layer in the form of accelerated ion beam.The first conductive type drain electrode 17 is located at upper table on longitudinal direction The lower section of face 11 ' is simultaneously contacted with upper surface 11 ', and in transverse direction, between the first conductive type source region 34, by the second conductive type Body zone 16 and the first conductive type well region 12 separate.
Next, the schematic top plan view as shown in Figure 10 L, diagrammatic cross-section shown in Figure 10 M (correspond to top view figure The hatching line A-A ' of 10L) with Figure 10 N shown in diagrammatic cross-section (the hatching line B-B ' corresponding to top view Figure 10 L), with photoresist layer 38 ' as shielding, to define the ion implanted region of multiple the second conductive type ontology join domains 38, and are walked with ion implantation technology Suddenly, it by the second conductive type impurity, in the form of accelerating ion, injects in the region of definition to form multiple the second conductive type ontologies In the second conductive type body zone 16, each ontology join domain 38 is located at below upper surface 11 ' simultaneously join domain 38 on longitudinal direction It is contacted with upper surface 11 ', and in the present embodiment, each ontology join domain 38 is in the first side for being adjacent to grid 33 in transverse direction S1, multiple ontology join domains 38 are between the substantially parallel arrangement of width direction and each two neighbouring ontology join domains 38 in width Direction is at least partly non-conterminous connects for degree.In the present embodiment, between each two neighbouring ontology join domains 38 in width direction not It is adjacent.In the present embodiment, multiple ontology join domains 38 respectively at grid 33 adjacent in transverse direction the first side S1, and by source Pole 34 separates as multiple source electrode sub-districts 341, plurality of source electrode sub-district 341 in the first side S1 of grid 33 adjacent in transverse direction, In multiple source electrode sub-districts 341 in width direction it is substantially parallel arrangement and each two neighbouring source electrode sub-districts 341 between in width direction It is non-conterminous to connect.In the present embodiment, photoresist layer 38 ' is formed to cover grid 33, to form multiple ontology join domains 38 In ion implantation process step, the impurity of the second conductive type is prevented, in the form of accelerated ion beam, the polysilicon of injector grid 33 In layer.
It is worth noting that, the present invention is better than one of technical characteristic of the prior art, it is: according to the present invention, with For embodiment shown in Figure 10 A-10N, when the formation of multiple ontology join domains 38, defined ion implanting step area Domain, any part not comprising grid 53, that is to say, that when the formation of multiple ontology join domains 38, grid 53 is completely by light Resistance layer 38 ' is covered, to avoid the second conductive type ion implanting grid 53.Compared to the prior art shown in Fig. 2A -2E, because For grid 23 is considered as self-aligning shielding, or in order to multiple ontology join domains 28 technique accuracy selection more Step is made in the lithographic of low accuracy, and p type impurity is made to be filled with grid 23, and forms P-type grid electrode region 23 ", the present embodiment Grid 53 polysilicon layer, as one and unique electric terminal of grid 53, and polysilicon layer according to the present invention All parts all have the first conductive type, do not include any the second conductive type part.When the operation of high-pressure MOS element conductive, root According to high-pressure MOS element 5 of the invention, the conducting resistance value than prior art high-pressure MOS element 2 is significantly reduced.
Figure 11 A-11Q shows the 9th embodiment of the invention.The present embodiment shows a kind of high-pressure MOS according to the present invention Manufacturing method.By taking third embodiment mesohigh MOS element 5 as an example, firstly, schematic top plan view as shown in Figure 11 A with Diagrammatic cross-section shown in Figure 11 B (the hatching line A-A ' corresponding to top view Figure 11 A), provides semiconductor substrate 11, wherein partly lead Structure base board 11 is such as, but not limited to P-type silicon substrate, naturally it is also possible to be other semiconductor substrates.Semiconductor substrate 11 is vertical in one To on (the dotted arrow direction in such as Figure 11 B), with an opposite upper surface 11 ' and a lower surface 11 ".Then, such as Figure 11 A With shown in Figure 11 B, formation the first conductive type well region 12 is located at below upper surface 11 ' in semiconductor substrate 11, and on longitudinal direction And it is connected to the upper surface 11 '；Wherein, formed the first conductive type well region 12 method, such as, but not limited to lithography process, from Sub- injection technology is formed with thermal process, this is well known to those skilled in the art, and it will not be described here.
Then, schematic top plan view as shown in Figure 11 C (corresponds to top view Figure 11 C with diagrammatic cross-section shown in Figure 11 D Hatching line A-A ') formed field oxide region 20, to define the active region of high-pressure MOS element 5；Be formed simultaneously field oxide region 20 ' in On 11 ' upper surfaces, and stack the surface for being connected to well region 12.Next, schematic top plan view and Figure 11 F as depicted in fig. 11E Shown in diagrammatic cross-section (the hatching line A-A ' corresponding to top view Figure 11 E), as shown, using photoresist layer 16 ' as shielding, with The ion implanted region of the second conductive type body zone 16 is defined, and with ion implantation process step, by the second conductive type impurity, to add The form of fast ion is injected to form the second conductive type body zone 16 in the first conductive type well region 12 in the region of definition, and In on longitudinal direction, it is located at below upper surface 11 ' and is connected to the upper surface 11 '.
Next, schematic top plan view as shown in fig. 11g (corresponds to top view figure with diagrammatic cross-section shown in Figure 11 H The hatching line A-A ' of 11G), as shown, form still undoped grid 53 on upper surface 11 ', and on longitudinal direction, part of grid pole 53 stack and are connected to the surface of part the second conductive type body zone 16.
Next, diagrammatic cross-section shown in schematic top plan view as shown in figure 11I, Figure 11 J (corresponds to top view figure The hatching line A-A ' of 11I) with Figure 11 K shown in diagrammatic cross-section (the hatching line B-B ' corresponding to top view Figure 11 I), as shown, Using field oxide region 20 and photoresist layer 34 ' as shielding, to define multiple the first conductive type source electrode sub-districts 341, drain electrode 17 and grid The ion implanted region of the first conductive type polysilicon layer in pole 53, and with ion implantation process step, by the first conductive type impurity, with The form for accelerating ion is injected in the region of definition and is respectively formed the first conductive type polysilicon layer, the first conduction of grid 53 Type source electrode 34 (including multiple the first conductive type source electrode sub-districts 341) is in the second conductive type body zone 16, with drain electrode 17 in well region In 12, and on longitudinal direction, the first conductive type source electrode 34 and drain electrode 17 are all located at 11 ' lower section of upper surface and are contacted with the upper surface 11'.Wherein, wherein to form the same ion implantation process step of source electrode 34 and drain electrode 17, in Figure 11 J, downward dotted line Arrow is illustrated, and the impurity of the first conductive type in the form of accelerated ion beam, injects in polysilicon layer.The first conductive type leakage Pole 17 is located at 11 ' lower section of upper surface and is contacted with upper surface 11 ' on longitudinal direction, and in transverse direction, with the first conductive type source area Domain 34 is separated by the second conductive type body zone 16 and the first conductive type well region 12.
Next, diagrammatic cross-section shown in schematic top plan view as shown in figure 11L, Figure 11 M (corresponds to top view figure The hatching line A-A ' of 11L) with Figure 11 N shown in diagrammatic cross-section (the hatching line B-B ' corresponding to top view Figure 11 L), with photoresist layer 38 ' as shielding, to define multiple the second conductive type ontology join domains 38 and the second conductive type polysilicon layer in grid 53 Ion implanted region, and with ion implantation process step, by the second conductive type impurity, in the form of accelerating ion, inject definition It is led with forming in grid 53 the second conductive type polysilicon layer with multiple the second conductive type ontology join domains 38 in second in region In electric type body zone 16, each ontology join domain 38 is located at below upper surface 11 ' on longitudinal direction and is contacted with upper surface 11 ', and In the present embodiment, each ontology join domain 38 is in the first side S1 for being adjacent to grid 53 in transverse direction, multiple ontology join domains 38 between the substantially parallel arrangement of width direction and each two neighbouring ontology join domains 38 in width direction at least partly not phase It is adjacent.In the present embodiment, it connects between each two neighbouring ontology join domains 38 in width direction is non-conterminous.In the present embodiment In, multiple ontology join domains 38 and separate source electrode 34 for multiple sources respectively at the first side S1 of grid 53 adjacent in transverse direction Pole sub-district 341, plurality of source electrode sub-district 341 is in the first side S1 of grid 53 adjacent in transverse direction, plurality of source electrode sub-district 341 It connects between the substantially parallel arrangement of width direction and each two neighbouring source electrode sub-districts 341 in width direction is non-conterminous.In this implementation In example, in the second conductive type impurity, in the form of accelerating ion (dotted arrow as downward in figure is illustrated), definition is injected When in region to form multiple the second conductive type ontology join domains 38, also by the second conductive type impurity, to accelerate the shape of ion Formula is injected in part of grid pole 53, as Figure 11 M and Figure 11 N illustrates.
Next, the schematic top plan view as shown in Figure 11 O, diagrammatic cross-section shown in Figure 11 P (correspond to top view figure The hatching line A-A ' of 11O) with Figure 11 Q shown in diagrammatic cross-section (the hatching line B-B ' corresponding to top view Figure 11 O), with photoresist layer 53 ' as shielding, to define the ion implanted region of grid compensating basin 531, and with ion implantation process step, by the first conductive type Impurity is injected in region defined in polysilicon layer in the form of accelerating ion, and the part of the polysilicon layer of grid 53 is had There is the region of the second conductive type, all compensation are reversed to the first conductive type, so that all parts of polysilicon layer all have first to lead Electric type.
Figure 12 A-12F shows the tenth embodiment of the invention.The present embodiment shows a kind of high-pressure MOS according to the present invention Manufacturing method.For the 4th embodiment mesohigh MOS element 6 of the invention shown in Fig. 6 A-6C.The manufacturer of front Method step is identical as the 8th embodiment of the invention shown in Figure 10 A-10H, please refers to Figure 10 A-10H.
Next, diagrammatic cross-section shown in schematic top plan view as illustrated in fig. 12, Figure 12 B (corresponds to top view figure The hatching line A-A ' of 12A) with Figure 12 C shown in diagrammatic cross-section (the hatching line B-B ' corresponding to top view Figure 12 A), as shown, Using field oxide region 20 and photoresist layer 44 ' as shielding, to define the ion of grid 53, the first conductive type source electrode 44 and drain electrode 17 Injection region, and with ion implantation process step, by the first conductive type impurity, in the form of accelerating ion, inject the region of definition It is interior be respectively formed grid 53 the first conductive type polysilicon layer, the first conductive type source electrode 44 is in the second conductive type body zone 16 In, with drain electrode 17 in well region 12, and on longitudinal direction, the first conductive type source electrode 44 and drain electrode 17 are all located at 11 ' lower section of upper surface And it is contacted with the upper surface 11 '.Wherein, with formed source electrode 44 and drain 17 same ion implantation process step, as Figure 12 B with In 12C, downward dotted arrow is illustrated, and by the impurity of the first conductive type, in the form of accelerated ion beam, injects polysilicon layer In.The first conductive type drain electrode 17 is located at 11 ' lower section of upper surface and is contacted with upper surface 11 ' on longitudinal direction, and in transverse direction, with Between the first conductive type source electrode 44, separated by the second conductive type body zone 16 and the first conductive type well region 12.
Next, diagrammatic cross-section shown in schematic top plan view as indicated in fig. 12d, Figure 12 E (corresponds to top view figure The hatching line A-A ' of 12D) with Figure 12 F shown in diagrammatic cross-section (the hatching line B-B ' corresponding to top view Figure 12 D), with photoresist layer 48 ' as shielding, to define the ion implanted region of multiple the second conductive type ontology join domains 48, and are walked with ion implantation technology Suddenly, it by the second conductive type impurity, in the form of accelerating ion, injects in the region of definition to form multiple the second conductive type ontologies In the second conductive type body zone 16, each ontology join domain 48 is located at below upper surface 11 ' simultaneously join domain 48 on longitudinal direction It is contacted with upper surface 11 ', and in the present embodiment, each ontology join domain 48 is in the first side for not being adjacent to grid 33 in transverse direction S1, multiple ontology join domains 48 are between the substantially parallel arrangement of width direction and each two neighbouring ontology join domains 48 in width Direction is at least partly non-conterminous connects for degree.In the present embodiment, between each two neighbouring ontology join domains 48 in width direction not It is adjacent.In the present embodiment, multiple ontology join domains 48 are respectively in transverse direction, the first side S1 of not adjacent grid 53, and Make source electrode 44 in the first side S1 of grid 53 adjacent in transverse direction.In the present embodiment, formed photoresist layer 48 ' to cover grid 53, To prevent the impurity of the second conductive type in the ion implantation process step for forming multiple ontology join domains 48, with accelerate from The form of beamlet, in the polysilicon layer of injector grid 53.
It is worth noting that, the 8th implementation difference shown in the present embodiment and Figure 10 A-10N, is: in this reality Apply in example, multiple ontology join domains 48 of high-pressure MOS element 6 in the first side S1 for not being adjacent to grid 53 in transverse direction, and this Body join domain 48 at least separates default spacing dp in laterally upper between the first side S1 of grid 53.And in the present embodiment, source Pole 44 is not divided into multiple source electrode sub-districts by multiple ontology join domains 48, and is a region being fully connected.
Illustrate the present invention for preferred embodiment above, but described above, is only easy to those skilled in the art Understand the contents of the present invention, interest field not for the purpose of limiting the invention.Under same spirit of the invention, art technology Personnel are contemplated that various equivalence changes.For example, other processing steps or knot can be added in the case where not influencing the main characteristic of element Structure, such as critical voltage adjust area；For another example, lithographic techniques are not limited to masking techniques, also may include e-beam lithography；Again Such as, conductivity type p-type can be interchanged with N-type, it is only necessary to which corresponding mutual change poles is also made in other regions can.The scope of the present invention should cover Above-mentioned and other all equivalence changes.In addition, under same spirit of the invention, it may occur to persons skilled in the art that various etc. Effect variation and various combinations, for example, it is can also be applied in the high voltage device of other patterns.It follows that in this hair Under bright same spirit, it may occur to persons skilled in the art that various equivalence changes and various combinations, a combination thereof mode is a lot of, Explanation numerous to list herein.Therefore, the scope of the present invention should cover above-mentioned and other all equivalence changes.

Claims (12)

1. a kind of high-voltage metal oxide semiconductor element, which is characterized in that be formed in semiconductor substrate, wherein the semiconductor Substrate has an opposite upper surface and a lower surface, which includes on a longitudinal direction:
One well region has a first conductive type, which is formed in the semiconductor substrate, and on the longitudinal direction, is located on this Lower face is simultaneously connected to the upper surface；
One body zone has a second conductive type, which is formed in the well region, and on the longitudinal direction, is located at table on this Below face and it is connected to the upper surface；
One grid is formed on the upper surface, and on the longitudinal direction, the part gate stack is simultaneously connected to the part body zone just Top；
One source electrode has the first conductive type, which is formed in the body zone, and on the longitudinal direction, which is located at should Below upper surface and it is contacted with the upper surface, and in one first side for being adjacent to the grid in a transverse direction；
Multiple ontology join domains have the second conductive type, and multiple ontology join domain is formed in the body zone, wherein Respectively the ontology join domain below the upper surface and is contacted with the upper surface, and in adjacent in the transverse direction on the longitudinal direction Or it is not adjacent to first side of the grid, wherein multiple ontology join domain is in the substantially parallel arrangement of a width direction and each It connects between the ontology join domain of neighbouring two in the width direction is non-conterminous；And
One drain electrode, has the first conductive type, which is formed in the well region, and on the longitudinal direction, is located under the upper surface Side is simultaneously contacted with the upper surface, and in the transverse direction, except second side for the grid, and with the source electrode by the body zone And the well region separates；
Wherein the grid has a polysilicon layer, as one and unique electric terminal of the grid, and the polysilicon layer All parts all have the first conductive type.
2. high-voltage metal oxide semiconductor element according to claim 1, wherein also include a field oxide region, formed In on the upper surface, and the surface for being connected to the part well region is stacked, wherein in the transverse direction, close to the part of the drain side The grid, the second side comprising the grid, stacks and is connected to the surface of at least partly field oxide region.
3. high-voltage metal oxide semiconductor element according to claim 1 or 2, wherein multiple ontology join domain It separates respectively at first side of the grid adjacent in the transverse direction, and by the source electrode as multiple source electrode sub-districts, wherein multiple source Pole sub-district is in first side of the grid adjacent in the transverse direction, wherein multiple source electrode sub-district is in the substantially parallel row of the width direction It connects between column and each two neighbouring source electrode sub-districts in the width direction is non-conterminous.
4. high-voltage metal oxide semiconductor element according to claim 1 or 2, wherein multiple ontology join domain In first side for not being adjacent to the grid in the transverse direction, and the ontology join domain in this laterally it is upper and the grid this first A default spacing is at least separated between side.
5. high-voltage metal oxide semiconductor element according to claim 4, wherein the default spacing is micro- not less than 0.05 Rice.
6. a kind of high-voltage metal oxide semiconductor element manufacturing method, characterized by comprising:
Semiconductor substrate is provided, on a longitudinal direction, there is an opposite upper surface and a lower surface；
A well region is formed in the semiconductor substrate, which has a first conductive type, and on the longitudinal direction, is located at table on this Below face and it is connected to the upper surface；
A body zone is formed in the first conductive type well region, which has a second conductive type, and on the longitudinal direction, position Below the upper surface and it is connected to the upper surface；
A grid is formed on the upper surface, on the longitudinal direction, the part gate stack is simultaneously connected to the part body zone just Top；
A source electrode is formed in the body zone, which has the first conductive type, and on the longitudinal direction, which is located on this Lower face is simultaneously contacted with the upper surface, and in one first side for being adjacent to the grid in a transverse direction；
Multiple ontology join domains are formed in the body zone, which has the second conductive type, wherein respectively should Ontology join domain below the upper surface and is contacted with the upper surface on the longitudinal direction, and in abutting in the transverse direction or not Be adjacent to first side of the grid, wherein multiple ontology join domain in a width direction it is substantially parallel arrangement and it is each neighbouring The two ontology join domains between connect in the width direction is non-conterminous；And
A drain electrode is formed in the well region, which has the first conductive type, and on the longitudinal direction, is located at below the upper surface And be contacted with the upper surface, and in the transverse direction, except second side for the grid, and with the source electrode by the body zone with And the well region separates；
Wherein the grid has a polysilicon layer, as one and unique electric terminal of the grid, and the polysilicon layer All parts all have the first conductive type.
7. high-voltage metal oxide semiconductor element manufacturing method according to claim 6, wherein also include following step It is rapid: a field oxide region is formed on the upper surface, and stacks the surface for being connected to the well region, wherein in the transverse direction, it is close The part of the drain side grid, the second side comprising the grid stack and are connected at least partly that the field oxide region is being just Top.
8. high-voltage metal oxide semiconductor element manufacturing method according to claim 6 or 7, wherein multiple ontology Join domain is separated respectively at first side of the grid adjacent in the transverse direction, and by the source electrode as multiple source electrode sub-districts, wherein Multiple source electrode sub-district is in first side of the grid adjacent in the transverse direction, wherein multiple source electrode sub-district is big in the width direction It causes to connect between arranged in parallel and each two neighbouring source electrode sub-districts in the width direction is non-conterminous.
9. high-voltage metal oxide semiconductor element manufacturing method according to claim 6 or 7, wherein multiple ontology Join domain is in first side for not being adjacent to the grid in the transverse direction, and the ontology join domain is in the lateral upper and grid First side between at least separate a default spacing.
10. high-voltage metal oxide semiconductor element manufacturing method according to claim 9, wherein the default spacing is not Less than 0.05 micron.
11. high-voltage metal oxide semiconductor element manufacturing method according to claim 6, wherein the formation grid The step of, comprising:
To form same first ion implantation process step of the source electrode and/or the drain electrode, by the impurity of the first conductive type, to add The form of fast ion beam is injected in the polysilicon layer；And
A photoresist layer is formed to cover the grid, in the one second ion implantation technology step for forming multiple ontology join domain In rapid, the impurity of the second conductive type is prevented, in the form of accelerated ion beam, is injected in the polysilicon layer.
12. high-voltage metal oxide semiconductor element manufacturing method according to claim 6, wherein the formation grid The step of, comprising:
To form same first ion implantation process step of the source electrode and/or the drain electrode, by the impurity of the first conductive type, to add The form of fast ion beam is injected in the polysilicon layer；And
With one second ion implantation process step, by the impurity of the first conductive type, in the form of accelerated ion beam, the polycrystalline is injected In silicon layer, by the polysilicon layer, the region with the second conductive type, all compensation are reversed to the first conductive type, so that this is more All parts of crystal silicon layer all have the first conductive type.
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