CN109726150A

CN109726150A - A method of realizing that the order of a variety of DDR agreements is sent

Info

Publication number: CN109726150A
Application number: CN201811646195.1A
Authority: CN
Inventors: 王亮
Original assignee: BRITE SEMICONDUCTOR (SHANGHAI) Corp
Current assignee: BRITE SEMICONDUCTOR (SHANGHAI) Corp
Priority date: 2018-12-29
Filing date: 2018-12-29
Publication date: 2019-05-07

Abstract

The invention discloses a kind of methods that the order for realizing a variety of DDR agreements is sent, and increase by two register groups in DDR controller, and a register group saves the data of rising edge clock, another register group saves the data of clock falling edge.The order that several combination ddr modes are realized using the mode of software, reduces design difficulty, while improving the flexibility of design and use.

Description

A method of realizing that the order of a variety of DDR agreements is sent

Technical field

The present invention relates to DDR (Double Data Rate synchronous DRAM) technical fields, more particularly to realize a variety of DDR The method that the order of agreement is sent.

Background technique

With the evolution of DDR, JEDEC (joint electron device engineering council) provides that DDR command is more and more, is adding In actual utilization, DDR controller needs compatible two kinds even several DDR agreements, and the order of every kind of DDR standard also has much not Equally, this just brings difficulty to our DDR controller design.And the design scheme of the prior art is real with the mode of hardware Existing various DDR commands, for bring the disadvantage is that design becomes especially complex, flexibility is also not high enough.

Summary of the invention

The purpose of the present invention is to provide a kind of methods that the order for realizing a variety of DDR agreements is sent, and use the side of software Formula come realize it is several combination ddr modes orders.

Realizing the technical solution of above-mentioned purpose is:

A method of realizing that the order of a variety of DDR agreements is sent, two register groups of increase in DDR controller, one A register group saves the data of rising edge clock, another register group saves the data of clock falling edge.

Preferably, each register group is made of 16 registers.

Preferably, the data of rising edge clock and failing edge, including DDR3, DDR4, LPDDR (Low Power Double Data Rate SDRAM) 2 and LPDDR3 order.

The beneficial effects of the present invention are: the present invention increases by two register groups, several groups are realized using the mode of software The order for closing ddr mode, reduces design difficulty, while improving the flexibility of design and use.

Detailed description of the invention

Fig. 1 is the schematic diagram for the method that the order of a variety of DDR agreements of realization of the invention is sent.

Specific embodiment

The present invention will be further described with reference to the accompanying drawings.

Referring to Fig. 1, the method that the order of a variety of DDR agreements of realization of the invention is sent, increases by two in DDR controller A register group, a register group save the data of rising edge clock, another register group saves the number of clock falling edge According to.

The DDR command transmission timing according to as defined in JEDEC standard, it is known that, DDR3/DDR4 order transmission is that single clock edge has Effect, and LPDDR2/LPDDR3 order transmission is doubleclocking along effective.So the transmission of compound command must be just single clock Along effectively, DDR3/DDR4, LPDDR2/LPDDR3 could be compatible with.

Each register group is made of 16 registers, can continuously transmit 16 groups of DDR commands.Provide a register It saves the data (such as table 1, i.e. phase0 table) of rising edge clock, the number of clock falling edge is saved with another register According to (such as table 1, i.e. phase1 table), the port of the combination DDR agreement listed in table, including DDR3/DDR4, LPDDR2/ The order of LPDDR3 can realize the transmission of various orders with two above register.

Table 1

Wherein, bit (position), addr (address), bg (bank group), ba (bank block), act_n (activation command), we_n (write It is enabled), cas_n (showing effect), ras_n (row is effective), cs_n (piece choosing), cke (clock enables).

When controller is in DDR3/DDR4 mode, because not needing doubleclocking edge, then two registers keep same The data of sample, when controller is in LPDDR mode, the data of two registers can be different, with this come when realizing double Clock is sent along order.

Above embodiments are used for illustrative purposes only, rather than limitation of the present invention, the technology people in relation to technical field Member, without departing from the spirit and scope of the present invention, can also make various transformation or modification, therefore all equivalent Technical solution also should belong to scope of the invention, should be limited by each claim.

Claims

1. a kind of method that the order for realizing a variety of DDR agreements is sent, which is characterized in that increase by two in DDR controller and post Storage group, a register group save the data of rising edge clock, another register group saves the data of clock falling edge.

2. the method that the order according to claim 1 for realizing a variety of DDR agreements is sent, which is characterized in that each described Register group is made of 16 registers.

3. the method that the order according to claim 1 for realizing a variety of DDR agreements is sent, which is characterized in that clock rises The data on edge and failing edge, the order including DDR3, DDR4, LPDDR2 and LPDDR3.