CN109713040A - A kind of integrated circuit structure - Google Patents
A kind of integrated circuit structure Download PDFInfo
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- CN109713040A CN109713040A CN201811562039.7A CN201811562039A CN109713040A CN 109713040 A CN109713040 A CN 109713040A CN 201811562039 A CN201811562039 A CN 201811562039A CN 109713040 A CN109713040 A CN 109713040A
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- 230000006835 compression Effects 0.000 claims abstract description 39
- 238000007906 compression Methods 0.000 claims abstract description 39
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 230000009286 beneficial effect Effects 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000000605 extraction Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000001737 promoting effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
A kind of integrated circuit structure provided by the invention, the integrated circuit structure by being arranged tensile stress insulating film or non-tensile stress insulating film on the nmos transistors, to increase or decrease the performance of NMOS transistor, compression insulating film or non-compression insulating film are set on the pmos transistors, to increase or decrease the performance of PMOS transistor, produce the controllable transistor of greater number of performance range, and, pass through the stress intensity of proof stress insulating film, and whether adulterate Ge element, meet accurate matching of the circuit different piece to transistor performance demand in SoC design, to in the case where ensuring that circuit performance obtains satisfaction, the power consumption of SoC is reduced as far as possible, the especially power consumption of subthreshold value extremely low power dissipation SoC, and then improve the work efficiency of SoC.
Description
Technical field
The present invention relates to technical field of integrated circuits, more specifically to a kind of integrated circuit structure.
Background technique
It, generally can be to similar in order to meet demand of the circuit to the different performance of device in ic manufacturing process
The transistor of the transistor manufacture different threshold voltages version of type, meets different circuit design demands, such as high threshold voltage device
Part is chiefly used in constituting low-power consumption or low-speed circuits part, and low threshold voltage device is chiefly used in constituting high speed circuit part, normal threshold
Threshold voltage device is chiefly used in constituting middling speed circuit part.
But the control of the threshold voltage of limited quantity is so that the control of device performance can only be very limited amount of thick
Grain range, in order to meet circuit performance, generally require select performance far more than circuit requirements transistor, thus consume it is unnecessary
Energy.
Summary of the invention
In view of this, technical solution is as follows to solve the above problems, the present invention provides a kind of integrated circuit structure:
A kind of integrated circuit structure, the integrated circuit structure include multiple NMOS transistors and multiple PMOS transistors；
Wherein, tensile stress insulating film, NMOS described in rest part are covered on the gate structure of the part NMOS transistor
Non- tensile stress insulating film is covered on the gate structure of transistor；And/or it is covered on the gate structure of the part PMOS transistor
Compression insulating film covers non-compression insulating film on the gate structure of PMOS transistor described in rest part.
Preferably, the stress of covering to the tensile stress insulating film on the gate structure of the part NMOS transistor is close
It spends of different sizes；And/or it covers to the stress of the compression insulating film on the gate structure of the part PMOS transistor
Density is of different sizes.
Preferably, non-tensile stress insulating film is covered on the gate structure of NMOS transistor described in the rest part, comprising:
Compression insulating film is covered on the gate structure of NMOS transistor described in rest part.
Preferably, answering to the compression insulating film on the gate structure of NMOS transistor described in rest part is covered
Force density is of different sizes.
Preferably, non-tensile stress insulating film is covered on the gate structure of NMOS transistor described in the rest part, comprising:
Unstressed insulating film is covered on the gate structure of NMOS transistor described in rest part.
Preferably, non-compression insulating film is covered on the gate structure of PMOS transistor described in the rest part, comprising:
Tensile stress insulating film is covered on the gate structure of PMOS transistor described in rest part.
Preferably, answering to the tensile stress insulating film on the gate structure of PMOS transistor described in rest part is covered
Force density is of different sizes.
Preferably, non-compression insulating film is covered on the gate structure of PMOS transistor described in the rest part, comprising:
Unstressed insulating film is covered on the gate structure of PMOS transistor described in rest part.
Preferably, the source contact regions of the PMOS transistor and drain contact areas adulterate Ge element, form SiGe,
To promote the performance of the PMOS transistor.
Preferably, the source contact regions of the NMOS transistor and drain contact areas adulterate Ge element, form SiGe,
To reduce the performance of the NMOS transistor.
Compared to the prior art, what the present invention realized has the beneficial effect that
The integrated circuit structure, by the way that tensile stress insulating film or non-tensile stress insulating film are arranged on the nmos transistors, with
The performance of NMOS transistor is increased or decreased, compression insulating film or non-compression insulating film are set on the pmos transistors, with
The performance for increasing or decreasing PMOS transistor produces the controllable transistor of greater number of performance range, meets SoC
Accurate matching of the circuit different piece to transistor performance demand in (System-on-Chip, system on chip) design, thus
In the case where ensuring that circuit performance obtains satisfaction, the power consumption of SoC, the especially function of subthreshold value extremely low power dissipation SoC are reduced as far as possible
Consumption, and then improve the work efficiency of SoC.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of schematic diagram of integrated circuit structure provided in an embodiment of the present invention；
Fig. 2 is a kind of structural schematic diagram of NMOS transistor provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of another NMOS transistor provided in an embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of PMOS transistor provided in an embodiment of the present invention；
Fig. 5 is the structural schematic diagram of another PMOS transistor provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
With reference to Fig. 1-Fig. 5, Fig. 1 is a kind of schematic diagram of integrated circuit structure provided in an embodiment of the present invention, and Fig. 2 is this hair
A kind of structural schematic diagram for NMOS transistor that bright embodiment provides, Fig. 3 are another NMOS crystal provided in an embodiment of the present invention
The structural schematic diagram of pipe, Fig. 4 are a kind of structural schematic diagram of PMOS transistor provided in an embodiment of the present invention, and Fig. 5 is the present invention
The structural schematic diagram for another PMOS transistor that embodiment provides, the integrated circuit structure 11 include multiple NMOS transistors 12
With multiple PMOS transistors 13；
Wherein, as shown in Fig. 2, covering tensile stress insulating film 21 on the gate structure G of the part NMOS transistor 12, such as
Shown in Fig. 3, non-tensile stress insulating film 31 is covered on the gate structure G of NMOS transistor 12 described in rest part；
As shown in figure 4, compression insulating film 41 is covered on the gate structure G of the part PMOS transistor 13, such as Fig. 5 institute
Show, non-compression insulating film 51 is covered on the gate structure G of PMOS transistor 13 described in rest part.
It should be noted that NMOS transistor 12 is one layer of oxide insulating layer 22 of generation in P type substrate, then use up
Carving technology spreads two highly doped N-type regions, and from N-type region extraction electrode, i.e., one of them is drain D, the other is source S,
One layer of metal layer is plated on oxide insulating layer between source S and drain D as gate structure G.
PMOS transistor 13 is one layer of oxide insulating layer 42 of generation in N-type substrate, then with photoetching process diffusion two
A highly doped p type island region, from p type island region extraction electrode, i.e., one of them is drain D, the other is source S, in source S and drain electrode
One layer of metal layer is plated on oxide insulating layer 42 between D as gate structure G.
In this embodiment, in order to improve the performance of device, it is suitable generally to cover on the gate structure of transistor
Insulating film with stress covers tensile stress insulating film 21, on the gate structure G of NMOS transistor 12 to improve NMOS crystal
The performance of pipe covers compression insulating film 41, on the gate structure G of PMOS transistor 13 to improve the property of PMOS transistor
Energy.
In fact, demand of the majority circuit part to performance be not high in SoC, majority circuit part is meeting performance need
Low-power consumption as far as possible is more required under the premise of asking.
Therefore, in embodiments of the present invention, by covering non-tensile stress insulating film on the gate structure of NMOS transistor,
To reduce the performance of NMOS transistor, non-compression insulating film is covered, on the gate structure of PMOS transistor to reduce PMOS
The performance of transistor, that is, effectively reduce power consumption under the premise of meeting circuit performance demand.
It should be noted that the NMOS transistor and the PMOS transistor specific position in integrated circuits, it can
Depending on specific circuit requirements, when circuit requirements high-performance, using covering tensile stress insulating film NMOS transistor and/
Or the PMOS transistor of covering compression insulating film；When circuit requirements low performance, using the non-tensile stress insulating film of covering
The PMOS transistor of NMOS transistor and/or the non-compression insulating film of covering, to reduce circuit power consumption.
Further, it is based on the above embodiment of the present invention, is covered to the gate structure of the part NMOS transistor 12
The tensile stress insulating film 21 stress intensity it is of different sizes；
It covers to the stress intensity of the compression insulating film 41 on the gate structure of the part PMOS transistor 13
It is of different sizes.
In this embodiment, the same type of stress insulation covered on the gate structure of same type of transistor
Film, stress intensity size can be different, that is, the same type covered on the gate structure of same type of transistor is answered
Power insulating film stress intensity can there are many, to provide performance different transistors, Ke Yigeng by the difference of stress intensity
Good satisfaction designs different circuits to the different demands of transistor performance, and can reduce power consumption to greatest extent.
Further, the above embodiment of the present invention, the gate structure G of NMOS transistor 12 described in the rest part are based on
The upper non-tensile stress insulating film 31 of covering, comprising:
Compression insulating film is covered on the gate structure G of NMOS transistor 12 described in rest part.
In this embodiment, when non-tensile stress insulating film 31 is compression insulating film, its advantages are NMOS transistor
Carrier mobility in 12 channels reduces, and 12 reduced performance of NMOS transistor, 12 performance of pair nmos transistor is wanted in circuit
When asking not high, under the premise of meeting circuit performance requirement, circuit can be further decreased using the transistor of this structure
Power consumption.
Further, it is based on the above embodiment of the present invention, is covered to the grid knot of NMOS transistor 12 described in rest part
The stress intensity of the compression insulating film on structure G is of different sizes.
In this embodiment, the multiple compression insulating films covered on the gate structure G of multiple NMOS transistors 12,
Between multiple compression insulating films stress intensity can there are many, so that it is different to provide performance by the difference of stress intensity
NMOS transistor can better meet and design different circuits to the different demands of transistor performance, and can be maximum
Reduce power consumption.
Further, the above embodiment of the present invention, the gate structure G of NMOS transistor 12 described in the rest part are based on
The upper non-tensile stress insulating film 31 of covering, comprising:
Unstressed insulating film is covered on the gate structure of NMOS transistor described in rest part.
In this embodiment, when non-tensile stress insulating film 31 is unstressed insulating film, the beneficial effect is that compared to use
When compression insulating film, the carrier mobility in 12 channel of NMOS transistor is higher, and transistor performance is higher, but compared to adopting
When with tensile stress insulating film, the carrier mobility in 12 channel of NMOS transistor is lower, and transistor performance is lower, in circuit
When 12 performance requirement of pair nmos transistor is not high and not low, under the premise of meeting circuit performance requirement, this structure is used
Transistor can further decrease the power consumption of circuit.
Further, the above embodiment of the present invention, the gate structure G of PMOS transistor 13 described in the rest part are based on
The upper non-compression insulating film 51 of covering, comprising:
Tensile stress insulating film is covered on the gate structure G of PMOS transistor 13 described in rest part.
In this embodiment, when non-compression insulating film 51 is tensile stress insulating film, the beneficial effect is that PMOS transistor
Carrier mobility in 13 channels reduces, PMOS transistor reduced performance, and pair pmos transistor performance requirement is not in circuit
Gao Shi can further decrease the power consumption of circuit using the transistor of this structure under the premise of meeting circuit performance requirement.
Further, it is based on the above embodiment of the present invention, is covered to the grid knot of PMOS transistor 13 described in rest part
The stress intensity of the tensile stress insulating film on structure G is of different sizes.
In this embodiment, the multiple tensile stress insulating films covered on the gate structure of multiple PMOS transistors are more
Between a tensile stress insulating film stress intensity can there are many, so that it is different to provide performance by the difference of stress intensity
PMOS transistor can better meet and design different circuits to the different demands of transistor performance, and can be maximum
Reduce power consumption.
Further, the above embodiment of the present invention, the gate structure G of PMOS transistor 13 described in the rest part are based on
The upper non-compression insulating film 51 of covering, comprising:
Unstressed insulating film is covered on the gate structure G of PMOS transistor 13 described in rest part.
In this embodiment, when non-tensile stress insulating film 51 is unstressed insulating film, the beneficial effect is that compared to use
When tensile stress insulating film, the carrier mobility in PMOS transistor channel is higher, and PMOS transistor performance is higher, but compared to
When using compression insulating film, the carrier mobility in PMOS transistor channel is reduced, and transistor performance reduces, in circuit
When pair pmos transistor performance requirement is not high and not low, under the premise of meeting circuit performance requirement, the crystalline substance of this structure is used
Body pipe can further decrease the power consumption of circuit.
Further, it is based on the above embodiment of the present invention, the source contact regions of the PMOS transistor 13 and drain electrode connect
Region doping Ge element is touched, SiGe is formed, to promote the performance of the PMOS transistor 13.
In this embodiment, by two p type island regions of PMOS transistor 13, i.e. source contact regions and drain contact region
Ge element is adulterated in domain, forms SiGe, compression is generated in the channel direction of PMOS transistor 13, to promote PMOS transistor 13
Performance.
Further, it is based on the above embodiment of the present invention, the source contact regions of the NMOS transistor 12 and drain electrode connect
Region doping Ge element is touched, SiGe is formed, to reduce the performance of the NMOS transistor 12.
In this embodiment, pass through two N-type regions in NMOS transistor 12, i.e. source contact regions and drain contact region
Ge element is adulterated in domain, forms SiGe, compression is generated in the channel direction of NMOS transistor 12, to reduce NMOS transistor 12
Performance.
Further, in existing integrated circuit structure, in order to meet the needs for promoting transistor performance, under the prior art
A kind of stress types (tensile stress) insulating film is used to all NMOS transistors, and stress intensity is identical；To all PMOS crystal
Pipe is using another stress types (compression) insulating film, and stress intensity is identical.For PMOS source/drain contact area doping Ge member
It is to do entirely that element, which forms SiGe, for promoting PMOS performance；It then undopes Ge to NMOS source drain contact region, because in NMOS source/drain
Contact zone doping Ge can reduce NMOS performance.Present this structure to do not need improving performance or performance boost do not need it is too high
Transistor so will lead to some unnecessary power consumptions using stress insulating film and PMOS source/drain contact area doping Ge.
In addition, the prior art does not have the effect of abundant different stress types insulating film, such as without being dropped using stress insulating film
Low device performance is to reduce circuit power consumption.
In order to preferably reduce power consumption, need in integrated circuit structure more subtly using the type of stress insulating film,
Size, source drain contact region doping Ge of stress intensity etc., to reduce power consumption under the premise of meeting circuit performance.
However, as can be seen from the above description, a kind of integrated circuit structure provided by the invention, by the nmos transistors
Tensile stress insulating film or non-tensile stress insulating film are set, to increase or decrease the performance of NMOS transistor, on the pmos transistors
Compression insulating film or non-compression insulating film are set and produce greater number to increase or decrease the performance of PMOS transistor
The controllable transistor of performance range, also, by the stress intensity of proof stress insulating film, and whether adulterate Ge element,
Accurate matching of the circuit different piece to transistor performance demand in SoC design is met, thus ensuring that circuit performance obtains
In the case where satisfaction, the power consumption of SoC, the especially power consumption of subthreshold value extremely low power dissipation SoC are reduced as far as possible, and then improve SoC's
Work efficiency.
A kind of integrated circuit structure provided by the present invention is described in detail above, it is used herein specifically a
Principle and implementation of the present invention are described for example, and it is of the invention that the above embodiments are only used to help understand
Method and its core concept；At the same time, for those skilled in the art, according to the thought of the present invention, in specific embodiment party
There will be changes in formula and application range, in conclusion the contents of this specification are not to be construed as limiting the invention.
It should be noted that all the embodiments in this specification are described in a progressive manner, each embodiment weight
Point explanation is the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
For the device disclosed in the embodiment, since it is corresponded to the methods disclosed in the examples, so being described relatively simple, phase
Place is closed referring to method part illustration.
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that the element that the process, method, article or equipment including a series of elements is intrinsic,
It further include either the element intrinsic for these process, method, article or equipments.In the absence of more restrictions,
The element limited by sentence "including a ...", it is not excluded that in the process, method, article or equipment including the element
In there is also other identical elements.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. a kind of integrated circuit structure, which is characterized in that the integrated circuit structure includes multiple NMOS transistors and multiple
PMOS transistor；
Wherein, tensile stress insulating film, NMOS crystal described in rest part are covered on the gate structure of the part NMOS transistor
Non- tensile stress insulating film is covered on the gate structure of pipe；And/or covering pressure is answered on the gate structure of the part PMOS transistor
Power insulating film covers non-compression insulating film on the gate structure of PMOS transistor described in rest part.
2. integrated circuit structure according to claim 1, which is characterized in that cover to the grid of the part NMOS transistor
The stress intensity of the tensile stress insulating film in the structure of pole is of different sizes；And/or it covers to the part PMOS transistor
The stress intensity of the compression insulating film on gate structure is of different sizes.
3. integrated circuit structure according to claim 1, which is characterized in that NMOS transistor described in the rest part
Non- tensile stress insulating film is covered on gate structure, comprising:
Compression insulating film is covered on the gate structure of NMOS transistor described in rest part.
4. integrated circuit structure according to claim 3, which is characterized in that covering to NMOS transistor described in rest part
Gate structure on the compression insulating film stress intensity it is of different sizes.
5. integrated circuit structure according to claim 1, which is characterized in that NMOS transistor described in the rest part
Non- tensile stress insulating film is covered on gate structure, comprising:
Unstressed insulating film is covered on the gate structure of NMOS transistor described in rest part.
6. integrated circuit structure according to claim 1, which is characterized in that PMOS transistor described in the rest part
Non- compression insulating film is covered on gate structure, comprising:
Tensile stress insulating film is covered on the gate structure of PMOS transistor described in rest part.
7. integrated circuit structure according to claim 6, which is characterized in that covering to PMOS transistor described in rest part
Gate structure on the tensile stress insulating film stress intensity it is of different sizes.
8. integrated circuit structure according to claim 1, which is characterized in that PMOS transistor described in the rest part
Non- compression insulating film is covered on gate structure, comprising:
Unstressed insulating film is covered on the gate structure of PMOS transistor described in rest part.
9. integrated circuit structure according to claim 1, which is characterized in that the source contact regions of the PMOS transistor
Ge element is adulterated with drain contact areas, SiGe is formed, to promote the performance of the PMOS transistor.
10. integrated circuit structure according to claim 1, which is characterized in that the source contact area of the NMOS transistor
Domain and drain contact areas adulterate Ge element, SiGe are formed, to reduce the performance of the NMOS transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811562039.7A CN109713040A (en) | 2018-12-20 | 2018-12-20 | A kind of integrated circuit structure |
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| CN201811562039.7A CN109713040A (en) | 2018-12-20 | 2018-12-20 | A kind of integrated circuit structure |
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| CN1937227A (en) * | 2005-09-20 | 2007-03-28 | 松下电器产业株式会社 | Semiconductor device and method for manufacturing the same |
| CN101207126A (en) * | 2006-12-22 | 2008-06-25 | 国际商业机器公司 | Scalable strained fet device and method of fabricating the same |
| CN101558494A (en) * | 2005-04-06 | 2009-10-14 | 飞思卡尔半导体公司 | Interlayer dielectric under stress for an integrated circuit |
| CN102420231A (en) * | 2011-04-29 | 2012-04-18 | 上海华力微电子有限公司 | SRAM (Static Random Access Memory) unit structure based on fake contact etch stop layer technology and preparation method of SRAM unit structure |
| US20140042549A1 (en) * | 2012-08-09 | 2014-02-13 | Globalfoundries Inc. | Methods of forming stress-inducing layers on semiconductor devices |
-
2018
- 2018-12-20 CN CN201811562039.7A patent/CN109713040A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101558494A (en) * | 2005-04-06 | 2009-10-14 | 飞思卡尔半导体公司 | Interlayer dielectric under stress for an integrated circuit |
| CN1937227A (en) * | 2005-09-20 | 2007-03-28 | 松下电器产业株式会社 | Semiconductor device and method for manufacturing the same |
| CN101207126A (en) * | 2006-12-22 | 2008-06-25 | 国际商业机器公司 | Scalable strained fet device and method of fabricating the same |
| CN102420231A (en) * | 2011-04-29 | 2012-04-18 | 上海华力微电子有限公司 | SRAM (Static Random Access Memory) unit structure based on fake contact etch stop layer technology and preparation method of SRAM unit structure |
| US20140042549A1 (en) * | 2012-08-09 | 2014-02-13 | Globalfoundries Inc. | Methods of forming stress-inducing layers on semiconductor devices |
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Application publication date: 20190503 |