CN109713028B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN109713028B CN109713028B CN201711014991.9A CN201711014991A CN109713028B CN 109713028 B CN109713028 B CN 109713028B CN 201711014991 A CN201711014991 A CN 201711014991A CN 109713028 B CN109713028 B CN 109713028B
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- 238000000034 method Methods 0.000 claims abstract description 35
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- 238000005468 ion implantation Methods 0.000 claims description 32
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Abstract
The invention provides a semiconductor device and a method for manufacturing the same, the device includes: the semiconductor device comprises a semiconductor substrate, a grid structure is formed on the semiconductor substrate, and a source electrode area and a drain electrode area are formed in the semiconductor substrate on two sides of the grid structure; at least a first doping type lightly doped region, a first doping type heavily doped region and a second doping type doped region are formed in the source region. The semiconductor device provided by the invention has lower subcritical swing amplitude, reduces leakage current and reduces power consumption.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
With the continuous development of semiconductor technology, the performance of integrated circuits is improved mainly by the continuous reduction of the size of integrated circuit devices to increase the speed thereof. Currently, the semiconductor industry has progressed to the nanotechnology process node in pursuit of high device density, high performance, and low cost. However, in deep submicron technologies, the decrease of threshold voltage, the decrease of channel length, and the decrease of gate dielectric thickness in CMOS circuits all result in severe leakage current. In the field of semiconductor technology, a leakage current (leakage current) phenomenon will cause an increase in power consumption of a semiconductor device, while reducing stability and reliability of the device.
Therefore, it is necessary to provide a new semiconductor device to solve the above problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The present invention provides a semiconductor device comprising:
the semiconductor device comprises a semiconductor substrate, a grid structure is formed on the semiconductor substrate, and a source electrode area and a drain electrode area are formed in the semiconductor substrate on two sides of the grid structure;
at least a first doping type lightly doped region and a first doping type heavily doped region and a second doping type doped region which are positioned in the first doping type lightly doped region are formed in the source region.
Further, the first doping type heavily doped region is arranged adjacent to the second doping type doping region; or,
the second doping type doping area is positioned in the first doping type heavily doped area.
Further, the first doping type doping comprises N-type doping and the second doping type doping comprises P-type doping; or,
the first doping type doping comprises P-type doping and the second doping type doping comprises N-type doping;
the P-type doping ions comprise B ions or In ions, and the N-type doping ions comprise P ions or As ions.
Further, the first doping type heavily doped region and the second doping type doping region form a voltage stabilizing diode.
Further, the doping concentration of the second doping type doping region is higher than that of the first doping type heavily doped region.
Further, the doping concentration of the first doping type heavily doped region is more than 1E14atom/cm 2 。
Further, the doping concentration of the first doping type lightly doped region is 8E12atom/cm 2 -1.2E13atom/cm 2 。
Further, the semiconductor device includes a low sub-threshold voltage swing device.
The invention also provides a manufacturing method of the semiconductor device, which comprises the following steps:
providing a semiconductor substrate, and forming a gate structure on the semiconductor substrate;
performing first ion implantation to form first doping type heavily doped regions in the semiconductor substrate on two sides of the gate structure;
performing second ion implantation to form a first doping type lightly doped region in the semiconductor substrate of at least the source region, wherein the doping depth of the first doping type lightly doped region is greater than that of the first doping type heavily doped region, and the doping concentration of the first doping type lightly doped region is lower than that of the first doping type heavily doped region;
forming side walls on two sides of the grid structure;
a third ion implantation is performed to form a second doping type doped region in at least the first doping type lightly doped region of the source region.
Further, the first doping type heavily doped region is arranged adjacent to the second doping type doping region; or,
the second doping type doping area is located in the first doping type heavily doped area.
Further, the first doping type doping comprises N-type doping and the second doping type doping comprises P-type doping; or,
the first doping type doping comprises P-type doping and the second doping type doping comprises N-type doping;
the P-type doping ions comprise B ions or In ions, and the N-type doping ions comprise P ions or As ions.
Further, the second ion implantation is LDD ion implantation.
Further, the first doping type heavily doped region and the second doping type doping region form a voltage stabilizing diode.
Further, the doping concentration of the second doping type doping region is higher than that of the first doping type heavily doped region.
Further, the doping concentration of the first doping type heavily doped region is more than 1E14atom/cm 2 。
Further, the doping concentration of the first doping type lightly doped region is 8E12atom/cm 2 -1.2E13atom/cm 2 。
Further, the semiconductor device includes a low sub-threshold voltage swing device.
According to the semiconductor device provided by the invention, the semiconductor substrate is at least provided with the first doping type lightly doped region in the source region, and the first doping type heavily doped region and the second doping type doped region which are positioned in the first doping type lightly doped region. The semiconductor device has lower subcritical swing amplitude, is communicated when the reverse bias voltage exceeds the threshold voltage, and has very small leakage current when the reverse bias voltage is lower, so that the leakage current is reduced, and the power consumption is reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail embodiments of the present invention with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings, like reference numbers generally represent like parts or steps.
In the drawings:
fig. 1A to 1E are schematic cross-sectional views of semiconductor devices respectively obtained by steps sequentially carried out by a method according to an exemplary embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of another semiconductor device obtained by sequentially performing steps of a method according to an exemplary embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of a semiconductor device obtained by the steps of a method implementation according to another exemplary embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a semiconductor device obtained by sequentially performing steps of a method according to another exemplary embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of another semiconductor device obtained by steps performed in sequence by a method according to another exemplary embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of yet another semiconductor device obtained by sequential steps of a method according to another exemplary embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of still another semiconductor device obtained by sequentially performing steps of a method according to another exemplary embodiment of the present invention.
Fig. 8 is a schematic flow chart of a method of fabricating a semiconductor device according to an exemplary embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
With the continuous development of semiconductor technology, the performance of integrated circuits is improved mainly by the continuous reduction of the size of integrated circuit devices to increase the speed thereof. Currently, the semiconductor industry has progressed to the nanotechnology process node in pursuit of high device density, high performance, and low cost. However, in deep submicron technologies, the decrease of threshold voltage, the decrease of channel length, and the decrease of gate dielectric thickness in CMOS circuits all result in severe leakage current. In the field of semiconductor technology, a leakage current (leakage current) phenomenon will cause an increase in power consumption of a semiconductor device, while reducing stability and reliability of the device.
Therefore, it is necessary to provide a new semiconductor device to solve the above problems.
In view of the deficiencies of the prior art, the present invention provides a semiconductor device comprising:
the semiconductor device comprises a semiconductor substrate, a grid structure is formed on the semiconductor substrate, and a source electrode area and a drain electrode area are formed in the semiconductor substrate on two sides of the grid structure;
at least a first doping type lightly doped region and a first doping type heavily doped region and a second doping type doped region which are positioned in the first doping type lightly doped region are formed in the source region.
The first doping type heavily doped region and the second doping type heavily doped region are arranged adjacently; or the second doping type doping region is positioned in the first doping type heavily doped region. The first doping type doping comprises N-type doping and the second doping type doping comprises P-type doping; or, the first doping type doping comprises P-type doping and the second doping type doping comprises N-type doping; wherein the P-type doped ions comprise B ions or In ions, and the N-type doped ions comprise PIons or As ions. The first doping type heavily doped region and the second doping type doping region form a voltage stabilizing diode. The doping concentration of the second doping type doping region is higher than that of the first doping type heavily doped region; the doping concentration of the first doping type heavily doped region is more than 1E14atom/cm 2 (ii) a The doping concentration of the first doping type lightly doped region is 8E12atom/cm 2 -1.2E13atom/cm 2 . The semiconductor device includes a low sub-threshold voltage swing device.
According to the semiconductor device provided by the invention, the semiconductor substrate is at least provided with the first doping type lightly doped region in the source region, and the first doping type heavily doped region and the second doping type doped region which are positioned in the first doping type lightly doped region. The semiconductor device has lower subcritical swing amplitude, is communicated when the reverse bias voltage exceeds the threshold voltage, and has very small leakage current when the reverse bias voltage is lower, so that the leakage current is reduced, and the power consumption is reduced.
Reference is now made to fig. 1-8, wherein fig. 1A-1E are schematic cross-sectional views of semiconductor devices respectively obtained by sequential steps of a method according to an exemplary embodiment of the present invention; fig. 2 is a schematic cross-sectional view of another semiconductor device obtained by steps performed in sequence by a method according to an exemplary embodiment of the present invention; fig. 3 is a schematic cross-sectional view of a semiconductor device obtained by the steps of a method implementation according to another exemplary embodiment of the invention; fig. 4 is a schematic cross-sectional view of a semiconductor device obtained by steps carried out in sequence by a method according to another exemplary embodiment of the present invention; fig. 5 is a schematic cross-sectional view of another semiconductor device obtained by steps performed in sequence by a method according to another exemplary embodiment of the present invention; fig. 6 is a schematic cross-sectional view of yet another semiconductor device obtained by sequential steps of a method according to another exemplary embodiment of the present invention; fig. 7 is a schematic cross-sectional view of still another semiconductor device obtained by sequential steps of a method according to another exemplary embodiment of the present invention; fig. 8 is a schematic flow chart of a method of fabricating a semiconductor device according to an exemplary embodiment of the invention.
The structure of the semiconductor device provided by the present invention is described below with reference to fig. 1E, and includes: the semiconductor device comprises a semiconductor substrate 100, a gate structure 101, a first doping type heavily doped region 1001, a first doping type lightly doped region 1002 and a second doping type doped region 1003. Wherein:
the semiconductor substrate 100 may be at least one of the following materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon germanium-on-insulator (S-SiGeOI), silicon germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like. As an example, the constituent material of the semiconductor substrate 100 is monocrystalline silicon. An isolation structure is also formed in the semiconductor substrate 100, and the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, and divides the semiconductor substrate 100 into different active regions, in which various semiconductor devices can be formed.
A well (well) is also formed in the semiconductor substrate 100. Illustratively, when the semiconductor substrate is an N-type substrate, a P well is formed in the N-type substrate; and when the substrate is a P-type substrate, forming an N well in the P-type substrate. As an example, the semiconductor substrate 100 is an N-type substrate, and specifically, an N-type substrate commonly used in the art may be selected by a person skilled in the art, and a P well is formed in the semiconductor substrate 100.
A gate structure 101 is formed on the semiconductor substrate 100, and the gate structure 101 may include a gate dielectric layer 1011 and a gate material layer 1012 sequentially stacked from bottom to top.
Illustratively, the gate dielectric layer 1011 may include an oxide layer, such as silicon dioxide (SiO) 2 ) And (3) a layer.
Illustratively, the gate material layer 1012 may include one or more of a polysilicon layer, a metal layer, a doped metal nitride layer, a doped metal oxide layer, and a metal silicide layer, wherein the metal layer may be composed of tungsten (W), nickel (Ni), or titanium (Ti); the doped metal nitride layer may include a titanium nitride (TiN) layer; the doped metal oxide layer may include iridium oxide (IrO) 2 ) A layer; the metal silicide layer may be wrappedIncluding a titanium silicide (TiSi) layer. As one example, the gate material layer 1012 is a polysilicon layer.
A first doping type lightly doped region 1002 and a first doping type heavily doped region 1001 and a second doping type doped region 1003 within the first doping type lightly doped region 1002 are formed in the source region.
Illustratively, in the semiconductor device provided by the present invention, the relative position relationship between the first doping type heavily doped region 1001 and the second doping type heavily doped region 1003 includes that the second doping type doped region 1003 is located in the first doping type heavily doped region 1001, as shown in fig. 1E, that is, a PN junction formed by the second doping type doped region 1003 and the first doping type heavily doped region 1001 is a vertical structure.
It should be noted that the relative position relationship between the first doping type heavily doped region 1001 and the second doping type heavily doped region 1003 formed according to the method of the present invention is not limited to the above case, and the first doping type heavily doped region 1001 and the second doping type heavily doped region 1003 may be adjacently disposed, as shown in fig. 2, that is, a PN junction formed by the second doping type doping region 1003 and the first doping type heavily doped region 1001 is a horizontal structure.
Illustratively, the first doping type is N-type doping and the second doping type is P-type doping, or the first doping type is P-type doping and the second doping type is N-type doping. As one example, the first doping type doping is an N-type doping and the second doping type doping is a P-type doping, in particular, N-type doping ions include As ions or P ions, and P-type doping ions include B ions or In ions.
Illustratively, the doping concentration of the second doping type doped region is higher than that of the first doping type heavily doped regionThe doping concentration of the first doping type heavily doped region is more than 1E14atom/cm 2 The doping concentration of the first doping type lightly doped region is 8E12atom/cm 2 -1.2E13atom/cm 2 Preferably 1E13atom/cm 2 。
It should be noted that the semiconductor device structure provided by the present invention is not limited to the above structure, and may further include a first doping type lightly doped region 1002, and a first doping type heavily doped region 1001 and a second doping type doped region 1003 located in the first doping type lightly doped region 1002, which are simultaneously formed in the source region and the drain region. Wherein, the second doping type doped 1003 region in the source region and the drain region is located in the first doping type heavily doped region 1001, as shown in fig. 4; or the second doping type doped 1003 region in the source region and the drain region is arranged adjacent to the first doping type heavily doped region 1001, as shown in fig. 5; or the second doping type doped 1003 region in the source region is located in the first doping type heavily doped region 1001, and the second doping type doped 1003 region in the drain region is arranged adjacent to the first doping type heavily doped region 1001, as shown in fig. 6; or the second doping type doped 1003 region in the source region is arranged adjacent to the first doping type heavily doped region 1001, and the second doping type doped 1003 region in the drain region is positioned in the first doping type heavily doped region 1001, as shown in fig. 7.
The semiconductor device provided by the invention comprises a low sub-threshold voltage swing device, wherein an MOS transistor is connected in series with a voltage stabilizing diode at a source region to obtain a lower sub-critical swing (sub-threshold swing), so that the leakage current is reduced, and the power consumption is reduced.
The present invention also provides a method for manufacturing a semiconductor device, as shown in fig. 5, the method includes the following main steps:
step S801: providing a semiconductor substrate, and forming a gate structure on the semiconductor substrate;
step S802: performing first ion implantation to form first doping type heavily doped regions in the semiconductor substrate at two sides of the gate structure;
step S803: performing second ion implantation to form a first doping type lightly doped region in the semiconductor substrate of at least the source region, wherein the doping depth of the first doping type lightly doped region is greater than that of the first doping type heavily doped region, and the doping concentration of the first doping type lightly doped region is lower than that of the first doping type heavily doped region;
step S804: forming side walls on two sides of the grid structure;
step S805: a third ion implantation is performed to form a second doping type doped region in at least the first doping type lightly doped region of the source region.
Next, a detailed description will be given of a specific embodiment of a method for manufacturing a semiconductor device of the present invention.
First, step S801 is performed, as shown in fig. 1A, providing a semiconductor substrate 100 on which a gate structure 101 is formed.
Illustratively, the semiconductor substrate 100 may be at least one of the following materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. As an example, the constituent material of the semiconductor substrate 100 is monocrystalline silicon. An isolation structure is also formed in the semiconductor substrate 100, and the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, and divides the semiconductor substrate 100 into different active regions, in which various semiconductor devices can be formed.
A well (well) is also formed in the semiconductor substrate 100. Illustratively, when the semiconductor substrate is an N-type substrate, a P-well is formed in the N-type substrate, specifically, a P-well window is formed on the N-type substrate first, ion implantation is performed in the P-well window, and then an annealing step is performed to form the P-well. When the substrate is a P-type substrate, an N well is formed in the P-type substrate, specifically, an N well window is formed on the P-type substrate firstly, ion implantation is performed in the N well window, and then an annealing step is performed to form the N well. As an example, the semiconductor substrate 100 is an N-type substrate, and specifically, an N-type substrate commonly used in the art may be selected by a person skilled in the art, and then a P-well is formed in the semiconductor substrate 100.
Next, as shown in fig. 1A, a gate structure 101 is formed on the semiconductor substrate 100, and the gate structure 101 may include a gate dielectric layer 1011 and a gate material layer 1012 sequentially stacked from bottom to top.
Illustratively, the gate dielectric layer 1011 may include an oxide layer, such as silicon dioxide (SiO) 2 ) A layer. The gate dielectric layer 1011 may be formed by an oxidation process known to those skilled in the art, such as Furnace oxidation (burn oxide), rapid thermal annealing (RTO), in-situ steam oxidation (ISSG), and the like.
Illustratively, the gate material layer 1012 may include one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer, wherein the metal layer may be composed of tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride layer may include a titanium nitride (TiN) layer; the conductive metal oxide layer may include iridium oxide (IrO) 2 ) A layer; the metal silicide layer may include a titanium silicide (TiSi) layer. The gate material layer 1012 may be formed by one of Molecular Beam Epitaxy (MBE), metal Organic Chemical Vapor Deposition (MOCVD), low Pressure Chemical Vapor Deposition (LPCVD), laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG). As an example, the gate material layer 1012 is a polysilicon layer, and specifically, the reaction gas may include hydrogen (H) gas 2 ) Entrained silicon tetrachloride (SiCl) 4 ) Or trichlorosilane (SiHCl) 3 ) Silane (SiH) 4 ) And dichlorosilane (SiH) 2 Cl 2 ) And the like, and performing high-temperature chemical reaction in the reaction chamber to reduce or thermally decompose the silicon-containing reaction gas, wherein the generated silicon atoms are epitaxially grown on the surface of the tunneling oxide layer.
Next, step S802 is performed, as shown in fig. 1B, a first ion implantation is performed to form a first doping type heavily doped region 1001 in the semiconductor substrate 100 at two sides of the gate structure 101.
Illustratively, the first doping type is N-type doping, or the first doping type is P-type doping, specifically, as ions or P ions are selected As doping ions for the N-type doping, and B ions or In ions are selected As doping ions or P ions for the P-type doping. As one example, the first doping type is N-type doping.
In this embodiment, ion implantation is performed on the semiconductor substrate 100 of the source region and the drain region, the implanted ions are As or P, so As to form a first doping type heavily doped region 1001 in the source region and the drain region, wherein the implantation angle of the first ion implantation is 0 to 35 °, the energy of the ion implantation is 1keV to 100keV, and the dose of the ion implantation is greater than 1E14atom/cm 2 。
Next, step S803 is performed to perform a second ion implantation to form a first doping type lightly doped region 1002 in the semiconductor substrate 100 of the source region as shown in fig. 1C, or to form the first doping type lightly doped region 1002 in the semiconductor substrate 100 of the source and drain regions as shown in fig. 3. Wherein, the doping concentration of the first doping type lightly doped region 1002 is lower than that of the first doping type heavily doped region 1001, and the doping depth of the first doping type lightly doped region 1002 is greater than that of the first doping type heavily doped region 1001.
Illustratively, the first doping type is N-type doping, or the first doping type is P-type doping, specifically, as ions or P ions are selected As doping ions for the N-type doping, and B ions or In ions are selected As doping ions or P ions for the P-type doping. As one example, the first doping type is N-type doping.
Illustratively, the second ion implantation may employ LDD ion implantation to form a first doping type lightly doped region 1002 at least in the source region. Specifically, the implantation angle of the second ion implantation is 0-35 degrees, the energy of the ion implantation is 10-500 keV, and the dose of the ion implantation is 0.8E12atom/cm 2 ～1.2E13atom/cm 2 Preferably 1E13atom/cm 2 Of the first doping typeThe doping concentration of the type lightly doped region 1002 is lower than that of the first type heavily doped region 1001, and the doping depth of the first type lightly doped region 1002 is greater than that of the first type heavily doped region 1001.
Next, step S804 is executed, as shown in fig. 1D, sidewalls 102 are formed on two sides of the gate structure 101.
Illustratively, first, sidewall material layers are formed on two sides of the gate structure 101, and then the sidewall material layers are etched by using an anisotropic etching process, so as to form sidewalls 102 on two sides of the gate structure 101. The side wall material can be one of silicon oxide, silicon nitride and silicon oxynitride or a combination thereof. As an example, the side wall is composed of silicon oxide and silicon nitride, and the specific process is as follows: firstly, forming a second silicon oxide layer, a second silicon nitride layer and a third silicon oxide layer on a semiconductor substrate 100, specifically, depositing to form the silicon oxide layer and the silicon nitride layer by adopting a heat treatment process or a chemical vapor deposition process, wherein the reaction temperature of the chemical vapor deposition process is 500-800 ℃, and the reaction time is 10 minutes-10 hours; an etching process is then performed to form the sidewall, in particular, the sidewall is etched using a dry etch, which can use an anisotropic etch based on carbon fluoride gas, or a wet etch, which can use a hydrofluoric acid solution, such as a buffered oxide etchant or a hydrofluoric acid buffer solution. The sidewall 102 may have various thicknesses, and as an example, the thickness of the sidewall is 5nm to 200nm.
Next, as shown in fig. 1E, a third ion implantation is performed to form a second doping type doped region 1003 in the first doping type heavily doped region 1001 of the source region.
Illustratively, the second doping type is P-type doping, or the second doping type is N-type doping, specifically, as ions or P ions are selected As doping ions for the N-type doping, and B ions or In ions are selected As doping ions or P ions for the P-type doping. As one example, the second doping type doping is a P-type doping.
Illustratively, a third ion implantation is performed on the semiconductor substrate toA second doping type doped region 1003 is formed at least within the second doping type lightly doped region 1002 of the source region. Specifically, the implantation angle of the third ion implantation is 0-15 degrees, the energy of the ion implantation is 1 keV-100 keV, and the dose of the ion implantation is more than 1E14atom/cm 2 The doping concentration of the second doping type doping region 1003 is formed to be higher than the doping concentration of the first doping type heavily doped region 1001.
Illustratively, in the semiconductor device provided by the present invention, the relative position relationship between the first doping type heavily doped region 1001 and the second doping type heavily doped region 1003 includes that the second doping type doped region 1003 is located in the first doping type heavily doped region 1001, as shown in fig. 1E, that is, a PN junction formed by the second doping type doped region 1003 and the first doping type heavily doped region 1001 is a vertical structure.
It should be noted that the relative position relationship between the first doping type heavily doped region 1001 and the second doping type heavily doped region 1003 formed by the method of the present invention is not limited to the above case, and may further include that the first doping type heavily doped region 1002 and the second doping type heavily doped region 1003 are adjacently disposed, as shown in fig. 2, that is, a PN junction formed by the second doping type doping 1003 and the first doping type heavily doped region 1001 is a horizontal structure.
In addition, according to another manufacturing method provided by the present invention, as shown in fig. 4, a third ion implantation is performed to form a second doping type doped region 1003 in the first doping type heavily doped region 1001 of the source region and the drain region, and the formed structure includes: the second doping type doped 1003 region in the source region and the drain region is located in the first doping type heavily doped region 1001, as shown in fig. 4; or the second doping type doped 1003 region in the source region and the drain region is arranged adjacent to the first doping type heavily doped region 1001, as shown in fig. 5; or the second doping type doped 1003 region in the source region is located in the first doping type heavily doped region 1001, and the second doping type doped 1003 region in the drain region is arranged adjacent to the first doping type heavily doped region 1001, as shown in fig. 6; or the second doping type doped 1003 region in the source region is arranged adjacent to the first doping type heavily doped region 1001, and the second doping type doped 1003 region in the drain region is positioned in the first doping type heavily doped region 1001, as shown in fig. 7.
According to the semiconductor device provided by the invention, the semiconductor substrate is at least provided with the first doping type lightly doped region in the source region, and the first doping type heavily doped region and the second doping type doped region which are positioned in the first doping type lightly doped region. The semiconductor device has lower subcritical swing amplitude, is communicated when the reverse bias voltage exceeds the threshold voltage, and has very small leakage current when the reverse bias voltage is lower, so that the leakage current is reduced, and the power consumption is reduced.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, all of which fall within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (13)
1. A semiconductor device, comprising:
the semiconductor device comprises a semiconductor substrate, a grid structure is formed on the semiconductor substrate, and a source electrode area and a drain electrode area are formed in the semiconductor substrate on two sides of the grid structure;
at least a first doping type lightly doped region, a first doping type heavily doped region and a second doping type doped region are formed in the source region;
the first doping type heavily doped region and the second doping type doping region are arranged adjacently, or the second doping type doping region is positioned in the first doping type heavily doped region, and the first doping type heavily doped region and the second doping type doping region form a voltage stabilizing diode.
2. The device of claim 1, in which the first doping type doping comprises an N-type doping and the second doping type doping comprises a P-type doping; or,
the first doping type doping comprises P-type doping and the second doping type doping comprises N-type doping;
wherein the P-type doped ions comprise B ions or In ions, and the N-type doped ions comprise P ions or As ions.
3. The device of claim 1, wherein a doping concentration of the second doping type doped region is higher than a doping concentration of the first doping type heavily doped region.
4. The device of claim 1, wherein the heavily doped region of the first doping type has a doping concentration greater than 1E14atom/cm 2 。
5. The device of claim 1, wherein the first doping type lightly doped region has a doping concentration of 8E12atom/cm 2 -1.2E13atom/cm 2 。
6. The device of claim 1, wherein the semiconductor device comprises a low sub-threshold voltage swing device.
7. A method for manufacturing a semiconductor device is characterized by comprising the following steps:
providing a semiconductor substrate, and forming a gate structure on the semiconductor substrate;
performing first ion implantation to form first doping type heavily doped regions in the semiconductor substrate at two sides of the gate structure;
performing second ion implantation to form a first doping type lightly doped region in the semiconductor substrate of at least the source region, wherein the doping depth of the first doping type lightly doped region is greater than that of the first doping type heavily doped region, and the doping concentration of the first doping type lightly doped region is lower than that of the first doping type heavily doped region;
forming side walls on two sides of the grid structure;
performing a third ion implantation to form a second doping type doping region in at least the first doping type lightly doped region of the source region;
the first doping type heavily doped region and the second doping type doping region are arranged adjacently, or the second doping type doping region is positioned in the first doping type heavily doped region, and the first doping type heavily doped region and the second doping type doping region form a voltage stabilizing diode.
8. The method of claim 7, wherein the first doping type doping comprises an N-type doping and the second doping type doping comprises a P-type doping; or,
the first doping type doping comprises P-type doping and the second doping type doping comprises N-type doping;
wherein the P-type doped ions comprise B ions or In ions, and the N-type doped ions comprise P ions or As ions.
9. The method of claim 7 wherein said second ion implantation is LDD ion implantation.
10. The method of claim 7, wherein the second doping type doped region has a higher doping concentration than the first doping type heavily doped region.
11. The method of claim 7, wherein the first heavily doped region has a doping concentration greater than 1E14atom/cm 2 。
12. The method of claim 7The manufacturing method is characterized in that the doping concentration of the first doping type light doping area is 8E12atom/cm 2 -1.2E13atom/cm 2 。
13. The method of manufacturing of claim 7, wherein the semiconductor device comprises a low sub-threshold voltage swing device.
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| US20010035557A1 (en) * | 1996-05-15 | 2001-11-01 | Park Young-Hoon | Methods for fabricating CMOS integrated circuits including a source/drain plug |
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