CN109712972A - A kind of domain structure of overvoltage protection chip - Google Patents
A kind of domain structure of overvoltage protection chip Download PDFInfo
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- CN109712972A CN109712972A CN201811261572.XA CN201811261572A CN109712972A CN 109712972 A CN109712972 A CN 109712972A CN 201811261572 A CN201811261572 A CN 201811261572A CN 109712972 A CN109712972 A CN 109712972A
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- 238000006243 chemical reaction Methods 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 3
- 238000009510 drug design Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 3
- 230000003750 conditioning effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000002452 interceptive effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 125000002619 bicyclic group Chemical group 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
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Abstract
The invention discloses a kind of domain structure of overvoltage protection chip, including the first layout area, the second layout area, third layout area, fourth edition graph region, the 5th layout area, sixth version graph regions.A kind of domain structure of overvoltage protection chip of the invention is fully considering in module; it the matched design of intermodule and interchannel and interferes with each other; under the premise of influence and Temperature Distribution of the digital circuit blocks to analog module influence each module; pass through the rational design of rational deployment and each domain area to chip layout; preferably realize the circuit function of overvoltage protection chip; so that the chip power-consumption that design obtains is low; internal resistance is small; the heat of generation is few; to be effectively saved space and the cost of circuit board, the service life of system is extended.
Description
Technical field
The invention belongs to chip layout topology fields, and in particular to a kind of domain structure of overvoltage protection chip.
Background technique
With the development of science and technology consumer electronics is universal, overvoltage protection (OVP) chip for protect subsequent conditioning circuit from
The destruction of instantaneous pressure, the service life for extending equipment have positive effect.Therefore the invention patent is intended to take into account OVP
Under the premise of energy, reasonable distribution signal path optimizes laying out pattern, so that laying out pattern has minimum area, it is whole system
Cost and space are saved.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, a kind of domain knot of overvoltage protection chip is provided
Structure, under the premise of taking into account OVP performance, reasonable distribution signal path optimizes laying out pattern, reduces chip cost.
To achieve the above object, domain structure provided by the invention, which is characterized in that including the first layout area, second
Layout area, third layout area, fourth edition graph region, the 5th layout area, sixth version graph region, first layout area
Respective modules (1) are located at the lower half portion of domain, and the second layout area respective modules (2) are located at the left side middle part of domain
Point, the third layout area respective modules (3) are located at the middle section of domain, the fourth edition graph region respective modules (4)
Positioned at the upper right portion of domain, the 5th layout area respective modules (5) are located at the upper middle portion of domain, and the described 6th
Layout area respective modules (6) are located at the upper left of domain.
First layout area is POWERMOS domain area, is subsequent power supply for generating output.
Second layout area is charge pump domain area, for generating the control voltage of N-type POWERMOS pipe.
The third layout area is high-low pressure conversion interface circuit domain area, is isolated using p-type trap ring while avoiding height
The inversion regime that pressure metal wire is generated in place.
The fourth edition graph region is benchmark circuit layout area, for generating other each region required voltages, electric current letter
Number.
5th layout area be it is enabled, trim circuit layout area, for generating enable signal, and place and trim electricity
Resistance.
The sixth version graph region is OVLO circuit layout area, for judging whether OVLO voltage is more than setting voltage, such as
More than powermos output is then turned off, the basic function of chip overvoltage protection is realized.
It can be seen that the domain structure of overvoltage protection chip of the invention is fully considering in module, intermodule and channel
Between interfere with each other and under the premise of Temperature Distribution influences each module, by the rational deployment of the domain structure to chip and
The rational design in each domain area, preferably realizes the circuit function of overvoltage protection chip, so that the chip power-consumption that design obtains
It is lower, internal resistance it is smaller and generate heat it is less, to be effectively saved circuit board space and cost.
Detailed description of the invention
Fig. 1 is the circuit structure block diagram of this OVP chip.
Fig. 2 is a kind of structural schematic diagram of the domain structure of overvoltage protection chip of the invention.
Fig. 3 is a kind of placement-and-routing's example of the first layout area of the domain structure of overvoltage protection chip of the invention
Figure.
Fig. 4 is a kind of placement-and-routing's example of the second layout area of the domain structure of overvoltage protection chip of the invention
Figure.
Fig. 5 is a kind of placement-and-routing's example of the third layout area of the domain structure of overvoltage protection chip of the invention
Figure.
Fig. 6 is a kind of placement-and-routing's example of the fourth edition graph region of the domain structure of overvoltage protection chip of the invention
Figure.
Fig. 7 is a kind of placement-and-routing's example of the 5th layout area of the domain structure of overvoltage protection chip of the invention
Figure.
Fig. 8 is a kind of placement-and-routing's example of the sixth version graph region of the domain structure of overvoltage protection chip of the invention
Figure.
Specific embodiment
Below with reference to attached drawing to design of the invention, the technical effect of specific structure and generation is described further, with
Adequately understand the purpose of the present invention, feature and effect.
This OVP chip structure is illustrated in fig. 1 shown below, after built-in N-type powermos switch (1) connection input power is with output
Continuous circuit power supply, ChargePump (2) module provide the control voltage higher than input power, HVtoLV (3) module for N-type switch
The power input of low pressure is provided for the conversion of chip interior each unit, BG (4) module provides bias voltage for chip interior each unit
Electric current, EN+trim (5) module provide various enable signals and trim unit, and comparator detecting is external built in OVLO (6) module
OVLO signal turns off output if being higher than threshold voltage, realizes the basic function of chip.
As illustrated in figs. 2 through 8, the domain structure of overvoltage protection chip of the present invention, including the first layout area, the second edition
Graph region, third layout area, fourth edition graph region, the 5th layout area, sixth version graph region, first layout area pair
Module (1) is answered to be located at the lower half portion of domain, the second layout area respective modules (2) are located at the left side middle part of domain
Point, the third layout area respective modules (3) are located at the middle section of domain, the fourth edition graph region respective modules (4)
Positioned at the upper right portion of domain, the 5th layout area respective modules (5) are located at the upper middle portion of domain, and the described 6th
Layout area respective modules (6) are located at the upper left of domain.
First layout area 1 is POWERMOS domain area, for generating output, is powered for subsequent conditioning circuit, this module occupies
Chip major part area, the cell layout provided technique are optimized, and make it have that area is smaller, and integrated level is high, electricity
The effects of levelling is equal.
Second layout area 2 is charge pump domain area, and the control voltage for generating N-type POWERMOS pipe (is higher than power supply
Input voltage).To avoid interfering, the contact of N-type trap inner ring is used to the module domain plus p-type is grounded the bicyclic isolation noise of trap
Measure.
Third layout area 3 is high-low pressure conversion interface circuit domain area, provides low pressure for the conversion of chip interior each unit
Power input, be isolated using p-type trap ring while the measure of the inversion regime that avoids high-pressure metal line from generating in place.
Fourth edition graph region 4 is benchmark circuit layout area, bias voltage electric current is provided for chip interior each unit, using P
Type is grounded the isolation of trap ring, and the shielding line being grounded is centered around reference signal line both sides and is arranged to avoid it by other signal interferences etc.
It applies.
5th layout area 5 is to enable, trim circuit layout area, for generating enable signal, and places and trims resistance.
Sixth version graph region 6 is OVLO circuit layout area, and built-in comparator detects external OVLO signal, for judging whether
More than setting voltage, output is turned off if being higher than setting voltage, realizes the basic function of chip overvoltage protection.To comparator pair
The Primary Components such as pipe use reasonable matching, the measures such as surrounding plus ring isolation.
By measures such as above-mentioned laying out pattern and reasonable Isolated Shields, can reduce in overvoltage protection chip of the invention
The influence of interfering with each other between module and heat distribution to modules makes to ensure that the realization of chip circuit function
It is with excellent performance.
Claims (7)
1. a kind of domain structure of overvoltage protection chip, which is characterized in that including the first layout area, the second layout area,
Three layout areas, fourth edition graph region, the 5th layout area, sixth version graph region, first layout area are located at domain
Lower half portion, second layout area are located at the left side middle section of domain, and the third layout area is located in domain
Between part, the fourth edition graph region is located at the upper right portion of domain, and the 5th layout area is located among the top of domain
Part, the sixth version graph region are located at the upper left of domain.
2. the domain structure of overvoltage protection chip according to claim 1, which is characterized in that first layout area is
POWERMOS domain area, for generating output signal.
3. the domain structure of overvoltage protection chip according to claim 1, which is characterized in that second layout area is
Charge pump domain area, for generating the control voltage of N-type POWERMOS pipe, to the module domain using the measure of isolation noise.
4. the domain structure of overvoltage protection chip according to claim 1, which is characterized in that the third layout area is
High-low pressure conversion interface circuit domain area, the inversion regime for being isolated using p-type trap ring while high-pressure metal line being avoided to generate in place.
5. the domain structure of overvoltage protection chip according to claim 1, which is characterized in that the fourth edition graph region is
Reference circuit domain area, for generating the bias voltage current signal of other modules needs.
6. the domain structure of overvoltage protection chip according to claim 1, which is characterized in that the 5th layout area is
It is enabled, circuit layout area is trimmed, for generating enable signal, and places and trims resistance.
7. the domain structure of overvoltage protection chip according to claim 1, which is characterized in that the sixth version graph region is
OVLO circuit layout area, for judging whether OVLO voltage is more than setting voltage.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711017408 | 2017-10-26 | ||
| CN201711017408X | 2017-10-26 |
Publications (2)
| Publication Number | Publication Date |
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| CN109712972A true CN109712972A (en) | 2019-05-03 |
| CN109712972B CN109712972B (en) | 2024-06-04 |
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| CN201811261572.XA Active CN109712972B (en) | 2017-10-26 | 2018-10-26 | Layout structure of overvoltage protection chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112115672A (en) * | 2020-09-15 | 2020-12-22 | 中国兵器工业集团第二一四研究所苏州研发中心 | Layout structure of high-voltage multiplexer chip |
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| JP2006133835A (en) * | 2004-11-02 | 2006-05-25 | Seiko Epson Corp | Layout design system and method for semiconductor integrated circuit |
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| CN112115672A (en) * | 2020-09-15 | 2020-12-22 | 中国兵器工业集团第二一四研究所苏州研发中心 | Layout structure of high-voltage multiplexer chip |
| CN112115672B (en) * | 2020-09-15 | 2024-01-26 | 中国兵器工业集团第二一四研究所苏州研发中心 | Layout structure of high-voltage multiplexer chip |
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|---|---|
| CN109712972B (en) | 2024-06-04 |
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Address after: 200083 806, floor 8, No. 125, Liuying Road, Hongkou District, Shanghai Applicant after: Shanghai Wei'an Electronic Co.,Ltd. Address before: 201202 Shanghai city Pudong New Area Town Road No. 1001 to seven Shiwan Applicant before: Shanghai Changyuan Wayon Circuit Protection Co.,Ltd. |
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Address after: Room 806, 8th floor, 125 Liuying Road, Hongkou District, Shanghai 200083 Applicant after: Shanghai Weian Electronics Co.,Ltd. Address before: 806, 8th floor, 125 Liuying Road, Hongkou District, Shanghai 200083 Applicant before: Shanghai Wei'an Electronic Co.,Ltd. |
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