CN109710193A - A kind of system and method controlling PWDIS signal in M.3 SSD - Google Patents
A kind of system and method controlling PWDIS signal in M.3 SSD Download PDFInfo
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- CN109710193A CN109710193A CN201811620042.XA CN201811620042A CN109710193A CN 109710193 A CN109710193 A CN 109710193A CN 201811620042 A CN201811620042 A CN 201811620042A CN 109710193 A CN109710193 A CN 109710193A
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Abstract
This application discloses a kind of system and methods of PWDIS signal in control M.3 SSD, the system includes: the first control module, the second control module or door, Switch chip and M.3 connector, or the input terminal of door is connect respectively with the first control module and the second control module or the output end of door passes sequentially through Switch chip and M.3 connector is connect with M.3 SSD.Method in the application includes: VPP signal of the parsing from CPU, and the first PWDIS signal of level is answered according to VPP signal output phase；The I2C signal from BMC is parsed, and answers the 2nd PWDIS signal of level according to I2C signal output phase；To the first PWDIS signal and the 2nd PWDIS signal carries out or operation, obtains PWDIS signal；PWDIS signal is transmitted to M.3 SSD via Switch chip and M.3 connector.By the application, the application scenarios of M.3 SSD can be extended, improve the ease for maintenance of M.3 SSD.
Description
Technical field
This application involves M.3 SSD (Solid State Drives, solid state hard disk) signal control technology fields, especially
It is related to a kind of system and method for controlling PWDIS signal in M.3 SSD.
Background technique
M.3 usually there are two groups of power supplys: 12V and 3V3_AUX in SSD.Wherein, 12V is the main power source of M.3 SSD, mainly
The operation such as read-write for M.3 SSD；3V3_AUX is mainly used for supporting the sideband signals module inside M.3 SSD.When 12V stops
When only powering, M.3 SSD in a dormant state when, system still can by SMBus read M.3 the capacity of SSD, temperature and
Other information.
For the working condition for describing two groups of power supplys in M.3 SSD, M.3 definition has PWDIS (Power in SSD interface
Disable, power-off) signal.This signal high level is effective, and when this signal is high level, M.3 the 12V power supply of SSD can be stopped
Fall, power relevant function of 12V enters dormant state, the no longer read-write requests of response system, and 3V3_AUX powers relevant function
It can operate normally.Therefore, the PWDIS signal in M.3 SSD is controlled, is that one in M.3 SSD developmental research is important
Problem.
Currently, being generally only to keep PWDIS signal to PWDIS signal in M.3 SSD there is no mature control program
It drags down, descends electricity extremely to avoid M.3 SSD.
However, at present in the control method of PWDIS signal, since only the holding of PWDIS signal being dragged down, control method
It is single, it is unfavorable for extending the application scenarios of M.3 SSD, so that M.3 the application scenarios of SSD are less.
Summary of the invention
It is right in the prior art to solve this application provides a kind of system and method for PWDIS signal in control M.3 SSD
The control method of PWDIS signal is single, is unfavorable for the problem of extending the M.3 application scenarios of SSD.
In order to solve the above-mentioned technical problem, the embodiment of the present application discloses following technical solution:
A kind of system controlling PWDIS signal in M.3 SSD, the system comprises: the first control module, the second control mould
Block or door, Switch (switch) chip and M.3 connector, described or door input terminal respectively with the first control module and
The connection of two control modules, described or door output end passes sequentially through the Switch chip and M.3 connector connects with M.3 SSD
It connects；
First control module answers level according to the VPP signal output phase for parsing the VPP signal from CPU
The first PWDIS signal, and according to the information in place of M.3 SSD control Switch chip on-off；
Second control module comes from BMC (Baseboard Management Controller, substrate for parsing
Management Controller) I2C (Inter-Integrated Circuit, IC bus, for connect microcontroller and its
Peripheral equipment) signal, answer the 2nd PWDIS signal of level according to the I2C signal output phase, and by the in place of M.3 SSD
Information is transmitted to BMC；
Described or door, for obtaining PWDIS letter for the first PWDIS signal and the progress of the 2nd PWDIS signal or operation
Number.
Optionally, first control module is that (Complex Programmable Logic Device is answered a CPLD
Miscellaneous programmable logic device), second control module is an I2C extended chip.
Optionally, the I2C extended chip is PCA9555 chip.
Optionally, further include a pull down resistor in the system, the pull down resistor be set to the Switch chip with
M.3 on the signal wire between connector.
A method of controlling PWDIS signal in M.3 SSD, which comprises
The VPP signal from CPU is parsed using CPLD, and answers the first PWDIS of level according to the VPP signal output phase
Signal；
The I2C signal from BMC is parsed using I2C extended chip, and answers the of level according to the I2C signal output phase
Two PWDIS signals；
To the first PWDIS signal and the 2nd PWDIS signal carries out or operation, obtains PWDIS signal；
The PWDIS signal is transmitted to M.3 SSD via Switch chip and M.3 connector.
Optionally, described to parse the VPP signal from CPU using CPLD, and level is answered according to the VPP signal output phase
The first PWDIS signal, comprising:
CPLD obtains the VPP signal from CPU；
When the PWREN#bit in VPP signal is low level, CPLD exports low level first PWDIS signal；
When the PWREN#bit in VPP signal is high level, CPLD exports the first PWDIS signal of high level.
Optionally, described to parse the I2C signal from BMC using I2C extended chip, and exported according to the I2C signal
2nd PWDIS signal of corresponding level, comprising:
I2C extended chip obtains the I2C signal from BMC；
When controlling bit electric under M.3 SSD in I2C signal is high level, I2C extended chip exports the second of high level
PWDIS signal；
When controlling bit electric under M.3 SSD in I2C signal is low level, I2C extended chip output low level second
PWDIS signal.
Optionally, the method also includes:
It detects the M.3 information in place of SSD and returns to BMC and CPU respectively；
The on-off of Switch chip is controlled according to the information in place of M.3 SSD.
It is optionally, described to detect the M.3 information in place of SSD and return to CPU and BMC respectively, comprising:
CPLD obtains the information in place of M.3 SSD, and by the information back in place of the M.3 SSD acquired in it to CPU；
I2C extended chip obtains the information in place of M.3 SSD, and by the information back in place of the M.3 SSD acquired in it
To BMC.
Optionally, the basis M.3 SSD information in place control Switch chip on-off, comprising:
When the detection signal in place of M.3 SSD is high level, CPLD controls Switch chip and disconnects；
When the detection signal in place of M.3 SSD is low level, CPLD controls Switch chip and connects.
The technical solution that embodiments herein provides can include the following benefits:
The application provides a kind of system for controlling PWDIS signal in M.3 SSD, which specifically includes that the first control mould
Block, the second control module or door, Switch chip and M.3 five part of connector, and or door input terminal respectively with the first control
The output end of molding block and the connection of the second control module or door passes sequentially through Switch chip and M.3 connector and M.3 SSD phase
Even.The VPP signal from CPU is parsed by the first control module, and according to the PWREN#bit output first in VPP signal
PWDIS signal gives or door, controls to realize the proximal end of PWDIS signal in M.3 SSD.By the second control module parse come
From the I2C signal of BMC, and according to I2C signal output phase answer the 2nd PWDIS signal of level to or door, thus realize to M.3
It is existing without going can to carry out remote control when M.3 SSD breaks down to it for the remote control of PWDIS signal in SSD
, and then improve the ease for maintenance of M.3 SSD.Due to the first control module and second mouthful of control module with or door connect, CPU
Or when either party electricity order lower to M.3 SSD sending of BMC, M.3 SSD is carried out lower electricity, is conducive to improve to PWDIS signal
The flexibility of control and the application scenarios for extending M.3 SSD.
The first control module is also used to control the logical of Switch chip according to the information in place of M.3 SSD in the present embodiment
It is disconnected, so that it is guaranteed that PWDIS signal can be just transmitted to M.3 SSD only when M.3 SSD is in place, and then realize M.3 SSD's
Hot plug is conducive to the application scenarios for extending M.3 SSD.The second control module is also used to exist M.3 SSD in the present embodiment
Position information is transmitted to BMC, obtains the information in place of M.3 SSD in time at the end BMC to realize, is conducive to improve to M.3 SSD
The accuracy of middle PWDIS signal remote control.
The application also provides a kind of method for controlling PWDIS signal in M.3 SSD, and this method is utilized respectively CPLD parsing and comes
From the VPP signal of CPU, and answer according to VPP signal output phase the first PWDIS signal of level, using I2C extended chip parse come
From the I2C signal of BMC, and answer according to I2C signal output phase the 2nd PWDIS signal of level；Then to the first PWDIS signal and
2nd PWDIS signal carries out or operation, obtains PWDIS signal；M.3 last PWDIS signal is transmitted to via Switch chip
SSD.The present embodiment parses the VPP signal from CPU by CPLD, can be realized to PWDIS signal in M.3 SSD
Proximal end control；The I2C signal from BMC is parsed by I2C extended chip, can be realized and PWDIS in M.3 SSD is believed
Number remote control, therefore, the method in the present embodiment can extend the application scenarios of M.3 SSD, and remote control can be non-
Remote control M.3 electricity under SSD is often conveniently realized, provides very big convenience for the maintenance of M.3 SSD.
Method in the present embodiment further includes according to the on-off of the information in place control Switch chip of M.3 SSD, only
When M.3 SSD is in place, PWDIS signal can be just transmitted to M.3 SSD, to realize the hot plug of M.3 SSD, be conducive to expand
The application scenarios of M.3 SSD are opened up, and to the convenience that M.3 SSD is safeguarded.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The application can be limited.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the application
Example, and together with specification it is used to explain the principle of the application.
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, for those of ordinary skill in the art
Speech, without creative efforts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of structural representation for controlling the system of PWDIS signal in M.3 SSD provided by the embodiment of the present application
Figure；
Fig. 2 is the control principle schematic diagram in the embodiment of the present application to PWDIS signal in M.3 SSD；
Fig. 3 is a kind of process signal for controlling the method for PWDIS signal in M.3 SSD provided by the embodiment of the present application
Figure.
Specific embodiment
In order to make those skilled in the art better understand the technical solutions in the application, below in conjunction with the application reality
The attached drawing in example is applied, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described implementation
Example is merely a part but not all of the embodiments of the present application.Based on the embodiment in the application, this field is common
The application protection all should belong in technical staff's every other embodiment obtained without making creative work
Range.
The application in order to better understand explains in detail presently filed embodiment with reference to the accompanying drawing.
Embodiment one
Referring to Fig. 1, Fig. 1 is a kind of knot for controlling the system of PWDIS signal in M.3 SSD provided by the embodiment of the present application
Structure schematic diagram.As shown in Figure 1, the present embodiment control M.3 in SSD the system of PWDIS signal specifically include that the first control module,
Second control module or door and Switch chip and M.3 connector,.Or the input terminal of door respectively with the first control module
Connected with the second control module or the output end of door pass sequentially through the Switch chip and M.3 connector, be connected to M.3
The M.3 connector of SSD is connected.
Wherein, the first control module is for parsing the VPP signal from CPU, answers the of level according to VPP signal output phase
One PWDIS signal, and the on-off according to the information in place of M.3 SSD control Switch chip.
The first control module is realized using a CPLD in the present embodiment.Specifically, using CPLD to the VPP from CPU
Signal is parsed, and the first PWDIS signal of level, that is, basis are answered according to the PWREN#bit output phase in VPP signal
PWREN#bit level states determine the level state of the first PWDIS signal in VPP data, and export the first PWDIS letter
Number.When PWREN#bit is low, the first PWDIS signal of control CPLD output is low level, when PWREN#bit is high, control
First PWDIS signal of CPLD output processed is high level.
Second control module answers the second of level according to I2C signal output phase for parsing the I2C signal from BMC
PWDIS signal, and the information in place of M.3 SSD is transmitted to BMC.
The second control module is realized using an I2C extended chip in the present embodiment, I2C extended chip i.e.: I2C
Expander chip.Specifically, the I2C signal from BMC is parsed using I2C extended chip, is controlled according in I2C signal
The position bit of M.3 SSD power-on and power-off is made, the level state of the 2nd exported PWDIS signal is controlled.When need will M.3 SSD by BMC
When, it may be assumed that controlled in I2C signal the position bit electric under M.3 SSD be high level when, I2C extended chip export high level second
PWDIS signal；Remaining situation I2C extended chip exports low level 2nd PWDIS signal.I2C extended chip in the present embodiment
The information in place of M.3 SSD can also be obtained in real time, and by acquired information back in place to BMC, M.3 for the end BMC
The status display in place of SSD.
Further, in this embodiment I2C extended chip can be realized using PCA9555 chip.
The setting of first control module can be realized the proximal end control to PWDIS signal in M.3 SSD；Second control mould
The setting of block can be realized the remote control to PWDIS signal in M.3 SSD, therefore, in the present embodiment control in M.3 SSD
The system of PWDIS signal is conducive to extend the application scenarios of M.3 SSD.Such as: when detecting M.3 SSD abnormal state or damage
When, staff need not arrive computer room scene, only need to be by network remote closing fault M.3 SSD, to prevent M.3 SSD
Continue power consumption, is conducive to the ease for maintenance for improving M.3 SSD.
With continued reference to Fig. 1 it is found that further including in the system of the present embodiment or door, for by the first PWDIS signal and second
PWDIS signal carries out or operation, obtains PWDIS signal.
The first PWDIS signal from CPLD and the 2nd PWDIS signal from I2C extended chip, by or door operation
After be given to Switch chip, when the either signal in the first PWDIS signal and the 2nd PWDIS signal is high level or door, that is, defeated
The PWDIS signal of high level out.As long as there is one to issue instruction electric under control SSD in i.e. CPU and BMC, M.3 SSD stops
Power supply, therefore, this structure setting is conducive to improve the flexibility for controlling PWDIS signal in M.3 SSD.
The present embodiment can also utilize the on-off of CPLD control Switch chip by the information in place according to M.3 SSD.
Specifically, when CPLD detects that the detection signal in place of M.3 SSD is high level, determine that M.3 SSD is not in place, CPLD control
Switch chip disconnects, and the output end of door and is M.3 in an off state at this time or between connector, PWDIS signal cannot be passed through
M.3 SSD is transmitted to by M.3 connector；When the detection signal in place for detecting M.3 SSD is low level, M.3 SSD is determined
In place, CPLD controls Switch chip and connects, and the output end of door and is M.3 at this time or between connector connected state, can be with
PWDIS signal is transmitted to M.3 SSD via M.3 connector.Therefore, it by the setting of the first control module, can be realized M.3
The hot plug of SSD is conducive to further expand the application scenarios of M.3 SSD.
In addition, connecting in the present embodiment or the output end of door passes sequentially through Switch chip and M.3 connector with M.3 SSD
It connects.Namely or the PWDIS signal of door output is after Switch chip, is just transmitted to M.3 SSD via M.3 connector.By
In M.3 SSD be inserted into server during, may result in PWDIS signal generate burr phenomena, the setting of Switch chip,
The burr phenomena of PWDIS signal can be greatly reduced, to avoid M.3 SSD generation abnormal, be conducive to improve M.3 SSD and run
Stability.
Further, the system that the present embodiment controls PWDIS signal in M.3 SSD further includes a pull down resistor, the drop-down
Resistance is set on Switch chip and the M.3 signal wire between connector.That is: one end of pull down resistor and M.3 SSD's is defeated
Enter end connection, the other end ground connection of pull down resistor.The setting of pull down resistor, so that the PWDIS signal for being given to M.3 SSD is defaulted as
Low level, it may be assumed that M.3 SSD default powers on, so as to avoid or door and Switch the chip I/O in power up initialization process
It is uncontrollable to lead to M.3 SSD abnormal electrical power supply, be conducive to improve the stability of M.3 SSD operation.
Fig. 2 is the control principle schematic diagram in the present embodiment to PWDIS signal in M.3 SSD.With the first control mould in Fig. 2
Block is described for using CPLD, the second control module to use BMC.As shown in Figure 2, CPLD gets the letter of the VPP from CPU
Number generating the first PWDIS signal, I2C extended chip gets the I2C signal from BMC and generates the 2nd PWDIS signal, and first
PWDIS signal and the 2nd PWDIS signal are connected to or the output end of the input terminal of door or door is sent to by Switch chip
M.3 connector, M.3 connector is connect with M.3 SSD, even the PWDIS signal of door output is eventually sent to M.3 SSD.CPLD
Signal also is sent to Switch chip, the on-off of Switch chip is controlled, to realize the hot plug of M.3 SSD.Separately
Outside, M.3 the output end of connector is connect with CPLD and I2C extended chip respectively, to realize the information in place inspection of M.3 SSD
It surveys.CPLD timely feedbacks the information in place of M.3 SSD to CPU, in order to which CPU controls M.3 SSD；I2C extends core
Piece timely feedbacks the information in place of M.3 SSD to BMC, in order to which in place state of the BMC to M.3 SSD is shown.This reality
It applies and is additionally provided with pull down resistor R1 in the system of example, the setting of pull down resistor R1, so that Switch chip is to between M.3 SSD
Signal dragged down by pull down resistor R1, thus guarantee PWDIS signal default conditions be low level.
Embodiment two
Referring to Fig. 3 on the basis of Fig. 1 and embodiment illustrated in fig. 2, Fig. 3 is a kind of control provided by the embodiment of the present application
Make the flow diagram of the method for PWDIS signal in M.3 SSD.
From the figure 3, it may be seen that the method that the present embodiment controls PWDIS signal in M.3 SSD, mainly comprises the following processes:
S1: the VPP signal from CPU is parsed using CPLD, and answers the first PWDIS of level according to VPP signal output phase
Signal.
Specifically, step S1 includes: again
S11:CPLD obtains the VPP signal from CPU.
S12: when the PWREN#bit in VPP signal is low level, CPLD exports low level first PWDIS signal.
S13: when the PWREN#bit in VPP signal is high level, CPLD exports the first PWDIS signal of high level.
By step S11-S13 it is found that PWREN#bit level states, control in the VPP signal that CPLD is issued according to CPU
Make the level state of the first PWDIS signal.
S2: the I2C signal from BMC is parsed using I2C extended chip, and answers the of level according to I2C signal output phase
Two PWDIS signals.
Specifically, step S2 includes: again
S21:I2C extended chip obtains the I2C signal from BMC.
S22: when controlling bit electric under M.3 SSD in I2C signal is high level, I2C extended chip exports high level
2nd PWDIS signal.
S23: when controlling bit electric under M.3 SSD in I2C signal is low level, the output of I2C extended chip is low level
2nd PWDIS signal.
By above step S21-S23 it is found that I2C extended chip is according to the bit for controlling M.3 SSD power-on and power-off in I2C signal
Position, to control the level state of the 2nd exported PWDIS signal.
S3: to the first PWDIS signal and the 2nd PWDIS signal carries out or operation, obtains PWDIS signal.
S4:PWDIS signal is transmitted to M.3 SSD via Switch chip.
Further, in this embodiment method further include:
S5: it detects the M.3 information in place of SSD and returns to BMC and CPU respectively.
Specifically, step S5 includes:
S51:CPLD obtains the information in place of M.3 SSD, and extremely by the information back in place of the M.3 SSD acquired in it
CPU。
S52:I2C extended chip obtains the information in place of M.3 SSD, and by the information in place of the M.3 SSD acquired in it
It is back to BMC.
S6: the on-off of Switch chip is controlled according to the information in place of M.3 SSD.
Specifically, step S6 includes:
S61: when the detection signal in place of M.3 SSD is high level, CPLD controls Switch chip and disconnects.
S62: when the detection signal in place of M.3 SSD is low level, CPLD controls Switch chip and connects.
The part being not described in detail in the embodiment may refer to Fig. 1 and embodiment shown in Fig. 2 two, two embodiments
Between can mutual reference, details are not described herein.
In conclusion the method that PWDIS signal in M.3 SSD is controlled in the present embodiment, by CPLD to from CPU's
VPP signal is parsed, and can be realized the proximal end control to PWDIS signal in M.3 SSD；By I2C extended chip to coming from
The I2C signal of BMC is parsed, and can be realized the remote control to PWDIS signal in M.3 SSD, therefore, through this embodiment
In method, guarantee M.3 SSD work normally under the premise of, can be realized M.3 SSD long-range lower electric tube reason and hot plug
Operation control so as to greatly expand the application scenarios of M.3 SSD, and is conducive to improve the ease for maintenance of M.3 SSD.
The above is only the specific embodiment of the application, is made skilled artisans appreciate that or realizing this Shen
Please.Various modifications to these embodiments will be apparent to one skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the application.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. a kind of system for controlling PWDIS signal in M.3 SSD, which is characterized in that the system comprises: the first control module,
Second control module or door, Switch chip and M.3 connector, described or door input terminal respectively with the first control module
It is connected with the second control module, described or door output end passes sequentially through the Switch chip and M.3 connector and M.3 SSD
Connection；
First control module answers the of level according to the VPP signal output phase for parsing the VPP signal from CPU
One PWDIS signal, and the on-off according to the information in place of M.3 SSD control Switch chip；
Second control module answers the of level according to the I2C signal output phase for parsing the I2C signal from BMC
Two PWDIS signals, and the information in place of M.3 SSD is transmitted to BMC；
Described or door, for obtaining PWDIS signal for the first PWDIS signal and the progress of the 2nd PWDIS signal or operation.
2. a kind of system for controlling PWDIS signal in M.3 SSD according to claim 1, which is characterized in that described first
Control module is a CPLD, and second control module is an I2C extended chip.
3. a kind of system for controlling PWDIS signal in M.3 SSD according to claim 2, which is characterized in that the I2C
Extended chip is PCA9555 chip.
4. a kind of system for controlling PWDIS signal in M.3 SSD according to claim 1 to 3, which is characterized in that
It further include a pull down resistor in the system, the pull down resistor is set to the Switch chip and M.3 between connector
On signal wire.
5. a kind of method for controlling PWDIS signal in M.3 SSD, which is characterized in that the described method includes:
The VPP signal from CPU is parsed using CPLD, and answers the first PWDIS of level to believe according to the VPP signal output phase
Number；
The I2C signal from BMC is parsed using I2C extended chip, and answers the second of level according to the I2C signal output phase
PWDIS signal；
To the first PWDIS signal and the 2nd PWDIS signal carries out or operation, obtains PWDIS signal；
The PWDIS signal is transmitted to M.3 SSD via Switch chip and M.3 connector.
6. a kind of method for controlling PWDIS signal in M.3 SSD according to claim 5, which is characterized in that the utilization
CPLD parses the VPP signal from CPU, and the first PWDIS signal of level is answered according to the VPP signal output phase, comprising:
CPLD obtains the VPP signal from CPU；
When the PWREN#bit in VPP signal is low level, CPLD exports low level first PWDIS signal；
When the PWREN#bit in VPP signal is high level, CPLD exports the first PWDIS signal of high level.
7. a kind of method for controlling PWDIS signal in M.3 SSD according to claim 5, which is characterized in that the utilization
I2C extended chip parses the I2C signal from BMC, and the 2nd PWDIS signal of level is answered according to the I2C signal output phase,
Include:
I2C extended chip obtains the I2C signal from BMC；
When controlling bit electric under M.3 SSD in I2C signal is high level, I2C extended chip exports the second of high level
PWDIS signal；
When controlling bit electric under M.3 SSD in I2C signal is low level, I2C extended chip output low level second
PWDIS signal.
8. according to the method for PWDIS signal in a kind of control any in claim 5-7 M.3 SSD, which is characterized in that
The method also includes:
It detects the M.3 information in place of SSD and returns to BMC and CPU respectively；
The on-off of Switch chip is controlled according to the information in place of M.3 SSD.
9. a kind of method for controlling PWDIS signal in M.3 SSD according to claim 8, which is characterized in that the detection
M.3 the information in place of SSD and CPU and BMC are returned to respectively, comprising:
CPLD obtains the information in place of M.3 SSD, and by the information back in place of the M.3 SSD acquired in it to CPU；
I2C extended chip obtains the information in place of M.3 SSD, and extremely by the information back in place of the M.3 SSD acquired in it
BMC。
10. a kind of method for controlling PWDIS signal in M.3 SSD according to claim 8, which is characterized in that described
According to the on-off of the information in place control Switch chip of M.3 SSD, comprising:
When the detection signal in place of M.3 SSD is high level, CPLD controls Switch chip and disconnects；
When the detection signal in place of M.3 SSD is low level, CPLD controls Switch chip and connects.
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