CN109698199A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109698199A CN109698199A CN201910002291.0A CN201910002291A CN109698199A CN 109698199 A CN109698199 A CN 109698199A CN 201910002291 A CN201910002291 A CN 201910002291A CN 109698199 A CN109698199 A CN 109698199A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The present invention relates to a kind of semiconductor structure and forming method thereof, the forming method of the semiconductor structure includes: offer substrate；It etches the substrate and forms the first figure, first figure has the first critical size；The first filled layer is formed in first figure, the first filling layer surface is lower than the substrate surface, fills first figure lower part；Form the adjustment layer for covering the first pattern side wall above first filled layer, second graph is formed between adjustment layer, the second graph bottom-exposed goes out the first filled layer of part, and the second graph has the second critical size, and second critical size is less than the first critical size；The second filled layer is filled in the second graph.The above method advantageously reduces the difficulty and cost for the size to form ultra-fine hole, improves reliability.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
In recent years, the development of flash memory (Flash Memory) memory is especially rapid.Flash memories are mainly characterized by
It can keep the information of storage for a long time in the case where not powered, and have that integrated level is high, access speed is fast, is easy to wipe and rewrite
The advantages that, thus be widely used in the multinomial field such as microcomputer, automation control.In order to further increase flash memory storage
The bit density (Bit Density) of device, while a cost (Bit Cost) is reduced, three-dimensional flash memories (3D NAND) skill
Art is rapidly developed.
In 3D nand memory, it is formed through the channel rod structure of stack layer, is needed at the top of the channel rod structure
Conductive plunger is formed, channel rod structure is electrically connected away.Due to needing through smaller size, for example, 39nm bit line by leading
Electric plug is connected to the channel rod structure, and the conductive plunger for connecting the channel rod structure and bit line is caused to need ultra-fine hole, top
Portion's critical size about 26nm, otherwise, bit line are easy the problems such as open circuit occurs between adjacent plug.And it forms small size and surpasses
The conductive plunger of high depth-to-width ratio is directed at illumination, etching and filling all bring very big challenge.
It is two light shields that the solution of current technique, which is by the figure dismantling of conductive plunger, is initially formed a larger size
Bottom plug, then the small sized plug of shape at the top of bottom plug, to reduce the depth-to-width ratio of single etch and filling, cost
While increase, still there are problems that lithography alignment, the etching of small size remains extremely difficult.
How to solve the above problems, is current urgent problem to be solved.
Summary of the invention
The technical problem to be solved by the invention is to provide a kind of semiconductor structures and forming method thereof, advantageously reduce
The difficulty and cost of the size in ultra-fine hole are formed, reliability is improved.
The present invention provides a kind of forming method of semiconductor structure, comprising: provides substrate；It etches the substrate and forms first
Figure, first figure have the first critical size；The first filled layer, first filling are formed in first figure
Layer surface is lower than the substrate surface, fills first figure lower part；Form first covered above first filled layer
The adjustment layer of pattern side wall forms second graph between adjustment layer, and the second graph bottom-exposed goes out the first filled layer of part,
The second graph has the second critical size, and second critical size is less than the first critical size；In the second graph
The second filled layer of interior filling.
Optionally, the substrate includes: substrate；Form stack layer on substrate and the channel column knot through stack layer
Structure；It is formed in the dielectric layer for stacking layer surface；First figure runs through the dielectric layer, exposes channel rod structure surface.
Optionally, first figure and channel rod structure the first critical size having the same.
Optionally, the channel rod structure includes: to be located at channel hole base substrate through the channel hole of stack layer to substrate
The semiconductor epitaxial layers on surface cover the function side wall of channel hole side wall, cover the function side wall and semiconductor epitaxial layers
Channel layer and fill channel hole channel dielectric layer.
Optionally, the adjustment layer also covers dielectric layer upper surface.
Optionally, first filled layer and the second filled layer are conductive material.
Optionally, first figure and second graph are poroid figure.
Optionally, the forming method of the adjustment layer includes: to form covering the first filling layer surface, the first figure side
The adjustment material layer of wall surface and substrate surface；Along the direction of the vertical substrate surface, using the etching mode of no exposure mask,
The adjustment material layer is etched, the second graph of the first filled layer part of the surface of the adjustment layer and exposure is formed.
Optionally, the adjustment material layer is formed using atom layer deposition process.
Optionally, the forming method of first filled layer includes: in first figure and substrate surface deposition the
One material layer, the first material layer fill full first figure；The first material layer is planarized, removal is located at
First material layer above substrate；First material layer in first figure is etched back, the first filled layer is formed.
Optionally, the material of the adjustment layer include silica, silicon nitride, silicon oxynitride, silicon oxide carbide, hafnium oxide and
At least one of zirconium oxide.
Technical solution of the present invention also provides a kind of semiconductor structure, comprising: substrate；Positioned at intrabasement first figure
Shape, first figure have the first critical size；It is filled in the first filled layer of first figure lower part, described first fills out
Layer surface is filled lower than the substrate surface；Cover the adjustment layer of the first pattern side wall above first filled layer, adjustment layer
Between there is second graph, the second graph has the second critical size, and second critical size is less than the first crucial ruler
It is very little；It is filled in the second filled layer in the second graph, second filled layer connects first filled layer.
Optionally, the substrate includes: substrate；Form stack layer on substrate and the channel column knot through stack layer
Structure；It is formed in the dielectric layer for stacking layer surface；First figure runs through the dielectric layer, exposes channel rod structure surface.
Optionally, first figure and channel rod structure the first critical size having the same.
Optionally, the channel rod structure includes: to be located at channel hole base substrate through the channel hole of stack layer to substrate
The semiconductor epitaxial layers on surface cover the function side wall of channel hole side wall, cover the function side wall and semiconductor epitaxial layers
Channel layer and fill channel hole channel dielectric layer.
Optionally, the adjustment layer also covers dielectric layer upper surface.
Optionally, first figure and second graph are poroid figure.
Optionally, first filled layer and the second filled layer are conductive material.
The forming method of semiconductor structure of the invention limits smaller size above the first filled layer by adjusting layer
Second graph, and in second graph filling formed the second filled layer, reduce technology difficulty and cost, and can ensure
Second filled layer is located at the first filling layer surface, avoids the occurrence of the second filled layer position and shifts, it is ensured that is described
The reliability that second filled layer is connect with first filled layer.
Detailed description of the invention
Fig. 1 to Fig. 6 is the structural schematic diagram of the forming process of the semiconductor structure of the embodiment of the invention.
Specific embodiment
The specific embodiment of semiconductor structure provided by the invention and forming method thereof is done in detail with reference to the accompanying drawing
Explanation.
Referring to FIG. 1, providing substrate 100.
The substrate 100 includes substrate 101, the stack layer 102 for being formed in 101 surface of substrate and the covering heap
The dielectric layer 103 of lamination 102；Channel rod structure 110 is formed in the stack layer 102.
The substrate 101 can be the semiconductor substrates such as monocrystalline silicon, monocrystalline germanium.
The stack layer 102 includes the insulating layer 1021 and control grid layer 1022 being alternately stacked, and the insulating layer material can
Think silica, the sacrificial layer material can be silicon nitride.
For the channel rod structure 110 through the stack layer 102 to substrate 100, the channel rod structure 110 includes running through
The channel hole of stack layer 102, the semiconductor epitaxial layers 111 positioned at 100 surface of substrate of channel hole bottom cover channel hole side wall
Function side wall 112, cover the function side wall 112 and semiconductor epitaxial layers 111 channel layer 113 and filling channel hole
Channel dielectric layer 114.The function side wall 112 successively includes electric charge barrier layer, electric charge capture layer and charge from outside to inside
Tunnel layer, usually ONO structure；The material of the channel layer 113 is usually polysilicon；The material of the channel dielectric layer 114
The usually dielectric materials such as silica.
The dielectric layer 103 covers the stack layer 102 and channel rod structure 110, and the dielectric layer 103 is that insulation is situated between
Material can be silica, silicon nitride or silicon oxynitride etc..
In other specific embodiments, the substrate 100 can also form smaller crucial ruler at top for other needs
The structure of very little figure.For example, being formed with metal interconnection structure in the substrate 100, need at the top of the metal interconnection structure
The contact portion for forming smaller size, is electrically connected with the metal interconnection structure.
Referring to FIG. 2, etching the substrate 100, the first figure 201 is formed, first figure 201 has the first key
Size CD1.
Light shield when forming channel hole, the light shield used when forming the first figure 201 as etching, so that institute can be used
The first figure 201 and first critical size having the same of channel rod structure 110 and position are stated, so that the first figure 202
Bottom-exposed goes out the top in channel hole 110.
Specifically, etching the dielectric layer 103 forms first figure 201,201 bottom-exposed of the first figure goes out
The top surface of the channel rod structure 110.
In the specific embodiment, first figure 201 is corresponding with the sectional view of the channel rod structure 110, is
Poroid figure, it is subsequent that the conductive plunger for connecting the channel rod structure 110 is formed in first figure 201.Described first
The critical size CD1 of figure 201 is the diameter of first figure 201.
In other specific embodiments, the groove or other shapes of first figure 201 or strip can
To be set according to structure decision to be connected below, or according to specific requirements.When first figure 201 is strip
When connected in star, the size of first figure 201 is the width of the groove.
Referring to FIG. 3, filling first material layer 301 in first figure 201 (please referring to Fig. 2).
The forming method of the first material layer 301 includes: to deposit the first material on 103 surface of dielectric layer, described
First material fills full first figure 201；It is stop-layer with the dielectric layer 103, first material is carried out flat
Change, forms the first material layer 301 being located in first figure 201.
In the specific embodiment, need to be formed conductive plunger, therefore first material at the top of the channel hole 110
The material of layer 301 is conductive material, can be the metals such as polysilicon and tungsten, copper or aluminium.
Referring to FIG. 4, being returned to the first material layer 301 (please referring to Fig. 3) in the first figure 201 (please referring to Fig. 2)
Etching forms the first filled layer 401.
First filled layer, 401 surface is lower than 103 surface of dielectric layer, fills the lower part of first figure 201.
Technique can be etched back to using selectivity, select the etching technics for having compared with high etch selectivity to the first material layer 301,
The first material layer 301 is etched back.The depth being etched back to can for 201 total depth of the first figure 1/3~
1/2.In a specific embodiment, being etched back to depth is 100nm.
Referring to FIG. 5, the adjustment layer 501 for covering 201 side wall of the first figure of 401 top of the first filled layer is formed,
Second graph 502 is formed between adjustment layer 501,502 bottom-exposed of second graph goes out the first filled layer of part 401, described
Second graph 502 has the second critical size CD2.
The critical size CD2 of the second graph 502 is the diameter of the second graph 502.
In other specific embodiments, the groove or other shapes of the second graph 502 or strip can
To be set according to structure decision to be connected below, or according to specific requirements.When the second graph 502 is strip
When connected in star, the size of first figure 502 is the width of the groove.
The second critical size CD2 is less than the first critical size CD1.
In the specific embodiment, the adjustment layer 501 only covers the first figure of 401 top of the first filled layer
The side wall of 201 (please referring to Fig. 4).In other specific embodiments, the adjustment layer 501 can also cover the dielectric layer
103 surface.
The forming method of the adjustment layer 501 includes: to form adjustment material layer using atom layer deposition process, so as to institute
The thickness for stating adjustment layer 501 is accurately controlled；It is formed and covers 401 surface of the first filled layer, 201 side wall table of the first figure
The adjustment material layer on 103 surface of face and dielectric layer；Along the direction of the vertical substrate surface, using the etching side of no exposure mask
Formula etches the adjustment material layer, forms the second figure of the adjustment layer 501 and exposure 401 part of the surface of the first filled layer
Shape 502.The material of the adjustment material layer includes silica, silicon nitride, silicon oxynitride, silicon oxide carbide, hafnium oxide and oxidation
At least one of insulating dielectric materials such as zirconium.Preferably, the material of the adjustment material layer and the material of the dielectric layer 103
Difference, convenient for subsequent during etching the adjustment material layer, using the dielectric layer 103 as etching stop layer.
The second graph 502 has the second critical size CD2, and the adjustment layer 501 is closed with a thickness of d, described second
Key size CD2=CD1-2d, by adjusting the thickness of the adjustment layer 501, it will be able to which the second critical size CD2 is carried out
Adjustment.
The second critical size CD2 cannot be too small, and the depth-to-width ratio for avoiding result in second graph 502 is excessive, and after influencing
Continue and forms the second filled layer in the second graph 502.Preferably, the first critical size CD1 and the second critical size
The ratio between CD2 range is 2:1~4:1.
In the specific embodiment, first figure 201 is hole shape, corresponding, and the second graph 502 is also hole
Shape.And since the second graph 502 is surrounded by the adjustment layer 501, filled out so that the second graph 502 is located at described first
The overcentre for filling layer 401, the problem of avoiding the occurrence of misalignment.
Referring to FIG. 6, filling the second filled layer 601 in the second graph 502 (please referring to Fig. 5).
The material of second filled layer 601 is in conductive material, including the metal materials such as polysilicon and tungsten, copper or aluminium
At least one, be electrically connected with being formed between first filled layer 401.In the specific embodiment, second filling
The material of layer 601 is identical as the material of first filled layer 401, is tungsten.
In other specific embodiments, the material of first filled layer 401 and second filled layer 601 according to
Demand can be other non-conducting materials.
In the forming method of above-mentioned semiconductor structure, smaller size is limited above the first filled layer by adjusting layer
Second graph, and filling forms the second filled layer in second graph, reduces technology difficulty and cost, and can ensure institute
It states the second filled layer and is located at the first filling layer surface, avoid the occurrence of the second filled layer position and shift, it is ensured that described the
The reliability that two filled layers are connect with first filled layer.
The above method is suitable for any required structure for forming ultra-fine hole, and this is not restricted.
A specific embodiment of the invention also provides a kind of semiconductor structure.
Referring to FIG. 6, the structural schematic diagram of the semiconductor structure for the embodiment of the invention.
The semiconductor structure includes: substrate；Positioned at intrabasement first figure, first figure has first
Critical size；It is filled in the first filled layer 401 of first figure lower part, 401 surface of the first filled layer is lower than described
Substrate surface；The adjustment layer 501 of the first pattern side wall of 401 top of the first filled layer is covered, is had between adjustment layer 501
Second graph, the second graph have the second critical size, and second critical size is less than the first critical size；It is filled in
Second filled layer 601 in the second graph, second filled layer 601 connect first filled layer 401.
In the specific embodiment, the substrate includes substrate 101, the stack layer 102 for being formed in 101 surface of substrate
And the dielectric layer 103 of the covering stack layer 102；Channel rod structure 110 is formed in the stack layer 102.
The substrate 101 can be the semiconductor substrates such as monocrystalline silicon, monocrystalline germanium.
The stack layer 102 includes the insulating layer 1021 and control grid layer 1022 being alternately stacked, and the insulating layer material can
Think silica, the sacrificial layer material can be silicon nitride.
For the channel rod structure 110 through the stack layer 102 to substrate 100, the channel rod structure 110 includes running through
The stack layer 102 is to the channel hole of substrate 100, semiconductor epitaxial layers 111 positioned at 100 surface of substrate of channel hole bottom,
The function side wall 112 for covering channel hole side wall, covers the channel layer 113 of the function side wall 112 and semiconductor epitaxial layers 111
And the channel dielectric layer 114 in filling channel hole.The function side wall 112 successively includes electric charge barrier layer, charge from outside to inside
Trapping layer and charge tunnel layer, usually ONO structure；The material of the channel layer 113 is usually polysilicon；The channel is situated between
The material of matter layer 114 is usually the dielectric materials such as silica.
The dielectric layer 103 covers the stack layer 102 and channel rod structure 110, and the dielectric layer 103 is that insulation is situated between
Material can be silica, silicon nitride or silicon oxynitride etc..
In other specific embodiments, the substrate 100 can also form smaller crucial ruler at top for other needs
The structure of very little figure.For example, being formed with metal interconnection structure in the substrate 100, need at the top of the metal interconnection structure
The contact portion for forming smaller size, is electrically connected with the metal interconnection structure.
First figure and second graph be it is poroid, the critical size of the first figure and second graph is diameter,
So that first filled layer 401 and the second filled layer 601 are column, first filled layer 401 and the second filled layer 601 are
It can be the metals such as polysilicon and tungsten, copper or aluminium for conductive material.
The ratio between 601 critical size of critical size and the second filled layer of first filled layer 401 range is 2:1~4:1.
The material of the adjustment layer 501 includes silica, silicon nitride, silicon oxynitride, silicon oxide carbide, hafnium oxide and oxidation
At least one of insulating dielectric materials such as zirconium.
The adjustment layer 501 limits the second graph of smaller size above the first filled layer 401, and in second graph
It is inside formed with the second filled layer 601, reduces technology difficulty and cost, and can ensure that second filled layer 601 is located at
First filled layer, 401 surface avoids the occurrence of 601 position of the second filled layer and shifts, it is ensured that second filled layer 601
The reliability being connect with first filled layer 401.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (18)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided；
It etches the substrate and forms the first figure, first figure has the first critical size；
The first filled layer is formed in first figure, the first filling layer surface is lower than the substrate surface, fills institute
State the first figure lower part；
The adjustment layer for covering the first pattern side wall above first filled layer is formed, forms second graph between adjustment layer,
The second graph bottom-exposed goes out the first filled layer of part, and the second graph has the second critical size, and described second closes
Key size is less than the first critical size；
The second filled layer is filled in the second graph.
2. the forming method of semiconductor structure according to claim 1, which is characterized in that the substrate includes: substrate；Shape
At stack layer on substrate and through the channel rod structure of stack layer；It is formed in the dielectric layer for stacking layer surface；Described first
Figure runs through the dielectric layer, exposes channel rod structure surface.
3. the forming method of semiconductor structure according to claim 1, which is characterized in that first figure and the ditch
Road rod structure the first critical size having the same.
4. the forming method of semiconductor structure according to claim 2, which is characterized in that the channel rod structure includes:
Channel hole side wall is covered positioned at the semiconductor epitaxial layers of channel hole bottom substrate surface through the channel hole of stack layer to substrate
Function side wall, cover the function side wall and semiconductor epitaxial layers channel layer and fill channel hole ditch track media
Layer.
5. the forming method of semiconductor structure according to claim 1, which is characterized in that the adjustment layer also covers dielectric
Layer upper surface.
6. the forming method of semiconductor structure according to claim 1, which is characterized in that first filled layer and second
Filled layer is conductive material.
7. the forming method of semiconductor structure according to claim 1, which is characterized in that first figure and the second figure
Shape is poroid figure.
8. the forming method of semiconductor structure according to claim 1, which is characterized in that the forming method of the adjustment layer
It include: to form the adjustment material layer for covering the first filling layer surface, the first pattern side wall surface and substrate surface；Along vertical
The direction of the straight substrate surface, etches the adjustment material layer, forms the first filled layer part of the adjustment layer and exposure
The second graph on surface.
9. the forming method of semiconductor structure according to claim 8, which is characterized in that use atom layer deposition process shape
At the adjustment material layer.
10. the forming method of semiconductor structure according to claim 1, which is characterized in that the shape of first filled layer
It include: in first figure and substrate surface deposition first material layer at method, the first material layer filling is full described
First figure；The first material layer is planarized, removal is located at the first material layer above substrate；To in the first figure
First material layer be etched back, formed the first filled layer.
11. the forming method of semiconductor structure according to claim 1, which is characterized in that the material packet of the adjustment layer
Include at least one of silica, silicon nitride, silicon oxynitride, silicon oxide carbide, hafnium oxide and zirconium oxide.
12. a kind of semiconductor structure characterized by comprising
Substrate；
Positioned at intrabasement first figure, first figure has the first critical size；
It is filled in the first filled layer of first figure lower part, the first filling layer surface is lower than the substrate surface；
The adjustment layer of the first pattern side wall above first filled layer is covered, there is second graph between adjustment layer, it is described
Second graph has the second critical size, and second critical size is less than the first critical size；
It is filled in the second filled layer in the second graph, second filled layer connects first filled layer.
13. semiconductor structure according to claim 12, which is characterized in that the substrate includes: substrate；It is formed in substrate
On stack layer and channel rod structure through stack layer；It is formed in the dielectric layer for stacking layer surface；First figure runs through
The dielectric layer exposes channel rod structure surface.
14. semiconductor structure according to claim 13, which is characterized in that first figure has with channel rod structure
Identical first critical size.
15. semiconductor structure according to claim 13, which is characterized in that the channel rod structure includes: through stacking
Layer covers the functioning side of channel hole side wall positioned at the semiconductor epitaxial layers of channel hole bottom substrate surface to the channel hole of substrate
Wall covers the channel layer of the function side wall and semiconductor epitaxial layers and fills the channel dielectric layer in channel hole.
16. semiconductor structure according to claim 12, which is characterized in that the adjustment layer also covers table on dielectric layer
Face.
17. semiconductor structure according to claim 12, which is characterized in that first figure and second graph are hole
Shape figure.
18. semiconductor structure according to claim 12, which is characterized in that first filled layer and the second filled layer are
Conductive material.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120061744A1 (en) * | 2010-09-10 | 2012-03-15 | Sung-Min Hwang | Three dimensional semiconductor memory devices |
| CN105637622A (en) * | 2013-08-26 | 2016-06-01 | 美光科技公司 | Semiconductor constructions and methods of forming electrically conductive contacts |
| CN107808884A (en) * | 2016-08-24 | 2018-03-16 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of three dimensional NAND flush memory device |
-
2019
- 2019-01-02 CN CN201910002291.0A patent/CN109698199A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120061744A1 (en) * | 2010-09-10 | 2012-03-15 | Sung-Min Hwang | Three dimensional semiconductor memory devices |
| CN105637622A (en) * | 2013-08-26 | 2016-06-01 | 美光科技公司 | Semiconductor constructions and methods of forming electrically conductive contacts |
| CN107808884A (en) * | 2016-08-24 | 2018-03-16 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of three dimensional NAND flush memory device |
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Application publication date: 20190430 |