CN109698008A - The restorative procedure and device of NOR type memory bit line failure - Google Patents
The restorative procedure and device of NOR type memory bit line failure Download PDFInfo
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- CN109698008A CN109698008A CN201710992665.9A CN201710992665A CN109698008A CN 109698008 A CN109698008 A CN 109698008A CN 201710992665 A CN201710992665 A CN 201710992665A CN 109698008 A CN109698008 A CN 109698008A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
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Abstract
The invention discloses the restorative procedures and device of a kind of NOR type memory bit line failure, comprising: whether the bit line for detecting main array memory cells and function array storage unit has exception, finds out the storage unit connecting with defective bit, is denoted as fault memory cell；Address, the reparation enable bit of fault memory cell and the classification logotype position of fault memory cell for storing fault memory cell, the reparation enable bit that fault memory cell is arranged is 0 or 1；Establish the mapping relations of fault memory cell and redundant storage unit；The corresponding reparation enable bit of storage unit to access is 1, then the storage unit to be accessed is the fault memory cell for needing to repair；Redundant storage unit corresponding with fault memory cell is selected to substitute fault memory cell.The technical solution of the embodiment of the present invention, the method by increasing classification logotype position, repairs fault memory cell, to improve product yield and the utilization rate to redundant storage unit.
Description
Technical field
The present embodiments relate to non-volatile memory technologies field more particularly to a kind of events of NOR type memory bit line
The restorative procedure and device of barrier.
Background technique
In NOR type memory, although determining that it has higher reliability by its structure, produce in order to better improve
Product yield can generally add one group of redundant storage unit in design beside main array memory cells, when main array stores list
When not writeable certain storage units appearance or wiping phenomenon are tested in member factory, this storage unit may be to connect with defective bit
Storage unit deposited in this way to bad at this point it is possible to be replaced by certain mapping relations with redundant storage unit
When storage unit address executes corresponding erasable operation, guarantee that chip data is correct, to improve the production yield of product.
In some special applications, in order to further guarantee chip reliability, error correction, encryption and decryption etc. can be added
Function, but there is no to the storage unit repair process wherein to break down.
Summary of the invention
In view of this, the embodiment of the invention provides the restorative procedure and device of a kind of NOR type memory bit line failure, it can
To be repaired to the fault memory cell in main array memory cells and function array storage unit, to improve product
Yield and utilization rate to redundant storage unit.
In a first aspect, the embodiment of the invention provides a kind of restorative procedure of NOR type memory bit line failure, this method packet
It includes:
Whether the bit line for detecting main array memory cells and function array storage unit has exception, finds out and connects with defective bit
The storage unit connect, is denoted as fault memory cell；
Store the address of the fault memory cell, the reparation enable bit of the fault memory cell and the failed storage
The classification logotype position of unit, and the fault memory cell is arranged according to the partial address in the address of the fault memory cell
Reparation enable bit be 0 or 1；
Establish the mapping relations of the fault memory cell and redundant storage unit；
By comparing the portion in the access unit address and the pre-stored fault memory cell address to be accessed
Sub-address obtains reparation enable bit corresponding with the storage unit to be accessed, if the storage unit to be accessed is corresponding
Reparation enable bit be 1, then the storage unit to be accessed be the fault memory cell that needs are repaired；
When the corresponding reparation enable bit of the storage unit to be accessed is 1, by the ground of the storage unit to be accessed
Location is compared with the address of the pre-stored fault memory cell, if the access unit address to be accessed and pre-
The address matching of the fault memory cell first stored, then according to the classification of the mapping relations and the fault memory cell
Marker selects the redundant storage unit substitution corresponding with the fault memory cell from the redundant storage unit
The fault memory cell.
Optionally, the classification logotype position according to the mapping relations and the fault memory cell, from the redundancy
In storage unit, the redundant storage unit corresponding with the fault memory cell is selected to substitute the fault memory cell tool
Body includes:
According to the classification logotype position of the fault memory cell, the failed storage list in the main array memory cells is set
The reparation sequence of fault memory cell in the first and described function array storage unit；
According to the reparation sequence and the mapping relations, the redundancy corresponding with the fault memory cell is selected
Storage unit substitutes the fault memory cell.
Optionally, the function array storage unit include encrypted array storage unit, decryption array memory cells or
One of error correction array memory cells are multiple.
Optionally, if the fault memory cell is located at the main array memory cells and the function array storage unit
In, and the function array storage unit be error correction array memory cells when, the failed storage list of the main array memory cells
The classification logotype position of member is 1, and the classification logotype position of the fault memory cell of the function array storage unit is 0.
Second aspect, the embodiment of the invention provides a kind of prosthetic devices of NOR type memory bit line failure, comprising:
Whether detection module, the bit line for detecting main array memory cells and function array storage unit have exception, look for
The storage unit connecting out with defective bit, is denoted as fault memory cell；
Latch module, the latch module are connected with the detection module, for storing the ground of the fault memory cell
Location, the reparation enable bit of the fault memory cell and the fault memory cell classification logotype position, and according to the failure
The reparation enable bit that the fault memory cell is arranged in partial address in access unit address is 0 or 1；
Mapping relations establish module, and the mapping relations establish module and are connected with the latch module, described for establishing
The mapping relations of fault memory cell and redundant storage unit；
Confirm that repair module, the confirmation repair module are connected with the latch module, for what is accessed by comparison
Partial address in access unit address and the pre-stored fault memory cell address obtains to be accessed with described
The corresponding reparation enable bit of storage unit, it is described to visit if the corresponding reparation enable bit of the storage unit to be accessed is 1
The storage unit asked is the fault memory cell for needing to repair；
Repair module, the repair module establish module phase with the confirmation repair module and the mapping relations respectively
Even, for being 1 when the corresponding reparation enable bit of the storage unit to be accessed, by the access unit address to be accessed
Be compared with the address of the pre-stored fault memory cell, if the access unit address to be accessed and in advance
The address matching of the fault memory cell of storage, then according to the classification mark of the mapping relations and the fault memory cell
Know position, from the redundant storage unit, the redundant storage unit corresponding with the fault memory cell is selected to substitute institute
State fault memory cell.
Optionally, the repair module further includes reparation sequence setup unit, and the reparation sequence setup unit is used for root
According to the classification logotype position of the fault memory cell, fault memory cell and the function in the main array memory cells are set
The reparation sequence of fault memory cell in energy array memory cells；
The repair module is used for according to the reparation sequence and the mapping relations, selection and the failed storage list
The corresponding redundant storage unit of member substitutes the fault memory cell.
Optionally, the function array storage unit include encrypted array storage unit, decryption array memory cells or
One of error correction array memory cells are multiple.
Optionally, if the fault memory cell is located at the main array memory cells and the function array storage unit
In, and the function array storage unit be error correction array memory cells when, the failed storage list of the main array memory cells
The classification logotype position of member is 1, and the classification logotype position of the fault memory cell of the function array storage unit is 0.
The technical solution of the present embodiment passes through the address of record storage fault memory cell and the classification of fault memory cell
Marker is reflected with having in redundant storage unit with the fault memory cell in main array memory cells and function array storage unit
The storage unit replacement fault memory cell of relationship is penetrated, to achieve the purpose that repair fault memory cell.Due to having recorded failure
The classification logotype position of storage unit can be used one group of redundant storage unit to repair fault memory cell, and can distinguish
What is repaired is main array memory cells or function array storage unit, improves product yield and to redundant storage unit
Utilization rate.
Detailed description of the invention
Fig. 1 is a kind of process signal of the restorative procedure for NOR type memory bit line failure that the embodiment of the present invention one provides
Figure；
Fig. 2 is a kind of process signal of restorative procedure of NOR type memory bit line failure provided by Embodiment 2 of the present invention
Figure；
Fig. 3 is a kind of structural representation of the prosthetic device for NOR type memory bit line failure that the embodiment of the present invention three provides
Figure；
Fig. 4 is that the structure of the prosthetic device for another NOR type memory bit line failure that the embodiment of the present invention three provides is shown
It is intended to.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Embodiment one
Fig. 1 is a kind of flow diagram of the restorative procedure of NOR type memory bit line failure provided in an embodiment of the present invention,
This method can be executed by a kind of prosthetic device of NOR type memory bit line failure, wherein the device can by hardware and/or
Software is realized, is specifically comprised the following steps:
Whether the bit line of step 101, the main array memory cells of detection and function array storage unit has exception, finds out and event
The storage unit for hindering bit line connection, is denoted as fault memory cell.
In the present embodiment, main array memory cells are generally used for reading and writing and erasing operation.In order to further protect
Error correction can be added in the reliability for demonstrate,proving chip, and the functions such as encryption and decryption, when these functions are added, corresponding encoding and decoding are believed
Breath can store in function array storage unit.Optionally, function array storage unit includes encrypted array storage unit, solution
One of close array memory cells or error correction array memory cells are multiple.
Step 102, the reparation enable bit and fault memory cell for storing the address of fault memory cell, fault memory cell
Classification logotype position, and according in the address of fault memory cell partial address setting fault memory cell reparation enable bit
It is 0 or 1.
In the present embodiment, when storing the address of fault memory cell, the classification logotype position that fault memory cell is arranged is
In order to distinguish the classification of main array memory cells and function array storage unit in fault memory cell.Illustratively, part
Address is not whole addresses of fault memory cell, can be highest several, is also possible to several, end, or interposition
Several set, occupy-place of the partial address in the address of fault memory cell can be continuously, be also possible to discontinuous.
Step 103, the mapping relations for establishing fault memory cell and redundant storage unit.
In the present embodiment, a logical address can be shared by setting fault memory cell and redundant storage unit
Mode establishes the mapping relations of fault memory cell and redundant storage unit.
Step 104, by compare the access unit address and pre-stored fault memory cell address to be accessed in
Partial address, obtain corresponding with the storage unit to be accessed reparation enable bit, corresponding repaired to the storage unit of access
Multiple enable bit is 1, then the storage unit to be accessed is the fault memory cell for needing to repair.
By comparing in the access unit address to be accessed and pre-stored fault memory cell address partly
During location, reparation enable bit corresponding with the storage unit to be accessed, the corresponding reparation of the storage unit to be accessed are obtained
Enable bit is 1, then the storage unit to be accessed is the fault memory cell for needing to repair.The storage unit to be accessed is corresponding to repair
Multiple enable bit is 1, illustrate to also including partial address in the access unit address to be accessed, and partial address will access
Access unit address it is identical with the occupy-place of pre-stored fault memory cell address.
Step 105, when the corresponding reparation enable bit of the storage unit to be accessed be 1, the storage unit that will be accessed
Address be compared with the address of pre-stored fault memory cell, to access access unit address with deposit in advance
The address matching of the fault memory cell of storage is deposited then according to the classification logotype position of mapping relations and fault memory cell from redundancy
In storage unit, redundant storage unit corresponding with fault memory cell is selected to substitute fault memory cell.
On the basis of above-mentioned steps, it is thus identified that the storage unit to be accessed is the fault memory cell for needing to repair,
Step 105 by way of replacement (selection redundant storage unit corresponding with fault memory cell substitution fault memory cell) come
Repair fault memory cell.
The technical solution of the present embodiment passes through the address of record storage fault memory cell and the classification of fault memory cell
Marker is reflected with having in redundant storage unit with the fault memory cell in main array memory cells and function array storage unit
The storage unit replacement fault memory cell of relationship is penetrated, to achieve the purpose that repair fault memory cell.Due to having recorded failure
The classification logotype position of storage unit can be used one group of redundant storage unit to repair fault memory cell, and can distinguish
What is repaired is main array memory cells or function array storage unit, improves product yield and to redundant storage unit
Utilization rate.
Optionally, in the technology of above-mentioned technical proposal, if fault memory cell is located at main array memory cells and function
In array memory cells, and function array storage unit be error correction array memory cells when, the failure of main array memory cells is deposited
The classification logotype position of storage unit is 1, and the classification logotype position of the fault memory cell of function array storage unit is 0.
Illustratively, if fault memory cell is located in main array memory cells and function array storage unit, and function
When array memory cells include error correction array memory cells, encrypted array storage unit and decryption array memory cells, main battle array
The classification logotype position of the fault memory cell of array storage unit is 11, the classification of the fault memory cell of error correction array memory cells
Marker is 00, and the classification logotype position of the fault memory cell of encrypted array storage unit is 01 and decryption array memory cells
Fault memory cell classification logotype position be 10.
It should be noted that if the position of increase classification logotype position can be passed through when function array storage unit is a variety of
Wide mode distinguishes the fault memory cell in function array storage unit and main array memory cells.
Embodiment two
On the basis of above-described embodiment, repairing the embodiment of the invention provides a kind of NOR type memory bit line failure
Compound method, referring to fig. 2, method and step is as follows:
Whether the bit line of step 201, the main array memory cells of detection and function array storage unit has exception, finds out and event
The storage unit for hindering bit line connection, is denoted as fault memory cell.
Step 202, the reparation enable bit and fault memory cell for storing the address of fault memory cell, fault memory cell
Classification logotype position, and according in the address of fault memory cell partial address setting fault memory cell reparation enable bit
It is 0 or 1.
Step 203, the mapping relations for establishing fault memory cell and redundant storage unit.
Step 204, by compare the access unit address and pre-stored fault memory cell address to be accessed in
Partial address, obtain corresponding with the storage unit to be accessed reparation enable bit, corresponding repaired to the storage unit of access
Multiple enable bit is 1, then the storage unit to be accessed is the fault memory cell for needing to repair.
Step 205, when the corresponding reparation enable bit of the storage unit to be accessed be 1, the storage unit that will be accessed
Address be compared with the address of pre-stored fault memory cell, to access access unit address with deposit in advance
The address matching of the fault memory cell of storage sets main array memory cells then according to the classification logotype position of fault memory cell
In fault memory cell and the fault memory cell in function array storage unit reparation sequence；According to reparation sequence and
Mapping relations select redundant storage unit corresponding with fault memory cell to substitute fault memory cell.
The classification logotype position for passing through fault memory cell in step 205, can set the failure in main array memory cells
The reparation sequence of storage unit and the fault memory cell in function array storage unit.Such as it is (superfluous in order to save reparation resource
The quantity of balance storage unit), it can be repaired by same group of redundant storage unit, and it is single preferentially to repair main array storage
Member；For main array memory cells and function array storage unit all faulty storage unit the case where, can pass through selection only
The address and classification logotype position for recording the fault memory cell of main array memory cells, preferentially repair the event of main array memory cells
Hinder storage unit, to guarantee that data are correct.When executing replacement operation, if the address information of fault memory cell is only recorded,
It so just distinguishes and does not come out that repair when the matching of current address is main array memory cells or function array storage unit, in order to
It solves the above problems, the technical solution of the present embodiment can be distinguished and be repaired by the classification logotype position of record fault memory cell
Multiple is main array memory cells or function array storage unit.
The technical solution of the present embodiment passes through the classification logotype of fault memory cell on the technology of above-described embodiment
Position can set the fault memory cell in main array memory cells and the fault memory cell in function array storage unit
Reparation sequence.
Embodiment three
Fig. 3 show a kind of prosthetic device structural representation of NOR type memory bit line failure provided in an embodiment of the present invention
Figure, which can be by hardware realization, as shown in figure 3, the device includes:
Whether detection module 301, the bit line for detecting main array memory cells and function array storage unit have exception,
The storage unit connecting with defective bit is found out, fault memory cell is denoted as；
Latch module 302, latch module 302 are connected with detection module 301, for storing the ground of the fault memory cell
Location, the reparation enable bit of the fault memory cell and the fault memory cell classification logotype position, and according to the failure
The reparation enable bit that the fault memory cell is arranged in partial address in access unit address is 0 or 1；
Mapping relations establish module 303, and mapping relations establish module 303 and are connected with latch module 302, for establishing failure
The mapping relations of storage unit and redundant storage unit；
Confirm that repair module 304, confirmation repair module 304 are connected with the latch module 302, for visit by comparing
The partial address in access unit address and the pre-stored fault memory cell address asked, acquisition will be visited with described
The corresponding reparation enable bit of the storage unit asked, it is described if the corresponding reparation enable bit of the storage unit to be accessed is 1
The storage unit to be accessed is the fault memory cell for needing to repair；
Repair module 305, the repair module 305 are built with the confirmation repair module 304 and the mapping relations respectively
Formwork erection block 303 is connected, for being 1 when corresponding the reparations enable bit of the storage unit to be accessed, by it is described to be accessed deposit
The address of storage unit is compared with the address of the pre-stored fault memory cell, if the storage unit to be accessed
Address and the pre-stored fault memory cell address matching, then according to the mapping relations and the failed storage
The classification logotype position of unit selects the redundancy corresponding with the fault memory cell to deposit from the redundant storage unit
Storage unit substitutes the fault memory cell.
Optionally, based on the above technical solution, referring to fig. 4, repair module 305 further includes that reparation sequence sets list
Member 3051, reparation sequence setup unit are used for the classification logotype position according to fault memory cell, set in main array memory cells
Fault memory cell and the fault memory cell in function array storage unit reparation sequence；
Repair module 305 is used to select redundancy corresponding with fault memory cell according to reparation sequence and mapping relations
Storage unit substitutes fault memory cell.
The technical solution of the present embodiment passes through the address of record storage fault memory cell and the classification of fault memory cell
Marker is reflected with having in redundant storage unit with the fault memory cell in main array memory cells and function array storage unit
The storage unit replacement fault memory cell of relationship is penetrated, to achieve the purpose that repair fault memory cell.Due to having recorded failure
The classification logotype position of storage unit can be used one group of redundant storage unit to repair fault memory cell, and can distinguish
What is repaired is main array memory cells or function array storage unit, improves product yield and to redundant storage unit
Utilization rate.
Optionally, based on the above technical solution, the function array storage unit includes that encrypted array storage is single
Member, decryption one of array memory cells or error correction array memory cells or multiple.
Optionally, based on the above technical solution, if the fault memory cell is located at the main array storage list
In the first and described function array storage unit, and the function array storage unit be error correction array memory cells when, the master
The classification logotype position of the fault memory cell of array memory cells is 1, the fault memory cell of the function array storage unit
Classification logotype position be 0.
Any embodiment of that present invention can be performed in the prosthetic device of the NOR type memory bit line failure provided in above-described embodiment
The restorative procedure of provided NOR type memory bit line failure has and executes the corresponding functional module of this method and beneficial effect.
The not technical detail of detailed description in the above-described embodiments, reference can be made to NOR type memory provided by any embodiment of the invention
The restorative procedure of bit line malfunctions.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts, be combined with each other and substitutes without departing from protection scope of the present invention.Therefore, although by above embodiments to this
Invention is described in further detail, but the present invention is not limited to the above embodiments only, is not departing from present inventive concept
In the case of, it can also include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (8)
1. a kind of restorative procedure of NOR type memory bit line failure characterized by comprising
Whether the bit line for detecting main array memory cells and function array storage unit have exception, finds out and connect with defective bit
Storage unit is denoted as fault memory cell；
Store the address of the fault memory cell, the reparation enable bit of the fault memory cell and the fault memory cell
Classification logotype position, and repairing for the fault memory cell is arranged according to the partial address in the address of the fault memory cell
Multiple enable bit is 0 or 1；
Establish the mapping relations of the fault memory cell and redundant storage unit；
By comparing in the access unit address to be accessed and the pre-stored fault memory cell address partly
Location obtains reparation enable bit corresponding with the storage unit to be accessed, repairs if the storage unit to be accessed is corresponding
Multiple enable bit is 1, then the storage unit to be accessed is the fault memory cell for needing to repair；
When the corresponding reparation enable bit of the storage unit to be accessed be 1, by the access unit address to be accessed with
The address of the pre-stored fault memory cell is compared, if the access unit address to be accessed with deposit in advance
The address matching of the fault memory cell of storage, then according to the classification logotype of the mapping relations and the fault memory cell
Position selects described in the redundant storage unit substitution corresponding with the fault memory cell from the redundant storage unit
Fault memory cell.
2. restorative procedure according to claim 1, which is characterized in that
The classification logotype position according to the mapping relations and the fault memory cell, from the redundant storage unit,
It selects the redundant storage unit corresponding with the fault memory cell to substitute the fault memory cell to specifically include:
According to the classification logotype position of the fault memory cell, set fault memory cell in the main array memory cells and
The reparation sequence of fault memory cell in the function array storage unit；
According to the reparation sequence and the mapping relations, the redundant storage corresponding with the fault memory cell is selected
Unit substitutes the fault memory cell.
3. restorative procedure according to claim 1, which is characterized in that
The function array storage unit includes encrypted array storage unit, decryption array memory cells or the storage of error correction array
One of unit is multiple.
4. restorative procedure according to claim 3, which is characterized in that
If the fault memory cell is located in the main array memory cells and the function array storage unit, and the function
When energy array memory cells are error correction array memory cells, the classification logotype of the fault memory cell of the main array memory cells
Position is 1, and the classification logotype position of the fault memory cell of the function array storage unit is 0.
5. a kind of prosthetic device of NOR type memory bit line failure characterized by comprising
Whether detection module, the bit line for detecting main array memory cells and function array storage unit have exception, find out with
The storage unit of defective bit connection, is denoted as fault memory cell；
Latch module, the latch module are connected with the detection module, for storing address, the institute of the fault memory cell
The reparation enable bit of fault memory cell and the classification logotype position of the fault memory cell are stated, and according to the failed storage list
The reparation enable bit that the fault memory cell is arranged in partial address in the address of member is 0 or 1；
Mapping relations establish module, and the mapping relations establish module and are connected with the latch module, for establishing the failure
The mapping relations of storage unit and redundant storage unit；
Confirm that repair module, the confirmation repair module are connected with the latch module, for by comparing the storage to be accessed
Partial address in the address of unit and the pre-stored fault memory cell address obtains and the storage to be accessed
The corresponding reparation enable bit of unit, it is described to be accessed if the corresponding reparation enable bit of the storage unit to be accessed is 1
Storage unit is the fault memory cell for needing to repair；
Repair module, the repair module establish module with the confirmation repair module and the mapping relations respectively and are connected, and use
In being 1 when the corresponding reparation enable bit of the storage unit to be accessed, by the access unit address to be accessed and in advance
The address of the fault memory cell first stored is compared, if the access unit address to be accessed be stored in advance
The fault memory cell address matching, then according to the classification logotype of the mapping relations and the fault memory cell
Position selects described in the redundant storage unit substitution corresponding with the fault memory cell from the redundant storage unit
Fault memory cell.
6. device according to claim 5, which is characterized in that
The repair module further includes reparation sequence setup unit, and the reparation sequence setup unit according to the failure for depositing
The classification logotype position of storage unit sets fault memory cell and function array storage list in the main array memory cells
The reparation sequence of fault memory cell in member；
The repair module is used for according to the reparation sequence and the mapping relations, selection and the fault memory cell pair
The redundant storage unit answered substitutes the fault memory cell.
7. prosthetic device according to claim 5, which is characterized in that
The function array storage unit includes encrypted array storage unit, decryption array memory cells or the storage of error correction array
One of unit is multiple.
8. prosthetic device according to claim 7, which is characterized in that
If the fault memory cell is located in the main array memory cells and the function array storage unit, and the function
When energy array memory cells are error correction array memory cells, the classification logotype of the fault memory cell of the main array memory cells
Position is 1, and the classification logotype position of the fault memory cell of the function array storage unit is 0.
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| WO2021134628A1 (en) * | 2019-12-31 | 2021-07-08 | 华为技术有限公司 | Failure repair method and device for memory |
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| US9646718B2 (en) * | 2014-08-01 | 2017-05-09 | Samsung Electronics Co., Ltd. | Semiconductor memory device having selective ECC function |
| US20160077940A1 (en) * | 2014-09-12 | 2016-03-17 | Jong-Pil Son | Memory device capable of quickly repairing fail cell |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021134628A1 (en) * | 2019-12-31 | 2021-07-08 | 华为技术有限公司 | Failure repair method and device for memory |
| CN111428280A (en) * | 2020-06-09 | 2020-07-17 | 浙江大学 | SoC (System on chip) security chip key information integrity storage and error self-repairing method |
| CN111428280B (en) * | 2020-06-09 | 2020-11-17 | 浙江大学 | SoC (System on chip) security chip key information integrity storage and error self-repairing method |
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