CN109697506B - 神经网络中的处理 - Google Patents

神经网络中的处理 Download PDF

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CN109697506B
CN109697506B CN201811206575.3A CN201811206575A CN109697506B CN 109697506 B CN109697506 B CN 109697506B CN 201811206575 A CN201811206575 A CN 201811206575A CN 109697506 B CN109697506 B CN 109697506B
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CN109697506A (zh
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斯蒂芬·菲利克斯
西蒙·克里斯蒂安·诺尔斯
戈弗雷·达·科斯塔
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Graphcore Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/061—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using biological neurons, e.g. biological neurons connected to an integrated circuit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/082—Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections

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  • Theoretical Computer Science (AREA)
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  • Pure & Applied Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
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CN201811206575.3A 2017-10-20 2018-10-16 神经网络中的处理 Active CN109697506B (zh)

Applications Claiming Priority (2)

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GB1717306.3A GB2568230B (en) 2017-10-20 2017-10-20 Processing in neural networks
GB1717306.3 2017-10-20

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CN109697506B true CN109697506B (zh) 2023-07-14

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EP (1) EP3474193B1 (https=)
JP (1) JP6709266B2 (https=)
KR (1) KR102197539B1 (https=)
CN (1) CN109697506B (https=)
CA (1) CA3021426C (https=)
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Families Citing this family (4)

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Publication number Priority date Publication date Assignee Title
KR102694572B1 (ko) * 2018-02-20 2024-08-13 삼성전자주식회사 완전 연결 네트워크의 데이터 입력 및 출력을 제어하는 방법 및 장치
KR102683757B1 (ko) * 2018-02-20 2024-07-10 삼성전자주식회사 심층 신경망의 학습을 수행시키는 방법 및 그에 대한 장치
CN117289991B (zh) * 2022-06-14 2025-09-12 北京有竹居网络技术有限公司 处理器以及用于数据处理的方法、设备和存储介质
KR102780709B1 (ko) * 2023-03-31 2025-03-12 한국과학기술원 부호형 비트 슬라이스 생성기 및 그 방법과, 부호형 비트 슬라이스 연산기와, 이들을 적용한 인공지능 신경망 가속장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101488084A (zh) * 2007-12-27 2009-07-22 英特尔公司 执行屏蔽加载和存储操作的指令和逻辑
WO2016043908A1 (en) * 2014-09-19 2016-03-24 Intel Corporation Data element selection and consolidation processors, methods, systems, and instructions
CN106030513A (zh) * 2014-03-27 2016-10-12 英特尔公司 用于采用到被屏蔽结果元素的传播将连续源元素存储到未屏蔽结果元素的处理器、方法、系统和指令
CN106127301A (zh) * 2016-01-16 2016-11-16 上海大学 一种随机神经网络硬件实现装置

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU641418B2 (en) * 1989-09-20 1993-09-23 Fujitsu Limited A parallel data processing system for processing and transmitting data concurrently
JPH11500547A (ja) * 1994-12-01 1999-01-12 インテル・コーポレーション 乗算を有するマイクロプロセッサ
US6473522B1 (en) * 2000-03-14 2002-10-29 Intel Corporation Estimating text color and segmentation of images
JP3621695B2 (ja) 2002-07-29 2005-02-16 株式会社東芝 半導体装置及び素子形成用基板
US20040230626A1 (en) * 2003-05-12 2004-11-18 International Business Machines Corporation Computer system method for a one cycle implementation of test under mask instructions
US7961873B2 (en) * 2004-03-03 2011-06-14 King Fahd University Of Petroleum And Minerals Password protocols using XZ-elliptic curve cryptography
US7502763B2 (en) * 2005-07-29 2009-03-10 The Florida International University Board Of Trustees Artificial neural network design and evaluation tool
US9477467B2 (en) * 2013-03-30 2016-10-25 Intel Corporation Processors, methods, and systems to implement partial register accesses with masked full register accesses
US9417845B2 (en) * 2013-10-02 2016-08-16 Qualcomm Incorporated Method and apparatus for producing programmable probability distribution function of pseudo-random numbers
CN104751227B (zh) * 2013-12-31 2018-03-06 科大讯飞股份有限公司 用于语音识别的深度神经网络的构建方法及系统
EP3123300A1 (en) 2014-03-28 2017-02-01 Intel Corporation Processors, methods, systems, and instructions to store source elements to corresponding unmasked result elements with propagation to masked result elements
US20160026912A1 (en) * 2014-07-22 2016-01-28 Intel Corporation Weight-shifting mechanism for convolutional neural networks
EP3035205A1 (en) * 2014-12-19 2016-06-22 Intel Corporation Reconfigurable functional unit and method for artificial neural networks
US10373054B2 (en) * 2015-04-19 2019-08-06 International Business Machines Corporation Annealed dropout training of neural networks
US10192162B2 (en) * 2015-05-21 2019-01-29 Google Llc Vector computation unit in a neural network processor
CN106447035B (zh) * 2015-10-08 2019-02-26 上海兆芯集成电路有限公司 具有可变率执行单元的处理器
JP2017097585A (ja) * 2015-11-24 2017-06-01 株式会社リコー 学習装置、プログラム及び学習方法
CN106796668B (zh) * 2016-03-16 2019-06-14 香港应用科技研究院有限公司 用于人工神经网络中比特深度减少的方法和系统
US10360496B2 (en) * 2016-04-01 2019-07-23 Intel Corporation Apparatus and method for a digital neuromorphic processor
US10891538B2 (en) * 2016-08-11 2021-01-12 Nvidia Corporation Sparse convolutional neural network accelerator
US11068781B2 (en) * 2016-10-07 2021-07-20 Nvidia Corporation Temporal ensembling for semi-supervised learning
US10528321B2 (en) * 2016-12-07 2020-01-07 Microsoft Technology Licensing, Llc Block floating point for neural network implementations
CA3108151C (en) * 2017-02-23 2024-02-20 Cerebras Systems Inc. Accelerated deep learning
US10776697B2 (en) * 2017-04-18 2020-09-15 Huawei Technologies Co., Ltd. System and method for training a neural network

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101488084A (zh) * 2007-12-27 2009-07-22 英特尔公司 执行屏蔽加载和存储操作的指令和逻辑
CN106030513A (zh) * 2014-03-27 2016-10-12 英特尔公司 用于采用到被屏蔽结果元素的传播将连续源元素存储到未屏蔽结果元素的处理器、方法、系统和指令
WO2016043908A1 (en) * 2014-09-19 2016-03-24 Intel Corporation Data element selection and consolidation processors, methods, systems, and instructions
CN106127301A (zh) * 2016-01-16 2016-11-16 上海大学 一种随机神经网络硬件实现装置

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Publication number Publication date
CA3021426A1 (en) 2019-04-20
JP6709266B2 (ja) 2020-06-10
JP2019079524A (ja) 2019-05-23
CN109697506A (zh) 2019-04-30
KR20190044549A (ko) 2019-04-30
US11900109B2 (en) 2024-02-13
TW201931107A (zh) 2019-08-01
US20190121639A1 (en) 2019-04-25
GB2568230B (en) 2020-06-03
TWI719348B (zh) 2021-02-21
GB201717306D0 (en) 2017-12-06
KR102197539B1 (ko) 2020-12-31
GB2568230A (en) 2019-05-15
EP3474193A1 (en) 2019-04-24
EP3474193B1 (en) 2025-09-10
CA3021426C (en) 2023-08-01

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