CN109695446A - A kind of induction log tool transmission power adaptation adjustment device - Google Patents
A kind of induction log tool transmission power adaptation adjustment device Download PDFInfo
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- CN109695446A CN109695446A CN201910006685.3A CN201910006685A CN109695446A CN 109695446 A CN109695446 A CN 109695446A CN 201910006685 A CN201910006685 A CN 201910006685A CN 109695446 A CN109695446 A CN 109695446A
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- E—FIXED CONSTRUCTIONS
- E21—EARTH DRILLING; MINING
- E21B—EARTH DRILLING, e.g. DEEP DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
- E21B47/00—Survey of boreholes or wells
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- E—FIXED CONSTRUCTIONS
- E21—EARTH DRILLING; MINING
- E21B—EARTH DRILLING, e.g. DEEP DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
- E21B47/00—Survey of boreholes or wells
- E21B47/12—Means for transmitting measuring-signals or control signals from the well to the surface, or from the surface to the well, e.g. for logging while drilling
Abstract
The invention discloses a kind of induction log tool transmission power adaptations to adjust device, is not necessarily to configuration software or programming program, realizes adjust automatically by hardware circuit completely.The signal magnitude that hardware circuit of the invention is acquired according to AD analog-digital converter calculates automatically and adjusts transmission power, the signal magnitude for ensuring that induction log tool eventually receives is in optimum state always, reception signal is allowed to be unlikely to excessive and be saturated, it is unlikely to too small and causes measurement accuracy inadequate, final realize reduces part system power consumption, reduce artificial step-up error, improves measurement accuracy and measurement efficiency.Meanwhile the present invention is not needed program software participation, greatly improves the reliability of system, can be placed in instrument system with individually designed at a hardware module, debugging is flexible, convenient disassembly due to the design using devices at full hardware circuit.
Description
Technical field
The invention belongs to transmission power automatic control technology fields, and in particular to a kind of induction log tool transmission power is adaptive
The design of device should be adjusted.
Background technique
With the development that induction logging technology is maked rapid progress, major part well logging field instrument system is all to pass through in advance at present
The good transmission power of the artificial configuration of host computer interface, or set the parameters in measurement process by repeatedly artificially calculating
Realize the configuration of transmission power.After setting transmission power, instrument is measured according to fixed transmission power always, this
Just certainly exist some drawbacks, if transmission power be arranged in advance it is excessive if, certainly will have the waste of transmission power, power consumption mentions
Height, inefficiency, while it is also possible that must to receive circuit signal excessive and be saturated, and then influence measurement result.If emitting function
The too small or route of transmission decaying of rate setting is excessive, the measurement of final result is also influenced whether, so that the signal received
It can become smaller, the measurement accuracy of signal-to-noise ratio and final system all can be impacted.When with depth of stratum increasing and region change
Becoming, bigger change can also occur for temperature, and temperature, which gets over high emission signal, to become smaller, then the signal amplitude received is also smaller,
The parameter so artificially set in advance does not adapt to the measurement of all depth, will certainly have certain error in this way, cause
The not fully matching of the parameter and actual measurement that set, while needing that parameter is artificially repeatedly arranged, it appears it is very cumbersome
And setting parameter can not reach perfect measurement effect.
Therefore being dimensioned correctly transmission power size is a very crucial step, traditional some instrument and equipment packets
It includes other measurement of correlation fields and all there is such a problem, i.e., how to adjust transmission power in real time, make it in measurement process
In remain an optimal emission state.
The instrument in certain measurement of correlation fields realizes the adjustment of transmission power adaptation by being internally integrated software judgement,
The signal magnitude arrived according to real-time measurement, is in real time adjusted transmission power, is adjusted to a proper range.But
The control of program software also has certain drawbacks, that is, software needs burning again once having modification, for certain instruments
Internal circuit cannot just carry out burning once sealing or assembled；Secondly, in certain measuring instrument systems, transmitting
Unit may there is no configuration correlation MCU controllers, artificial increase controller to lose more than gain a little with program software, can use letter
The function that single hardware circuit is completed does not remove design software as far as possible；Be again the integrity problem of software, either single-chip microcontroller also
It is that other control processors will necessarily have integrity problem, for example program fleet crashes, electronic interferences etc., and complete
Hardware circuit compares still gap.
Summary of the invention
The purpose of the present invention is the deficiencies for traditional logging instrument transmission power adaptation setting at present, propose a kind of sense
Logging instrument transmission power adaptation is answered to adjust device.
The technical solution of the present invention is as follows: a kind of induction log tool transmission power adaptation adjusts device, including 8 parallel port AD
Analog-digital converter, the first subtracter, the second adder-subtractor, control word status latch, analog switch resistor network and DDS number
Word frequency synthesizer.The input terminal of first subtracter inputs 8 ideal value signals and respectively by 8 parallel port AD analog-digital converter
8 measured value signals generated, output end are connect with the input terminal of the second adder-subtractor；The output end of second adder-subtractor with
The input terminal of control word status latch connects；The output end of control word status latch respectively with the second adder-subtractor and mould
Quasi- switched resistor network connection, and its control port connects clock control input signal；Analog switch resistor network is as DDS number
The load resistance of word frequency synthesizer output pin Iout；The output end of DDS digital frequency synthesizer is connect with transmit circuit.
Further, the model ADC0804 of 8 parallel port AD analog-digital converters.
Further, the first subtracter includes the full adder U1 and U2 that two models are 74LS283, the A1 of full adder U1
~A4 pin respectively corresponds A1~A4 pin difference of Gao Siwei the signal A4~A7, full adder U2 of input 8 ideal value signals
Low four signal A0~A3 of the ideal value signal of corresponding input 8.First subtracter further include 8 NOR gate circuit U3A, U3B,
U3C, U3D, U4A, U4B, U4C and U4D, 8 measured value signal B0~B7 that 8 parallel port AD analog-digital converters generate are respectively corresponded
Be input to the first input end of NOR gate circuit U4B, the first input end of NOR gate circuit U4D, NOR gate circuit U4C first
Input terminal, the first input end of NOR gate circuit U4A, the first input end of NOR gate circuit U3B, NOR gate circuit U3D
The first input end of one input terminal, the first input end of NOR gate circuit U3C and NOR gate circuit U3A, each NOR gate circuit
The second input terminal connect with the C0 pin of full adder U2.B1~B4 pin of full adder U1 is connected respectively XOR gate electricity
The output end of road U3B, the output end of NOR gate circuit U3D, the output end of NOR gate circuit U3C and NOR gate circuit U3A it is defeated
Outlet, B1~B4 pin of full adder U2 be connected respectively the output end of NOR gate circuit U4B, NOR gate circuit U4D it is defeated
The output end of outlet, the output end of NOR gate circuit U4C and NOR gate circuit U4A.The C0 pin and full adder U2 of full adder U1
The connection of C4 pin, the C0 pin of full adder U2 also connect with ground resistance R1 and power vd D3 respectively, the VCC of full adder U1
The VCC pin of pin and full adder U2 are connect with power vd D3, the GND pin of full adder U1 and the GND pin of full adder U2
It is grounded.
Further, the second adder-subtractor includes the full adder U5 and U6 that two models are 74LS283, full adder U5's
B1~B3 pin is connected respectively S2~S4 pin of full adder U1, the B4 pin ground connection of full adder U5；The B1 of full adder U6
~B3 pin is connected respectively S2~S4 pin of full adder U2, and the B4 pin of full adder U6 and the S1 pin of full adder U1 connect
It connects.The C4 pin of full adder U1 is connect with the input terminal of reverser U9A, and the C0 of the output end and full adder U6 of reverser U9A draws
Foot connection, the C0 pin of full adder U5 connect with the C4 pin of full adder U6, the VCC pin of full adder U5 and full adder U6's
VCC pin is connect with power vd D3, and the GND pin of full adder U5 and the GND pin of full adder U6 are grounded, full adder U5's
C4 pin output carry controls signal C4_CNT.
Further, control word status latch includes the latch U10 and U11 that two models are 74LS573, is latched
D0~D3 pin of device U10 is connected respectively S1~S4 pin of full adder U6, and D4~D7 pin of latch U10 is right respectively
S1~S4 pin of full adder U5 should be connected, Q0~Q7 pin of latch U10 is connected respectively D0~D7 of latch U11
Pin.The Q0 pin of latch U11 is connect with the A1 pin of one end of resistance R26 and full adder U6 respectively, latch U11's
Q1 pin is connect with the A2 pin of one end of resistance R25 and full adder U6 respectively, the Q2 pin of latch U11 respectively with resistance
The connection of the A3 pin of one end of R24 and full adder U6, the Q3 pin of latch U11 respectively with one end of resistance R23 and complete
The A4 pin of device U6 is added to connect, the Q4 pin of latch U11 connects with the A1 pin of one end of resistance R22 and full adder U5 respectively
It connects, the Q5 pin of latch U11 is connect with the A2 pin of one end of resistance R21 and full adder U5 respectively, the Q6 of latch U11
Pin is connect with the A3 pin of one end of resistance R20 and full adder U5 respectively, the Q7 pin of latch U11 respectively with resistance
One end of R19 and the A4 pin connection of full adder U5；The other end of resistance R19 is connect with power vd D3, resistance R20~R26
The other end with ground resistance R29 and carry control signal C4_CNT connect.The OE pin and latch of latch U10
The OE pin of U11 is connect with carry control signal C4_CNT, the VCC pin of latch U10 and the VCC pin of latch U11
It is connect with power vd D3, the GND pin of latch U10 and the GND pin of latch U11 are grounded, and the LE of latch U10 draws
Foot is connect with the input terminal of ground resistance R27, clock control input signal and reverser U12A respectively, and reverser U12A's is defeated
Outlet is connect with the LE pin of latch U11.
Further, analog switch resistor network includes an analog switch and 8 concatenated resistance R4~R11, mould
Quasi- switch includes 8 channel switch Y0~Y7, and each channel switch is corresponding to be parallel to a resistance, at the same with other 7 resistance
Series connection；Control terminal K0~K7 of 8 channel switch Y0~Y7 is correspondingly connected with Q0~Q7 pin of latch U11 respectively, simulation
Switch and 8 resistance R4~R11 collectively form an adjustable resistor network Rload, and defeated as DDS digital frequency synthesizer
The load resistance of pin Iout out.
Further, the size of resistance R4~R11 is in binary system progressive relationship, i.e. rear stage resistance is that previous stage resistance is big
Small twice.
Further, the main control chip model AD9831 of DDS digital frequency synthesizer.
The beneficial effects of the present invention are:
(1) present invention is combined into 8 the first subtracters and second by 4 tetrad carrylook-ahead adders and adds
Subtracter, is converted into digital quantity for the analog quantity of measuring signal, finds out the difference between ideal value by the first subtracter, so
Afterwards according to the size of difference, suitable control word is calculated by the second adder-subtractor, control analog switch resistor network Rload's
Size adjusts the size of transmission power with this.
(2) present invention adjusts to the output of the first subtracter, is utilized after the end full adder U1 carry-out C4 negates and makees
For the second adder-subtractor carry input, according to the difference of addition subtraction principle with contact so that the second adder-subtractor can be done
Addition can do subtraction again, 4 XOR gate chips (U7, U8, U13, U14) dexterously be omitted very much, so that circuit design is more
Simply, circuit structure is greatly optimized.
(3) pass through setting control since the value after the output of the second adder-subtractor is not only when output but also when input in the present invention
Word state latch processed and a clock control input signal, dexterously realize the lock of the second adder-subtractor output state
It deposits, so that input is independent of each other with output.
(4) the carry control signal C4_CNT that the present invention exports the C4 pin of full adder U5 is as to control word 255
Control is latched, the design on hardware is by carry control signal C4_CNT as the upper of analog switch resistor network control terminal K6~K0
Also it is used as the OE control terminal of 2 latch U10, U11 while pulling down control terminal, adds when the second adder-subtractor executes
When the value obtained after method operation is greater than 255, C4_CNT is high level, and two latch export high resistant, analog switch resistor network
It is 255 that control terminal K7~K0, which exports whole high level, indicates full power transmitting, is avoided because of control when control word is greater than 255
Parameter mismatches so that analog switch tampers the problem of making.
(5) present invention is according to binary system principle, with 8 binary system control words control one by 8 analog switch Y0~
The resistor network of Y7 composition, realization is adjustable within the scope of 0-255, and the size by controlling the resistance changes DDS numerical frequency
The output of synthesizer, the final adjustment for realizing transmission power adaptation.
(6) present invention is matched using reasonable parameter, so that entire circuit system does not need other software control, according to difference
It is worth size adjust automatically transmission power, adjusts principle using the first subtracter difference shifting function and Approach by inchmeal, move closer to
Ideal value, so that adjustment number is less, speed is faster.
(7) present invention is pure hardware circuit design, and all arithmetic operations are executed according to binary arithmetic operation principle,
Execution efficiency is high, highly reliable.
Detailed description of the invention
Fig. 1 show a kind of induction log tool transmission power adaptation adjustment apparatus structure of the offer of the embodiment of the present invention one
Block diagram.
Fig. 2 show the ADC0804 chip schematic diagram of the offer of the embodiment of the present invention one.
Fig. 3 show the first subtraction circuit figure of the offer of the embodiment of the present invention one.
Fig. 4 show the first subtracter and the second adder-subtractor connection relationship circuit diagram of the offer of the embodiment of the present invention one.
Fig. 5 show the first subtracter that the embodiment of the present invention one provides and the second adder-subtractor connection relationship is simplified
Circuit diagram.
Fig. 6 show the control word state latch circuit figure of the offer of the embodiment of the present invention one.
Fig. 7 show the analog switch resistance network circuit figure of the offer of the embodiment of the present invention one.
Fig. 8 show the DDS digital frequency synthesizer circuit diagram of the offer of the embodiment of the present invention one.
Fig. 9 show a kind of induction log tool transmission power adaptation method of adjustment process provided by Embodiment 2 of the present invention
Figure.
Description of symbols:
1-8 parallel port AD analog-digital converters, the first subtracter of 2-, the second adder-subtractor of 3-, 4- control word status latch,
5- analog switch resistor network, 6-DDS digital frequency synthesizer, 7- transmit circuit.
Specific embodiment
Carry out detailed description of the present invention illustrative embodiments with reference to the drawings.It should be appreciated that shown in attached drawing and
The embodiment of description is only exemplary, it is intended that is illustrated the principle and spirit of the invention, and is not limited model of the invention
It encloses.
Embodiment one:
The embodiment of the invention provides a kind of induction log tool transmission power adaptations to adjust device, as shown in Figure 1, including
8 parallel port AD analog-digital converters 1, the first subtracter 2, the second adder-subtractor 3, control word status latch 4, analog switch resistance
Network 5 and DDS digital frequency synthesizer 6.
The input terminal of first subtracter 2 inputs 8 ideal value signals respectively and is produced by 8 parallel port AD analog-digital converters 1
8 raw measured value signals, output end are connect with the input terminal of the second adder-subtractor 3；The output end of second adder-subtractor 3 with
The input terminal of control word status latch 4 connects；The output end of control word status latch 4 respectively with the second adder-subtractor 3 with
And analog switch resistor network 5 connects, and its control port connects clock control input signal；Analog switch resistor network 5 is made
For the load resistance of 6 output pin Iout of DDS digital frequency synthesizer；The output end and transmitting electricity of DDS digital frequency synthesizer 6
Road 7 connects.
The present invention is completed addition and subtraction twice and is operated by way of Digital Logic gate circuit, and passes through latch for state
It latches, keeps current control word, it is defeated as DDS digital frequency synthesizer 6 by one 8 analog switch resistor networks 5
The load resistance of foot Iout out, the resistance sizes are directly proportional to the transmitted waveform voltage swing that it is exported, and controlled with this to reach
Emit the purpose of signal amplitude.Ideal value, measured value, control word etc. are all converted into 8 binary systems by the present invention, due to the present invention
It is the design of devices at full hardware, circuit can only carry out binary algorithm, just as machine language is held with binary code
Row operation is opened final binary system control word to control simulation with reasonable matching after carrying out binary add subtraction
Resistor network 5 is closed, changes the range value of transmitting signal output, to finally change transmission power.
Wherein ideal value indicates to need measured value to be achieved during actual measurement, needs to be manually set in advance, generally
80% for full amplitude 0xFF is advisable, i.e. 255*80%=204 (11001100), in actual application can according to demand into
Row appropriate adjustment.
Measured value indicate induction log tool receiving coil output small-signal by a series of signal condition, amplification with
Filtering, the value exported after sending to 8 parallel port AD analog-digital converters 1, range are 0~255.In the embodiment of the present invention, 8 parallel port AD
Analog-digital converter 1 is used only to calculate control word, does not need very high precision, the actual signal reception processing of induction log tool
Module needs to use high-precision serial AD and is at least 16 or more, does not conflict with it, will not change induction log tool itself
Actual measurement effect.
Control word is the switch level control word of 8 analog switch resistor networks 5, is final after plus and minus calculation twice
It obtains, the control word after each conversion all can carry out state latch by control word state latch 4, for saving current mould
The control word of quasi- switch, in case operation next time.
Therefore, overall thought of the invention is to illustrate that transmission power is big when finding that measured value is greater than ideal value, this
When just need to reduce transmission power；When measured value is less than ideal value, illustrate that transmission power is small, then just needing to increase transmitting
Power.
In the embodiment of the present invention, as shown in Fig. 2, the model ADC0804 of 8 parallel port AD analog-digital converters 1, wherein pin
DB0~DB78 measured value signal B0~B7 of corresponding output.The input of 8 parallel port AD analog-digital converters 1 is exactly to come from induction logging
The output of instrument receiving coil is by signal condition, amplification and filtered signal.
In the embodiment of the present invention, as shown in figure 3, the first subtracter 2 includes the full adder U1 that two models are 74LS283
And A1~A4 pin of U2, full adder U1 respectively correspond Gao Siwei the signal A4~A7, full adder U2 of input 8 ideal value signals
A1~A4 pin respectively correspond low four signal A0~A3 of the ideal value signals of input 8.
First subtracter 2 further includes 8 NOR gate circuits U3A, U3B, U3C, U3D, U4A, U4B, U4C and U4D (present invention
In real-time example, 8 NOR gate circuits constitute XOR gate chip U3, U4 that two models are SN74LS86AD), 8 parallel ports
8 measured value signal B0~B7 that AD analog-digital converter 1 generates respectively correspond the first input for being input to NOR gate circuit U4B
End, the first input end of NOR gate circuit U4D, the first input end of NOR gate circuit U4C, NOR gate circuit U4A it is first defeated
Enter end, the first input end of NOR gate circuit U3B, the first input end of NOR gate circuit U3D, NOR gate circuit U3C first
The first input end of input terminal and NOR gate circuit U3A, C0 of the second input terminal of each NOR gate circuit with full adder U2
Pin connection.
B1~B4 pin of full adder U1 is connected respectively the output end of NOR gate circuit U3B, NOR gate circuit U3D
The output end of output end, the output end of NOR gate circuit U3C and NOR gate circuit U3A, B1~B4 pin difference of full adder U2
It is correspondingly connected with the output end of NOR gate circuit U4B, the output end of NOR gate circuit U4D, the output end of NOR gate circuit U4C and different
The output end of OR circuit U4A.
The carry input C0 pin of full adder U1 is connect with the carry input C4 pin of full adder U2, full adder U2's
C0 pin is also connect with ground resistance R1 and power vd D3 respectively, the VCC pin of full adder U1 and the VCC pin of full adder U2
It is connect with power vd D3, the GND pin of full adder U1 and the GND pin of full adder U2 are grounded.
74LS283 is a tetrad carrylook-ahead adder, and can be used to do add operation can also be used to do subtraction
Operation, its realization principle are as follows: the 7th pin C0 carry input needs to be 0, Yao Shixian 10+7=17, such as A when doing add operation
(1010)+B (0111)=S (1 0001), highest order are that the 9th pin C4 carry output of 1 expression is 1, this decimal representation
For 16, IO output end S4~S1 output 0001.When doing subtraction, according to binary arithmetic operation characteristic, subtraction formula can become
A-B=A+ (B is anti-)+1- (2^n), n 4, Yao Shixian 10-7=3 needs subtrahend 7 to carry out binary system to negate, i.e., 0111 changes into
1000, while the 7th pin C0 carry input needs to be 1, then formula A+ (B is anti-)+1 becomes: 1010+1000+1=10011,
Most significant bits 1 indicate that C4 carry output is 1, finally also need to subtract (2^4)=16.Since the value of carry output is 1, two
System size is equal with 16, therefore casts out, then S4~S1 output 0011, final result 3.
When minuend than subtrahend also than it is small when, i.e. B-A=7-10=-3 be negative, according to reduction formula B-A=B+ (A is anti-)
+ 1- (2^n), similarly 0111+0101+1=01101, highest order are that 0 expression C4 carry output is 0, finally also need to subtract (2
^4)=16, it since highest order is 0, can not be subtracted (2^4) by casting out C4 carry flag to realize at this time, therefore can lead to
Cross after negating S4~S1=1101 plus 1 acquire, 1101 negate after become 0010, add 1 to become 0011, the decimal system 3, C4 into
Position output end is expressed as negative for 0, then final result is -3.
8 binary subtracters i.e. the first subtracter 2 can be constituted by 2 74LS283 full adders U1, U2,
Wherein U1 is responsible for high 4 subtractions, and U2 is responsible for low 4 subtractions, and the 9th pin carry output C4 of U2 is connected to the 7th of U1
Pin carry input C0, as shown in Figure 3；The 7th pin carry input C0 of U2 draws high by VDD3 and does for high level expression
Subtraction.Again since subtrahend needs to do before input inversion operation, and 8 NOR gate circuit U3A, U3B, U3C, U3D, U4A,
U4B, U4C and U4D carry out inversion operation to 8 measured values, and such full adder U1, U2 and XOR gate chip U3, U4 are just
It has been combined into 8 binary subtracters.Ideal value high 4 subtract that measured value is 4 high, and ideal value low 4 subtract measured value low 4
Position, is combined the difference for having reformed into them.At this point, the level height of the 9th pin carry output C4 of U1 is used to represent
First subtracter, 2 output valve it is positive and negative, positive number i.e. ideal value is expressed as when being high level greater than measured value, otherwise is managed for negative
Think that value is less than measured value.
In the embodiment of the present invention, as shown in figure 5, the second adder-subtractor 3 includes the full adder that two models are 74LS283
B1~B3 pin of U5 and U6, full adder U5 are connected respectively S2~S4 pin of full adder U1, the B4 pin of full adder U5
Ground connection；B1~B3 pin of full adder U6 is connected respectively S2~S4 pin of full adder U2, the B4 pin of full adder U6 with
The S1 pin of full adder U1 connects.
The C4 pin of full adder U1 is connect with the input terminal of reverser U9A, and the output end of reverser U9A is with full adder U6's
The connection of C0 pin, the C0 pin of full adder U5 are connect with the C4 pin of full adder U6, the VCC pin and full adder U6 of full adder U5
VCC pin connect with power vd D3, the GND pin of full adder U5 and the GND pin of full adder U6 are grounded, full adder U5
C4 pin output carry control signal C4_CNT.In the embodiment of the present invention, the model SN74HCT04D of phase inverter U9A.
Sign of the carry output C4 of full adder U1 as the first subtracter 2 output difference, when its output is 1,
Expression difference is positive number, otherwise is negative, and by Fig. 4, it can be seen that, the C4 pin output of full adder U1 connects a model
The reverser U9A of SN74HCT04D, in order to make the output of C4 reversed, then to NOR gate circuit (U7A, U7B, U7C,
U7D, U8A, U8B, U8C, U8D, U13A, U13B, U13C, U13D, U14A, U14B, U14C and U14D) constitute 4
SN74LS86AD chip inputs.According to exclusive or principle A XOR 0=A, A XOR1=(A is negated), therefore any number and 0 exclusive or
It all remains unchanged, then represents and negate with 1 exclusive or.
First subtracter 2 is anti-by U9A when the carry output C4 of full adder U1 output is 1 after subtraction
Become 0 backward, as one end of XOR gate chip U7, U8 input, the other end is S4~S1 of full adder U1, U2, due to any
Several and 0 exclusive or all remains unchanged, then can't after xor operation in the case that difference is positive after 2 subtraction of the first subtracter
Change the output of S4~S1 of full adder U1, U2.With should full adder U1 carry output C4 output for 0 when, indicate first
The difference that subtracter 2 exports is negative, then the output of the first subtracter 2 needs to add 1 can just obtain really again after negating
Difference.Therefore the carry output C4 level of U1 becomes 1 after reversed, as one end of exclusive or gate device U7, U8 input,
The other end is S4~S1 of full adder U1, U2, since any number and 1 exclusive or all indicate to negate, then the output of the first subtracter 2
Difference be negative in the case where by exclusive or gate device U7, U8 it negate plus 1 after, the exhausted of true difference can be obtained
To value.The present invention does not increase the circuit that volume is to optimize structure, when the first subtracter 2 output difference be negative the case where
Under, 1 is not added after negating to it, actually final result is had no effect on, influences can be ignored in other words, error
It is exactly 1/255.Therefore the output S4 with full adder U1, U2 afterwards is negated by the carry output C4 pin level to full adder U1
~S1 carries out XOR operation, cleverly realizes very much the operation of 8 binary subtractions of ideal value and measured value, exclusive or gate device
The output of U7, U8 are the absolute values of the true difference of ideal value and measured value, and sign can pass through C4 carry output
Low and high level state judges.
After the difference between ideal value and measured value is calculated, next just need to its it is further converted,
It is converted into suitable control word finally to control the adjustment that analog switch resistor network 5 realizes transmission power.Electric-opening on instrument
When work, starting transmission power can be generated, 50% starting transmission power, i.e. initial control word are set as in the embodiment of the present invention
128 (1,000 0000) are set as, as seen in Figure 7, K7~K0 controls pin, and only K7 level pulls up, other 7 pipes
Underfooting sockets ground, and expression highest order K7 is high level, other are low level.
As shown in Figure 4, the difference between the value K7~K0 and ideal value and measured value of original control word carries out addition and subtraction behaviour
Make, is 1 to its Signal signal after reversed when full adder U1 carry output C4 is low level, indicates measured value than reason
Think that value is big, can just make measured value close to ideal value then the needs of initial control word 128 are turned down.The present invention is by U1 carry output C4
Signal signal after reversed is used as the carry input of full adder U6 in the second adder-subtractor 3, due to Signal signal electricity
Putting down is 1, then the second adder-subtractor 3 executes subtraction operation, but needs to negate subtrahend before executing subtraction operation, and due to the
The output of one subtracter 2 has already been through the exclusive or inversion operation of XOR gate chip U7, a U8, negates again to it,
The difference of so the first subtracter 2 output then experienced inversion operation twice, i.e. NOR gate circuit U7A, U7B, U7C, U7D,
U8A, U8B, U8C, U8D, U13A, U13B, U13C, U13D, U14A, U14B, U14C and U14D are inversion operation, input terminal
Signal signal is 1, and any number and 1 exclusive or all indicate to negate, and any number value final after negating twice still maintains not
Become.Therefore for the difference of the first subtracter 2 output after negating operation twice, value still protects change.Following second addition and subtraction
Device 3 executes subtraction operation to the difference that the first subtracter 2 exports.
Conversely, negating rear Signal signal to it is 0 when full adder U1 carry output C4 is high level, the is indicated
One subtracter, 2 difference is positive, i.e., ideal value is greater than measured value, to realize measured value close to ideal value, then control word must increase
Greatly.Signal signal is used as to the carry input of full adder U6, since the Signal signal is 0, then second adds
Subtracter 3 executes add operation.Again due to the input terminal of NOR gate circuit U7A, U7B, U7C, U7D, U8A, U8B, U8C and U8D
Signal is 0, and any number and 0 exclusive or all remain unchanged, similarly NOR gate circuit U13A, U13B, U13C, U13D, U14A,
U14B, U14C and U14D are also such.Therefore the difference of the first subtracter 2 output by twice with after 0 XOR operation not yet
The size of change value, following second adder-subtractor 3 execute add operation, add operation to the difference that the first subtracter 2 exports
Two numbers are directly added.
Therefore regardless of the second adder-subtractor 3 executes add operation or subtraction, U7A, U7B, U7C, U7D, U8A,
4 XOR gate chips that U8B, U8C, U8D, U13A, U13B, U13C, U13D, U14A, U14B, U14C and U14D are constituted not shadows
The output of 2 result of the first subtracter is rung, then these final NOR gate circuits can omit, such as Fig. 5 institute after circuit reduction
Show.
Second adder-subtractor 3 is before executing operation, it is also necessary to do fuzzy algorithmic approach to the difference (S7~S0) of the first subtracter 2
Processing, i.e. shifting function, because the difference of the first subtracter 2 can not be directly reciprocity with the difference of control word, if without
It is chaotic that displacement probably will appear control.
For example, actual measured value 180, ideal measured value is 204, then first in the case that original control word is 128
The difference that subtracter 2 exports is 24, practical to survey if be directly added after obtaining the new output of control word 152 24 with 128
Magnitude may will become 180* (128+24)/128=213.Actual measured value is bigger than ideal value, and then control word is done subtract again
Method operation, generating new control word is 152- (213-204)=143；Repeatedly by 4 operations finally can be realized measured value with
Ideal value is consistent (difference is less than 1).
For another example when actual measured value is 250, ideal measured value is 204, then the difference of the first subtracter 2 output is
45, if directly being added to obtain new control word output to be 83 with 128 45；So actual measured value may will become 250*
83/128=162, at this moment measured value is again less than normal for ideal value, therefore again increases control word, obtains new
Control word 83+ (204-162)=125；When control word is 125, measured value then becomes 244.Going down so again and again needs
Measured value and ideal value could be made close after having carried out ten secondary operations even more several times, it is comparatively very complicated.
In order to reduce the number of operation, the difference that the first subtracter 2 exports move to right the bit manipulation i.e. difference divided by 2
It inputs to the second adder-subtractor 3 again afterwards and executes addition and subtraction operation.For example, initial control word is 128, measured value 250, ideal is surveyed
Magnitude is 204, and the difference 45 that the first subtracter 2 exports is halved and becomes 22, initial control word 128 obtains new control after subtracting 22
Word processed is 106, and finally calculating measured value should be 207 or so, therefore only needs to adjust once or can be achieved with measured value 2 times and connect
Nearly ideal value, compared to having greatly improved in the past.
Specific practice of the operation that first subtracter 2 output difference halves on hardware circuit is exactly to cast out in full adder U2
Lowest order S1, then S2 replace S1, S3 replace S2, and so on carry out shifting function after as second add adder 3 it is defeated
Enter.As shown in figure 5, the input terminal end highest order B4 of U5 is grounded, B3, B2, B1 meet S4, S3, S2 of U1 respectively；B4, B3 of U6,
B2, B1 meet the S1 of U1, S4, S3, S2 of U2 respectively.
In the embodiment of the present invention, the second adder-subtractor 3 execute arithmetic operation after output control word both when output again when
Input, it is therefore desirable to by its state latch, so that input is independent of each other with output.As shown in fig. 6, control word status latch 4
It is the latch U10 and U11 of 74LS573 including two models, D0~D3 pin of latch U10 is connected respectively complete add
D4~D7 pin of S1~S4 pin of device U6, latch U10 is connected respectively S1~S4 pin of full adder U5, latch
Q0~Q7 pin of U10 is connected respectively D0~D7 pin of latch U11.
The Q0 pin of latch U11 is connect with the A1 pin of one end of resistance R26 and full adder U6 respectively, latch
The Q1 pin of U11 is connect with the A2 pin of one end of resistance R25 and full adder U6 respectively, the Q2 pin difference of latch U11
It is connect with the A3 pin of one end of resistance R24 and full adder U6, the Q3 pin of latch U11 one end with resistance R23 respectively
And the A4 pin connection of full adder U6, the Q4 pin of the latch U11 A1 with one end of resistance R22 and full adder U5 respectively
Pin connection, the Q5 pin of latch U11 are connect with the A2 pin of one end of resistance R21 and full adder U5 respectively, latch
The Q6 pin of U11 is connect with the A3 pin of one end of resistance R20 and full adder U5 respectively, the Q7 pin difference of latch U11
It is connect with the A4 pin of one end of resistance R19 and full adder U5；The other end of resistance R19 is connect with power vd D3, resistance R20
The other end of~R26 is connect with ground resistance R29 and carry control signal C4_CNT.
The OE pin of latch U10 and the OE pin of latch U11 are connect with the carry of U5 control signal C4_CNT, are locked
The VCC pin of storage U10 and the VCC pin of latch U11 are connect with power vd D3, the GND pin of latch U10 and latch
The GND pin of device U11 is grounded, the LE pin of latch U10 respectively with ground resistance R27, clock control input signal and
The input terminal of reverser U12A connects, and the output end of reverser U12A is connect with the LE pin of latch U11, therefore the LE of U10
It holds opposite each other with both the end LE of U11 level.In the embodiment of the present invention, the model SN74HCT04D of phase inverter U12A.
As shown in fig. 6, when system initial power-on, the 2nd pin LE of latch U10 due to there is power vd D3 pull-up,
For high level, latch U10 work is equal in normal mode, input with output, and since the end LE of latch U11 is low electricity
Flat, then its output be in latch mode, and original state control word X0 is (K7~K0=10000000) initially, i.e., state by
It pulls up pull down resistor R19~R26 to determine, is connected to the A4~A1 input terminal and 8 analog switch resistance of full adder U5, U6
Switch control terminal Y7~Y0 of network 5.Later when the 2nd pin LE of latch U10 is low level, pin Q7~Q1 output
State latch and remain unchanged, at this point, input terminal of the state output to latch U11, due to the LE pin of latch U11
Level be negated after become high level, latch U11 work inputs and the level such as output, then latch in normal mode
U10 latch mode control word X1 be treated as control word K7~K0 be connected to full adder U5, U6 A4~A1 input terminal and 8
Switch control terminal Y7~Y0 of analog switch resistor network 5, the detailed control when C4_CNT is low level are closed with latch mode
System can be found in shown in table 1.
Table 1
The end LE of latch U10 can be controlled with individual I/O port, can also be inputted with clock, in the embodiment of the present invention
It is controlled using clock control input signal.The end the LE level of latch U10 is input to the 2nd of latch U11 after negating and draws
Foot LE*, and when the LE of latch U10 is high level, K7~K0 is then remained unchanged, when the LE of latch U10 is low level,
The output state of second adder-subtractor 3 is correctly exported to K7~K0, and a high level of LE adds a low level state i.e.
Complete primary adjustment.LE conversion frequency can choose between 1HZ-10HZ, indicate the number of whole system adjustment operation in one second,
Maximum adjustment number of the invention does not exceed 10 times, if first measured value and ideal value are closer, the number of adjustment is fewer；
When first measured value is much smaller than the half of ideal value, the number of adjustment is also few instead.
As shown in Figures 5 and 6, the carry-out C4 end output carry of full adder U5 controls signal in the second adder-subtractor 3
C4_CNT, the OE that 2 latch U10, U11 are also used as while pulling down control terminal by the pull-up as K6~K0 are controlled
End processed, when 3 output valve of the second adder-subtractor is less than or equal to 255, C4_CNT is low level, and latch U10, U11 are worked normally
Operation；When the second adder-subtractor output valve is greater than 255, C4_CNT is high level, and the output of latch U10, U11 at this time is height
It is unrelated with latch output to be equivalent to the breaking i.e. K7~K0 state of latch U10, U11 output for resistance state.
The size that transmission power most starts is 50%, i.e., control word is 128, then the state that K7~K0 most starts should be
10000000, drop-down is pulled up to complete this function by resistance R19~R26 on hardware circuit.C4_CNT is as the upper of K6~K0
Drawing control terminal is pulled down, since no matter the result of which kind of situation output is always less than 255 for the first time operation of the second adder-subtractor 3
, then carry control signal C4_CNT is low level certainly, K6~K0 is low level, ensures that starting transmission power control
Word K7~K0 processed is in 10000000 states.It is ideal to reach only when initial measurement is fewer than the half of ideal value
Value is in other words closer to ideal value, and control word can be equal to or more than 256 after operation several times, the carry of the second adder-subtractor 3
Output end C4 exports high level, then C4_CNT is also high level, two latch export high resistant, and K6~K0 pull-up is high electricity
It is flat, therefore K7~K0 all gets higher level 11111111, the power control word decimal system is 255, and hereafter transmission power is constantly in
Emission state at full capacity.
If without this design of C4_CNT, the control of system is likely to cause confusion.For example, when original control word is
In the case where 128, ideal value 204, actual measured value 80, measured value is also smaller than the half of ideal value, then by several times
After conversion, the final control word calculated can achieve binary one 01000110, the decimal system 326, and highest order is 1 table
Show that U5 carry output C4 level is high level, which is much larger than the big of the decimal system 255 of maximum 8 control words 11111111
It is small, if still using the least-significant byte of 101000110 (decimal systems 326) as new control word, 8 new control words
It is 01000110, the decimal system 70 is also smaller than initial 128, it is clear that undesirable, correct way is direct full power hair
It penetrates.Because measuring signal is strictly very faint, even if transmission power at full capacity sometimes under conditions of certain extreme
In the case of, it is still also difficult to ensure and reaches ideal measured value, at this moment only need transmission power being set as maximum.Therefore when the
When the power control word of two adder-subtractors 3 output is greater than 255, pass through the high level of the carry output C4 of the second adder-subtractor 3
State cleverly prohibits the output of 2 latch very much, while having drawn high the level of K6~K0 again, so that final K7~K0 is defeated
It is all high level out, the transmitting of system full power guarantees that the signal received is in optimum state.At the same time, in measurement process
In when the second adder-subtractor 3 output power control word be less than or equal to 255 when, then carry output C4 be low level, K7
The particular state of~K0 becomes to be equal to the output of the second adder-subtractor 3 by the output control of 2 latch, level state again
Value.
Detailed operation truth table is referring to 2~table of table 5:
Table 2
| Power control word | Ideal value | Measured value | The output of first subtracter | The output of second addition and subtraction | Latch exports control word |
| 128 | 204 | 50 | 154 | 128+77=205 | 205 |
| Power control word | Ideal value | Measured value | The output of first subtracter | The output of second addition and subtraction | Latch exports control word |
| 205 | 204 | 80 | 124 | 205+62=267 | 255 |
| Power control word | Ideal value | Measured value | The output of first subtracter | The output of second addition and subtraction | Latch exports control word |
| 255 | 204 | 100 | 104 | 255+52=307 | 255 |
Table 3
Table 4
| Power control word | Ideal value | Measured value | The output of first subtracter | The output of second addition and subtraction | Latch exports control word |
| 128 | 204 | 180 | 24 | 128+12=140 | 140 |
| Power control word | Ideal value | Measured value | The output of first subtracter | The output of second addition and subtraction | Latch exports control word |
| 140 | 204 | 196 | 8 | 140+4=144 | 144 |
| Power control word | Ideal value | Measured value | The output of first subtracter | The output of second addition and subtraction | Latch exports control word |
| 144 | 204 | 202 | 2 | 144+1=145 | 145 |
| Power control word | Ideal value | Measured value | The output of first subtracter | The output of second addition and subtraction | Latch exports control word |
| 145 | 204 | 203 | 1 | 145+0=145 | 145 |
Table 5
In the embodiment of the present invention, as shown in fig. 7, analog switch resistor network 5 includes an analog switch and 8 series connection
Resistance R4~R11, analog switch includes 8 channel switch Y0~Y7, and each channel switch correspondence is parallel to a resistance, together
When connect with other 7 resistance；Q0~Q7 of the control terminal K0~K7 of 8 channel switch Y0~Y7 respectively with latch U11 draws
Foot is correspondingly connected with, and analog switch and 8 resistance R4~R11 collectively form an adjustable resistor network Rload, and as DDS
The load resistance of 6 output pin Iout of digital frequency synthesizer.
The size of resistance R4~R11 is in binary system progressive relationship, i.e. rear stage resistance is twice of previous stage resistance sizes.
In the embodiment of the present invention, the main control chip model AD9831 of DDS digital frequency synthesizer 6, peripheral circuit and
Its connection relationship with adjustable resistor network Rload is as shown in figure 8, since the connection relationship of its peripheral circuit belongs to existing skill
Art, details are not described herein.
To keep technical solution of the present invention clearer, complete, now the induction that embodiment one provides is surveyed with embodiment two
It offsets method corresponding to well instrument transmission power adaptation adjustment device to be described in detail, it is intended to further illustrate that embodiment one provides
Induction log tool transmission power adaptation adjustment device operation principle and process.
Embodiment two:
The embodiment of the invention provides a kind of induction log tool transmission power adaptation methods of adjustment, as shown in figure 9, including
Following steps S1~S10:
S1, conditioning amplification filtering is carried out to the signal of induction log tool receiving coil output, turned by 8 parallel port AD moduluses
Filtered measuring signal is amplified in parallel operation acquisition conditioning, and inputs the first subtracter after being converted into 8 measured value signals.
The conditioning filtering and amplifying circuit that conditioning amplification filtering is carried out to receiving coil output signal is induction logging instrument sheet
Body is included, and the measuring signal need to be only introduced in the embodiment of the present invention.
S2, in the first subtracter using 8 of setting ideal value signals as minuend, using 8 measurement signal values as
After subtrahend and step-by-step negate, carries out subtraction and obtain 8 potential difference values.
Before the first subtracter does subtraction, step-by-step inversion operation is done to subtrahend i.e. 8 measurement signal value, utilizes exclusive or
Gate circuit will carry out again subtraction after its every and 1 progress XOR operation.
In the embodiment of the present invention, 80% i.e. 204 of general power 255 can be previously set into 8 ideal value signals, secondly into
It is made as 11001100.The 8 potential difference values that operation obtains in the first subtracter can just be born, and sign symbol can pass through full adder U1
The 9th pin carry output C4 differentiate.
S3, judge whether ideal value is equal to measured value according to 8 potential difference values, if then completing to induction log tool transmission power
Adaptive adjustment, otherwise enter step S4.
S4, judge whether ideal value is greater than measured value according to 8 potential difference values, if then entering step S5, otherwise enter step
S6。
The 9th pin carry output C4 level of full adder U1 is also inputted as the carry of the second adder-subtractor after negating,
The differentiation for doing plus and minus calculation, after the end C4 negates be high level when, execute subtraction operation；It is on the contrary then execute add operation.Cause
This if ideal value is greater than measured value, controls the high-order carry flag pin of full adder U1 in the first subtracter in step s 4
The output of C4 is 1, enters step S5；If ideal value is less than measured value, control full adder U1 in the first subtracter it is high-order into
The output of bit flag pin C4 is 0, enters step S6.
S5, the second adder-subtractor will be inputted after 8 potential difference value shifting functions, and uses 8 old controls in the second adder-subtractor
Word processed adds low 7 differences, obtains 8 new control words, enters step S7.
S6, the second adder-subtractor will be inputted after 8 potential difference value shifting functions, and uses 8 old controls in the second adder-subtractor
Word processed subtracts low 7 differences, obtains 8 new control words, enters step S7.
In step S5 and S6, fuzzy algorithmic approach processing, i.e. shifting function are done to the difference of the first subtracter output, cast out minimum
Position, it is then high-order mobile to low level, it indicates numerically divided by 2, the beneficial effect is that the number of adjustment can be reduced, shortens whole
A adjustment time, so that measured value Approach by inchmeal ideal value, rather than the fluctuation up and down between ideal value.
In the embodiment of the present invention, if ideal value is less than measured value, the output of the high-order carry flag pin C4 of full adder U1
It is 0, the first subtracter output valve needs add 1 after negating again, obtain the absolute value of difference, symbol is negative.The present invention is in order not to increasing
No longer add 1 after adding additional circuit, difference to negate, very little is influenced on adjustment.Since difference is negative, the second adder-subtractor needs are done
Subtraction operation, then subtrahend is also required to negate.Therefore it needs once to be negated again after the output valve of the first subtracter negates,
That is output valve experience negates operation with 1 exclusive or twice.Similarly, if ideal value is greater than measured value, the high-order carry flag pin of U1
The output of C4 is 1, and the first subtracter output valve is true difference, and the second adder-subtractor needs to do add operation, and first subtracts
Musical instruments used in a Buddhist or Taoist mass output valve by twice with 0 XOR operation.According to the principle of XOR operation, any number and 0 exclusive or can all be remained unchanged, with
1 exclusive or, which is equivalent to, to be negated, and is then equivalent to 1 exclusive or negates twice twice, and any number negates twice is also equivalent to the number still
It remains unchanged.Finally, by the reasonable control to full-adder carry-out input and output, the second addition and subtraction no matter do add operation or
Subtraction is done, the output of the first subtracter can be directly as the input of the second adder-subtractor, therefore can be omitted 4
XOR gate chip amounts to 16 NOR gate circuits.
S7, judge whether new control word is less than or equal to 255, if then entering step S8, otherwise send out induction log tool
Power setting is penetrated as full power transmitting, and terminates the adaptive adjustment to induction log tool transmission power.
By the way that the carry output C4_CNT of full adder U5 in the second adder-subtractor is defeated as the OE of latch U10, U11
Enter end, at the same time the input as the pull-up drop-down of analog switch resistor network control terminal K6~K0 level again.When C4_CNT is 1
When, indicate that new control word is greater than 255, latch U10, U11 are then prohibited to export, and K6~K0 level is raised, induction log tool
Transmission power is arranged to full power transmitting, avoids because control parameter mismatches so that mould when control word is greater than 255
Quasi- switch tampers the problem of making.Conversely, indicating that new control word is less than or equal to 255, latch U10, U11 when C4_CNT is 0
Enabled output, K6~K0 level is enabled to be dragged down, and analog switch resistor network control terminal K7~K0 level is determined by latch output,
Enter step S8.
When there are special circumstances, i.e., when measured value is much smaller than ideal value, the word of the second adder-subtractor output control is greater than
256, since the design and control of C4_CNT directly can set maximum for transmission power, to end automatically the adjustment of this time
Journey.After changing test environment or changing investigation depth, measured value is gradually increased when measured value is also bigger than ideal value,
When i.e. the output of the first subtracter is negative value, C4_CNT level state becomes low level, is restored to normal adjustment week again at this time
Phase, until measured value and ideal value are close.
S8, it is adjusted by the control word that clock control input signal exports control word status latch.
When the clock control input signal of the LE pin of input latch U10 is high level, control word status latch
The control word of output is the control word that last state latches, when the clock control input signal of the LE pin of input latch U10
When for low level, the control word of control word status latch output is the new control word that step S5 or step S6 are obtained.
For example, (Initial Trans are according to general power for initial control word 128 when the adjustment of first time transmission power
50% opens the initial minuend X0 emitted) as the second adder-subtractor, and the difference of the first subtracter output is as the second plus-minus
The subtrahend or addend of musical instruments used in a Buddhist or Taoist mass export new control word X1 after executing signed magnitude arithmetic(al).Due to the difference warp of the first subtracter output
After crossing a shifting function, when which is less than the execution subtraction operation of the 128, therefore second adder-subtractor always, the value X1 of output begins
Be eventually it is positive, with should execute add operation when, the value X1 that the second adder-subtractor exports for the first time is consistently less than 256, therefore not
The second adder-subtractor of pipe execute be addition or subtraction operation, the value X1 of output be all it is authentic and valid, can be directly as simulation
The new control word X1 of resistor network.
New control word X1, which passes through to be latched by latch U10, U11, to be exported, when the 2nd end pin LE of latch U10 is high electricity
Usually, U10 work is exported in normal mode, the level such as the output and input of latch U10 to latch U11 input terminal, and by
It is low level in the 2nd pin LE end level state of latch U11, therefore the end K7~K0 level state is constant.As latch U10
The 2nd end pin LE when being low level, current state is latched in pin Q7~Q0 output, and by the 2nd pin of latch U11
The end LE* level state is high level, and U11 work is in normal mode, the level such as output and input, new control word X1 final output
To the input terminal of analog switch resistor network control terminal K7~K0 and full adder U5, U6, S9 is entered step.
In another example 8 parallel port AD analog-digital converters collect new number when after the change of one or many transmission powers
According to and convert output after again with ideal value carry out subtraction, find out difference, then carry out the adjustment of transmission power.The difference is again
It is secondary to carry out operation output current control word X with the second adder-subtractorN+1To the input terminal of latch U10.Due to latch this moment
The end second pin LE of U10 is low level, in latch mode and exports old control word XN, XN+1It is limited in latch U10
Input side；When the end LE of latch U10 is high level, the level such as latch U10 output and input export XN+1；Latch
U11 is in latch mode, output power word or XN, new control word XN+1It is limited in the input side of latch U11.
When the end LE of latch U10 is again low level, latch U10 latch mode XN+1, latch U11 input and output etc. are electric
Flat, latch U11 exports XN+1, finally by new control word XN+1It exports to resistor network control terminal K7~K0 and full adder
The input terminal of U5, U6, enter step S9.
S9, the size of analog switch resistor network is adjusted according to the control word that control word status latch exports,
Specific adjustment mode are as follows:
8 channel switch Y0 of the corresponding control of the level state of 8 control words exported by control word status latch~
The on-off of Y7, when position a certain in control word is 1, corresponding channel switch control terminal is high level, which disconnects,
When position a certain in control word is 0, corresponding channel switch control terminal is low level, and channel switch closure is realized with this
The resistance value of resistor network Rload changes in the range of 0~255 Ω.Output electricity of the Rload as DDS digital frequency synthesizer
Resistance, the resistance sizes are directly proportional to the voltage waveform that it is exported.
S10, using analog switch resistor network as the load resistance of DDS digital frequency synthesizer output pin Iout, lead to
The output result for crossing DDS digital frequency synthesizer is adjusted the transmission power of induction log tool transmit circuit, return step
S1。
Repeatedly, after operation several times, measured value and ideal value are very close, when difference is less than 1, that is, complete
The process of transmission power adaptation adjustment.
The overall design philosophy of the method for the present invention is: the faint analog signal that receiving coil exports is converted into 8 bit digitals
Signal calculates its difference with ideal value, corresponding with the progress of current power control word after shifting function to convert, and obtains new
Power control word, then by latch export latch, finally export into analog switch resistor network change resistance Rload it is big
It is small, to change the size of transmission power.It is final to realize hair by converting several times and measured value Approach by inchmeal ideal value after adjustment
Penetrate the process of power adaptively adjusted.
Those of ordinary skill in the art will understand that the embodiments described herein, which is to help reader, understands this hair
Bright principle, it should be understood that protection scope of the present invention is not limited to such specific embodiments and embodiments.This field
Those of ordinary skill disclosed the technical disclosures can make according to the present invention and various not depart from the other each of essence of the invention
The specific variations and combinations of kind, these variations and combinations are still within the scope of the present invention.
Claims (8)
1. a kind of induction log tool transmission power adaptation adjusts device, which is characterized in that including 8 parallel port AD analog-digital converters
(1), the first subtracter (2), the second adder-subtractor (3), control word status latch (4), analog switch resistor network (5) and
DDS digital frequency synthesizer (6)；
The input terminal of first subtracter (2) inputs 8 ideal value signals and respectively by 8 parallel port AD analog-digital converter
(1) 8 measured value signals generated, output end are connect with the input terminal of the second adder-subtractor (3)；Second adder-subtractor
(3) output end is connect with the input terminal of control word status latch (4)；The output end of the control word status latch (4)
It is connect respectively with the second adder-subtractor (3) and analog switch resistor network (5), and the connection clock control input of its control port
Signal；Load resistance of the analog switch resistor network (5) as DDS digital frequency synthesizer (6) output pin Iout；Institute
The output end for stating DDS digital frequency synthesizer (6) is connect with transmit circuit (7).
2. induction log tool transmission power adaptation according to claim 1 adjusts device, which is characterized in that described 8
The model ADC0804 of parallel port AD analog-digital converter (1).
3. induction log tool transmission power adaptation according to claim 1 adjusts device, which is characterized in that described first
Subtracter (2) includes the full adder U1 and U2 that two models are 74LS283, and A1~A4 pin of the full adder U1 is right respectively
A1~A4 pin that Gao Siwei the signal A4~A7, full adder U2 of 8 ideal value signals should be inputted respectively corresponds 8 ideals of input
Low four signal A0~A3 of value signal；
First subtracter (2) further includes 8 NOR gate circuit U3A, U3B, U3C, U3D, U4A, U4B, U4C and U4D, described
8 measured value signal B0~B7 that 8 parallel port AD analog-digital converters (1) generate, which are respectively corresponded, is input to NOR gate circuit U4B's
First input end, the first input end of NOR gate circuit U4D, the first input end of NOR gate circuit U4C, NOR gate circuit U4A
First input end, the first input end of NOR gate circuit U3B, the first input end of NOR gate circuit U3D, NOR gate circuit
The first input end of U3C and the first input end of NOR gate circuit U3A, the second input terminal of each NOR gate circuit add with complete
The C0 pin of device U2 connects；
B1~B4 pin of the full adder U1 is connected respectively the output end of NOR gate circuit U3B, NOR gate circuit U3D
The output end of output end, the output end of NOR gate circuit U3C and NOR gate circuit U3A, B1~B4 pin of the full adder U2
It is connected respectively the output end of the output end of NOR gate circuit U4B, the output end of NOR gate circuit U4D, NOR gate circuit U4C
With the output end of NOR gate circuit U4A；
The C0 pin of the full adder U1 is connect with the C4 pin of full adder U2, the C0 pin of the full adder U2 also respectively with connect
The VCC pin of ground resistance R1 and power vd D3 connection, the VCC pin of the full adder U1 and full adder U2 with power vd D3
Connection, the GND pin of the full adder U1 and the GND pin of full adder U2 are grounded.
4. induction log tool transmission power adaptation according to claim 3 adjusts device, which is characterized in that described second
Adder-subtractor (3) includes the full adder U5 and U6 that two models are 74LS283, B1~B3 pin difference of the full adder U5
It is correspondingly connected with S2~S4 pin of full adder U1, the B4 pin ground connection of the full adder U5；B1~B3 of the full adder U6 draws
Foot is connected respectively S2~S4 pin of full adder U2, and the B4 pin of the full adder U6 and the S1 pin of full adder U1 connect
It connects；
The C4 pin of the full adder U1 is connect with the input terminal of reverser U9A, the output end and full adder of the reverser U9A
The C0 pin of U6 connects, and the C0 pin of the full adder U5 is connect with the C4 pin of full adder U6, and the VCC of the full adder U5 draws
The VCC pin of foot and full adder U6 are connect with power vd D3, and the GND pin of the full adder U5 and the GND of full adder U6 draw
Foot is grounded, and the C4 pin output carry of the full adder U5 controls signal C4_CNT.
5. induction log tool transmission power adaptation according to claim 4 adjusts device, which is characterized in that the control
Word state latch (4) includes the latch U10 and U11 that two models are 74LS573, D0~D3 of the latch U10
Pin is connected respectively S1~S4 pin of full adder U6, and D4~D7 pin of the latch U10 is connected respectively entirely
Add S1~S4 pin of device U5, D0~D7 that Q0~Q7 pin of the latch U10 is connected respectively latch U11 draws
Foot；
The Q0 pin of the latch U11 is connect with the A1 pin of one end of resistance R26 and full adder U6 respectively, the latch
The Q1 pin of device U11 is connect with the A2 pin of one end of resistance R25 and full adder U6 respectively, and the Q2 of the latch U11 draws
Foot is connect with the A3 pin of one end of resistance R24 and full adder U6 respectively, the Q3 pin of the latch U11 respectively with resistance
The connection of the A4 pin of one end of R23 and full adder U6, the Q4 pin of the latch U11 respectively with one end of resistance R22 with
And the A1 pin connection of full adder U5, the Q5 pin of the latch U11 respectively with one end of resistance R21 and full adder U5
The connection of A2 pin, the Q6 pin of the latch U11 are connect with the A3 pin of one end of resistance R20 and full adder U5 respectively,
The Q7 pin of the latch U11 is connect with the A4 pin of one end of resistance R19 and full adder U5 respectively；The resistance R19
The other end connect with power vd D3, the other end of the resistance R20~R26 with ground resistance R29 and carry control believe
Number C4_CNT connection；
The OE pin of the latch U10 and the OE pin of latch U11 are connect with carry control signal C4_CNT, the lock
The VCC pin of storage U10 and the VCC pin of latch U11 are connect with power vd D3, the GND pin of the latch U10 and
The GND pin of latch U11 is grounded, and the LE pin of the latch U10 is inputted with ground resistance R27, clock control respectively
The connection of the input terminal of signal and reverser U12A, the output end of the reverser U12A are connect with the LE pin of latch U11.
6. induction log tool transmission power adaptation according to claim 5 adjusts device, which is characterized in that the simulation
Switched resistor network (5) includes an analog switch and 8 concatenated resistance R4~R11, and the analog switch includes 8 logical
Road switch Y0~Y7, each channel switch correspondence is parallel to a resistance, while connecting with other 7 resistance；8 channels
Control terminal K0~K7 of switch Y0~Y7 is correspondingly connected with Q0~Q7 pin of latch U11 respectively, the analog switch and 8
Resistance R4~R11 collectively forms an adjustable resistor network Rload, and as DDS digital frequency synthesizer (6) output pin
The load resistance of Iout.
7. induction log tool transmission power adaptation according to claim 6 adjusts device, which is characterized in that the resistance
The size of R4~R11 is in binary system progressive relationship, i.e. rear stage resistance is twice of previous stage resistance sizes.
8. induction log tool transmission power adaptation according to claim 1 adjusts device, which is characterized in that the DDS
The main control chip model AD9831 of digital frequency synthesizer (6).
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