CN109686725A - Positive temperature coefficient polysilicon resistance structure and its manufacturing method - Google Patents
Positive temperature coefficient polysilicon resistance structure and its manufacturing method Download PDFInfo
- Publication number
- CN109686725A CN109686725A CN201910056882.6A CN201910056882A CN109686725A CN 109686725 A CN109686725 A CN 109686725A CN 201910056882 A CN201910056882 A CN 201910056882A CN 109686725 A CN109686725 A CN 109686725A
- Authority
- CN
- China
- Prior art keywords
- resistance
- polysilicon
- temperature coefficient
- crystal silicon
- positive temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/647—Resistive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of positive temperature coefficient polysilicon resistance structure and its manufacturing method, the electric resistance structure includes several polysilicon cell resistances, each polysilicon cell resistance includes the metallization multi-crystal silicon area changed positioned at non-metallic multi-crystal silicon area of the resistance value in negative temperature coefficient variation of intermediate region and the resistance value positioned at end regions in positive temperature coefficient, and adjacent polysilicon cell resistance is connect with resistance value in the metal wire that positive temperature coefficient changes by the contact hole formed on end regions.Accounting of the manufacturing method by adjusting non-metallic multi-crystal silicon area relative to metallization multi-crystal silicon area makes the resistance value of metallization multi-crystal silicon area be more than or equal to the resistance value of non-metallic multi-crystal silicon area with the negative sense variable quantity of temperature with the positive change amount of temperature.The present invention can evade the limitation of performance of semiconductor device, the positive temperature coefficient polysilicon resistance structure of acquisition higher resistance value in the case where not increasing technique burden and guaranteeing device technology stability, do not sacrifice area.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, in particular to a kind of positive temperature coefficient polysilicon resistance structure and its
Manufacturing method.
Background technique
Semiconductor resistor device is one of most widely used device in semiconductor core flake products, and the temperature characterisitic of resistance exists
It is extremely important in products application.Common resistance has following several.Oxygen is passed through on semiconductor substrate using polycrystalline silicon material
Change layer and the resistance to be formed, referred to as polysilicon (Poly) resistance is isolated.Please refer to Figure 14, the position of diffusion region resistance and polysilicon resistance
It is as follows to set relationship.It from top to bottom successively include P-type silicon substrate 301, N-type diffusion region resistance 302, oxidation by taking P-type silicon substrate as an example
Layer 303 and polysilicon resistance 304 further includes the shallow trench that is formed of 302 periphery of diffusion region resistance on silicon substrate 301 certainly every
From structure 305, the first conductive column 306 connecting with diffusion region resistance 302, and what is connect with polysilicon resistance 304 second are led
Electric column 307.Please refer to Figure 15, the positional relationship of well region resistance and polysilicon resistance is as follows.By taking P-type silicon substrate as an example, from it is lower to
On successively include P-type silicon substrate 401, N-type well region resistance 402, the first fleet plough groove isolation structure 403, oxide layer 404 and polysilicon
Resistance 405 further includes the second fleet plough groove isolation structure 406 that 402 periphery of well region resistance on silicon substrate 401 is formed certainly,
It is distributed in the N-type heavily doped region 407 of 402 end of well region resistance, the first conductive column 408 being connect with N-type heavily doped region 407, with
And the second conductive column 409 being connect with polysilicon resistance 405.Above-mentioned diffusion region resistance and well region resistance, polysilicon resistance do not exist
On silicon substrate, but layer of oxide layer is spaced between silicon substrate, therefore, the characteristic of polysilicon resistance is than diffusion region (ACT)
Resistance and well region (NWell) resistance will be got well, for example, the matching performance and noiseproof feature of polysilicon resistance are superior to diffusion region resistance
With well region resistance.In addition, general polysilicon resistance is divided into non-metallic (unsalicide) poly resistance and metallization
(salicide) two kinds of poly resistance, the former because resistance value it is larger (it is up to a hundred or even thousands of, according to different levels of doping, but overall
Substantially all cry and be lightly doped), and the latter, resistance are typically less than 10 ohms/squares (ohm/sqr), so making it have positive temperature
Coefficient is also impracticable.In polysilicon resistance structure, the plan structure of polysilicon resistance is usually a rectangular shape, and with square
The S-shaped shape that is formed based on shape shape and spiral-shaped etc..Fig. 1 is the non-metallic polysilicon resistance structure of conventional rectangular shape
Overlooking structure diagram, referring to FIG. 1, polysilicon resistance 10 have certain length L and width W rectangular shape, including in
Between region 11 and both ends end regions 12, with virtual boundary line 20 description.Intermediate region 11 is the major part of resistance, and holds
Portion region 12 is intended merely to the coupling part of device connection and generation.The polysilicon resistance 10 of such structure, in-between region 11
Resistance value be far longer than the resistance values of end regions 12.For a certain polysilicon resistance 10, the electricity of end regions 12
Resistance value be it is fixed, the accounting of end regions 12 is determined by the entire length of polysilicon resistance 10.Fig. 2 is certain polysilicon resistance
The curve graph that the resistance value of structure varies with temperature.Three kinds of identical square number (No.of squre) different in width are shown in Fig. 2
The width W of the curve graph that the resistance value of the polysilicon resistance structure of W varies with temperature, the resistance of three kinds of identical square numbers is respectively
2um, 5um and 10um.Wherein abscissa is temperature value, and unit is DEG C that ordinate is the total resistance value of polysilicon resistance structure, single
Position is Ω.Referring to FIG. 2, resistance changes in negative temperature coefficient, i.e., with the liter of temperature value due to the characteristic that polysilicon is lightly doped
Height, resistance value variation on a declining curve.To obtain the positive temperature coefficient resistor structure of higher resistance value, generally pass through above-mentioned expansion
The technique for dissipating area's resistance perhaps well region resistance obtains the disadvantage is that sacrifice precision or area as cost, but ought partly lead
When the critical size of body device is restricted or is very strict to resistance precision requirement, because that can not obtain with positive temperature coefficient
Polysilicon resistance structure and make design be restricted.Therefore, how not increase technique burden and guarantee that device technology is stablized
Degree, do not sacrifice obtain in the case where area higher resistance value positive temperature coefficient polysilicon resistance structure be those skilled in the art urgently
Technical problem to be solved.
Summary of the invention
The technical problem to be solved by the present invention is to overcome the above deficiency, provide a kind of positive temperature coefficient polysilicon electricity
Structure and its manufacturing method are hindered, to evade the limitation of performance of semiconductor device, is not increasing technique burden and is guaranteeing device technology
Stability, the positive temperature coefficient polysilicon resistance structure that higher resistance value is obtained in the case where not sacrificing area.
In order to solve the above technical problem, the present invention provides a kind of positive temperature coefficient polysilicon resistance structure, including it is several
The polysilicon cell resistance of a rectangular shape, each polysilicon cell resistance include the resistance value positioned at intermediate region in negative
What the resistance value of the non-metallic multi-crystal silicon area of temperature coefficient variation and the end regions positioned at both ends changed in positive temperature coefficient
Metallization multi-crystal silicon area, wherein the resistance value of metallization multi-crystal silicon area is more than or equal to non-gold with the positive change amount of temperature
The resistance value of categoryization multi-crystal silicon area is with the negative sense variable quantity of temperature, and adjacent polysilicon cell resistance in end regions by forming
Contact hole and resistance value connect in the metal wire of positive temperature coefficient variation.
Further, positive temperature coefficient polysilicon resistance structure provided by the invention, the positive temperature coefficient polysilicon electricity
Resistance structure both ends are electrically connected by the contact hole and metal wire of end regions and draw to form pin.
In order to solve the above-mentioned technical problem, the present invention also provides a kind of manufacturers of positive temperature coefficient polysilicon resistance structure
Method, comprising the following steps:
The polysilicon cell resistance that several rectangular shapes are formed using polycrystalline silicon material, by each polysilicon unit
Resistance is divided into intermediate region and the end regions positioned at intermediate region both ends；
Resistance value is formed in the nonmetallic of negative temperature coefficient variation in the intermediate region of each polysilicon cell resistance
Change multi-crystal silicon area, forms the metal that resistance value is in positive temperature coefficient variation in the end regions of each polysilicon cell resistance
Change multi-crystal silicon area, the accounting by adjusting non-metallic multi-crystal silicon area relative to metallization multi-crystal silicon area makes the polysilicon that metallizes
The resistance value in area is more than or equal to the resistance value of non-metallic multi-crystal silicon area with temperature with the positive change amount of temperature
Negative sense variable quantity；
Adjacent polysilicon cell resistance is become by the contact hole and resistance value formed in end regions in positive temperature coefficient
The metal wire of change connects, to form the positive temperature coefficient polysilicon resistance structure of integral structure.
Further, the manufacturing method of positive temperature coefficient polysilicon resistance structure provided by the invention, by adjusting polycrystalline
Length ratio of the intermediate region of silicon cell resistance relative to end regions, to adjust non-metallic multi-crystal silicon area relative to metallization
The accounting of multi-crystal silicon area.
Further, the manufacturing method of positive temperature coefficient polysilicon resistance structure provided by the invention, by each institute
The blocking layer of metal silicide covered in polysilicon cell resistance is stated, each polysilicon cell resistance is divided into middle area
The end regions in domain and both ends, wherein end regions and the boundary line of intermediate region are contact interface.
Further, the manufacturing method of positive temperature coefficient polysilicon resistance structure provided by the invention, the metal silication
Object barrier layer is one or more of silicon nitride, silica and silicon oxynitride.
Further, the manufacturing method of positive temperature coefficient polysilicon resistance structure provided by the invention, by each institute
Stating the blocking layer of metal silicide covered in polysilicon cell resistance is mask, and the intermediate region of covering is made to form resistance value in negative
The non-metallic multi-crystal silicon area of temperature coefficient variation, and so that exposed end regions is formed resistance value and change in positive temperature coefficient
Metallization multi-crystal silicon area.
Further, the manufacturing method of positive temperature coefficient polysilicon resistance structure provided by the invention, by exposed
End regions deposited metal silicide forms the metallization multi-crystal silicon area that resistance value is in positive temperature coefficient variation.
Further, the manufacturing method of positive temperature coefficient polysilicon resistance structure provided by the invention, the metal silication
Object is one or more of nickle silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, silication erbium and palladium silicide.
Further, the manufacturing method of positive temperature coefficient polysilicon resistance structure provided by the invention, the polysilicon material
Material is the polysilicon of p-type doping or n-type doping.
Positive temperature coefficient polysilicon resistance structure and its manufacturing method provided by the invention are by the more of a traditional monolith
Crystal silicon electric resistance structure is divided into the fritter polysilicon cell resistance of several rectangular shapes, then by each fritter polycrystalline
Non-metallic multi-crystal silicon area of the silicon cell resistance setting in negative temperature coefficient attribute change and the metal in positive temperature coefficient variation
Change multi-crystal silicon area, the accounting by adjusting non-metallic multi-crystal silicon area relative to metallization multi-crystal silicon area makes the polysilicon that metallizes
The resistance value in area is more than or equal to the resistance value of non-metallic multi-crystal silicon area with temperature with the positive change amount of temperature
Then negative sense variable quantity is connected adjacent polysilicon cell resistance by the metal wire in positive temperature coefficient variation, thus will
Several polysilicon cell resistances form the resistance value of integral structure in the polysilicon resistance structure of positive temperature coefficient variation.With it is existing
There is technology to compare, present invention utilizes the end regions of ignored resistance device under normal circumstances, and pass through metal wire for phase
Adjacent polysilicon cell resistance connection, the specific gravity for keeping end regions shared in entire electric resistance structure increase, it is made to reach certain
After a ratio, the temperature characterisitic for changing entire resistance becomes positive temperature coefficient from negative temperature coefficient.Thus mentioned to designer
A kind of technology stability has been supplied to be better than the positive temperature coefficient obtained in the prior art using diffusion region resistance or well region resistance
The scheme of resistance.Therefore, the limitation that can evade performance of semiconductor device is not increasing technique burden and is guaranteeing that device technology is steady
Fixed degree, the positive temperature coefficient polysilicon resistance structure that higher resistance value is obtained in the case where not sacrificing area.
Detailed description of the invention
Fig. 1 is the overlooking structure diagram of the polysilicon resistance structure of traditional rectangular shape；
Fig. 2 is the curve graph that the resistance value of traditional polysilicon resistance structure varies with temperature；
Fig. 3 is the structural representation in the intermediate region of traditional polysilicon resistance structure covering blocking layer of metal silicide
Figure；
Fig. 4 is the curve graph that the resistance value of the intermediate region of traditional polysilicon resistance structure varies with temperature；
Fig. 5 is resistance value of the end regions of traditional polysilicon resistance structure after metal silicide metallizes with temperature
The curve graph of variation；
Fig. 6 is several the polysilicon cell resistances with negative temperature coefficient being spaced apart in one embodiment of the invention
Structural schematic diagram；
Fig. 7 is to cover blocking layer of metal silicide in the intermediate region of the polysilicon cell resistance of one embodiment of the invention
Structural schematic diagram；
Fig. 8 is the structure in the end regions formation metal silicide layer of the polysilicon cell resistance of one embodiment of the invention
Schematic diagram；
Fig. 9 is that the polysilicon cell resistance of one embodiment of the invention is connected to form one the positive temperature of structure by metal wire
Spend the structural schematic diagram of the polysilicon resistance of coefficient；
Figure 10 is the perspective structure schematic diagram of Fig. 9；
Figure 11 is the simplified structure diagram of Fig. 9；
Figure 12 is the intermediate region for changing polysilicon cell resistance in one embodiment of the invention and the length ratio of end regions
Structural schematic diagram；
Figure 13 is the intermediate region that polysilicon cell resistance is changed simultaneously in one embodiment of the invention and the length of end regions
Degree is than the structural schematic diagram with width ratio；
Figure 14 is the location diagram of diffusion region resistance and polysilicon resistance；
Figure 15 is the location diagram of well region resistance and polysilicon resistance.
Specific embodiment
The present invention is described in detail with reference to the accompanying drawing:
Fig. 3 is the structural representation in the intermediate region covering blocking layer of metal silicide of the non-metallic polysilicon resistance of tradition
Figure.Referring to FIG. 3, in the fabrication process due to polysilicon resistance structure, metal silicide is arranged by region 11 therebetween
Barrier layer 20, to prevent intermediate region 11 from metallizing, and the end regions 12 of exposure are usually that contact hole 13 is arranged through metallic silicon
It is connected after compound metallization by metal wire.Fig. 4 is that the resistance value of the intermediate region of polysilicon resistance structure varies with temperature
Curve graph；Fig. 5 is that resistance value of the end regions of polysilicon resistance structure after metal silicide metallizes varies with temperature
Curve graph.Wherein abscissa be temperature value, unit be DEG C, ordinate be polysilicon resistance structure total resistance value, unit Ω.
The difference is that the temperature value in Fig. 5 is expressed using scientific algorithm method, it is illustrated by taking 1.28E+02 as an example, E is that science counts
Method symbol, meaning are 1.28 × 102Ω.Fig. 4 and Fig. 5 are please referred to, inventor has found that in polysilicon resistance 10
Between the temperature characterisitic of region 11 and end regions 12 be presented opposite trend, polysilicon resistance structure 10 intermediate region 11 due to
The effect of blocking layer of metal silicide 20 and form the nonmetallic silicification area not being metallized, in negative temperature coefficient variation keep
It is constant, and end regions 12 are formed after metal silicide metallizes by metal silication area, metal silication area and nonmetallic silication
The end regions that area has a common boundary, contact hole and connection metal form, because this four part is positive temperature coefficient, end region
Domain 12 generally also changes in positive temperature coefficient, i.e. the resistance value of end regions 12 increases as the temperature rises.It sends out as a result,
Bright people proposes that 12 resistance value of end regions that whether can use polysilicon resistance 10 is obtained in the characteristic of positive temperature coefficient variation
Positive temperature coefficient polysilicon resistance structure.To overcome the technology prejudice in diffusion region resistance and well region resistance, thus using a kind of
New process structure realization do not increase technique burden and guarantees device technology stability, do not sacrifice area in the case where obtain it is higher
The polysilicon resistance structure of the positive temperature coefficient of resistance value.
Fig. 6 to Figure 11 is please referred to, the embodiment of the present invention provides a kind of positive temperature coefficient polysilicon resistance structure 100, including
The polysilicon cell resistance 110 of several rectangular shapes, each polysilicon cell resistance 110 include being located at intermediate region
The resistance value of non-metallic multi-crystal silicon area 111 of the resistance value in negative temperature coefficient variation and the end regions positioned at both ends is in positive temperature
The metallization multi-crystal silicon area 112 of index variation is spent, wherein positive change of the resistance value of metallization multi-crystal silicon area 112 with temperature
Amount is more than or equal to negative sense variable quantity of the resistance value of non-metallic multi-crystal silicon area 111 with temperature, adjacent polysilicon unit
Resistance 110 is connect with resistance value in the metal wire 140 of positive temperature coefficient variation by the contact hole 113 formed in end regions.
Please refer to Fig. 6 to Figure 11, positive temperature coefficient polysilicon resistance structure 100 provided in an embodiment of the present invention, it is described just
140 electricity of contact hole 113 and metal wire that the integrally-built both ends of temperature coefficient polysilicon electric resistance structure 100 pass through end regions
Property connects and draws to form pin.Pin is used to use in the circuits such as semiconductor devices as electric connection.It is connect with pin
Metal wire 140 further enhance integral structure positive temperature coefficient polysilicon resistance structure 100 resistance value in positive temperature
Index variation.
The embodiment of the present invention also provides a kind of manufacturing method of positive temperature coefficient polysilicon resistance structure 100, including following
Step:
Step 201, referring to FIG. 6, forming the polysilicon cell resistance of several rectangular shapes using polycrystalline silicon material
110, each polysilicon cell resistance 110 is divided into intermediate region and end regions positioned at intermediate region both ends.Example
Fig. 6 to Fig. 7 is such as please referred to, by the blocking layer of metal silicide 120 covered in each polysilicon cell resistance 110,
Each polysilicon cell resistance 110 is divided into the end regions at intermediate region and both ends, wherein end regions and centre
The boundary line in region is contact interface.Wherein blocking layer of metal silicide 120 is one in silicon nitride, silica and silicon oxynitride
Kind or more.Wherein polycrystalline silicon material can be the polysilicon of p-type doping, or the polysilicon of n-type doping.Wherein p-type is miscellaneous
The ion of matter can be one or more of phosphorus, arsenic and antimony.The ion of N-type impurity can for one of boron, gallium and indium or
It is several.
Step 202, referring to FIG. 6, forming resistance value in negative in the intermediate region of each polysilicon cell resistance 110
The non-metallic multi-crystal silicon area 111 of temperature coefficient variation, forms electricity in the end regions of each polysilicon cell resistance 110
Resistance value is in the metallization multi-crystal silicon area 112 of positive temperature coefficient variation, by adjusting non-metallic multi-crystal silicon area 111 relative to metal
The accounting for changing multi-crystal silicon area 112 makes the resistance value of metallization multi-crystal silicon area 112 as the positive change amount of temperature is greater than or waits
In non-metallic multi-crystal silicon area 111 resistance value with temperature negative sense variable quantity.Wherein non-metallic multi-crystal silicon area 111 is more
Crystal silicon material self attributes determine that its resistance value changes in negative temperature coefficient, and the resistance value for multi-crystal silicon area 112 of metallizing is in
Positive temperature coefficient variation.Please refer to Figure 12, by adjusting polysilicon cell resistance 110 intermediate region length L relative to end
The length ratio of the length L1 in portion region, for example, keeping L small as far as possible under the conditions of meeting process rule, to adjust non-metallic polycrystalline
Accounting of the silicon area 111 relative to metallization multi-crystal silicon area 112.The middle area of polysilicon cell resistance 110 can also be adjusted simultaneously
The length L in domain relative to the length L1 of end regions length than with whole width ratio, such as former width is W, adjusted
Width is W1, is in the nature adjustment length ratio.
Step 203, Fig. 9 to Figure 11 is please referred to, adjacent polysilicon cell resistance 110 is connect by what is formed in end regions
Contact hole 113 is connect with resistance value in the metal wire 140 of positive temperature coefficient variation, to form the positive temperature coefficient polycrystalline of integral structure
Silicon resistor structure 100.
Referring to FIG. 7, the manufacturing method of positive temperature coefficient polysilicon resistance structure 100 provided in an embodiment of the present invention, leads to
Crossing the blocking layer of metal silicide 120 covered in each polysilicon cell resistance 110 is mask, makes the middle area of covering
Domain forms resistance value and is in the non-metallic multi-crystal silicon area 111 of negative temperature coefficient variation, and exposed end regions is made to form electricity
Resistance value is in the metallization multi-crystal silicon area 112 of positive temperature coefficient variation.
Referring to FIG. 8, the manufacturing method of positive temperature coefficient polysilicon resistance structure 100 provided in an embodiment of the present invention, leads to
It crosses and forms the metallization multi-crystal silicon area that resistance value is in positive temperature coefficient variation in exposed end regions deposited metal silicide 130
112.Wherein, metal silicide 130 is nickle silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, silication erbium and silicon
Change one or more of palladium.
Positive temperature coefficient polysilicon resistance structure 100 provided in an embodiment of the present invention, the metal wire 140 can be single
Metal material or alloy material.Single metal such as metallic copper, aluminium and gold etc..Alloy material such as albronze etc..
Positive temperature coefficient polysilicon resistance structure 100 provided in an embodiment of the present invention is more by several by metal wire 140
Crystal silicon cell resistance 100 cascades, and can form the positive temperature coefficient polysilicon resistance structure 100 of the higher high value of resistance value.
Please refer to Fig. 6 to Fig. 7, the manufacturer of positive temperature coefficient polysilicon resistance structure 100 provided in an embodiment of the present invention
Method, 130 blocking layer of metal silicide 120 of metal silicide are equal to or slightly greater than the centre of polysilicon cell resistance 110
Region.Wherein blocking layer of metal silicide 120 is slightly larger than the intermediate region of polysilicon cell resistance 110, refers to metal silicide
The width direction on barrier layer 120 needs the width W greater than polysilicon cell resistance 110, the purpose is to make intermediate region have compared with
Good coverage rate, the intermediate region to avoid polysilicon cell resistance 110 is exposed and is metallized.Wherein, the length of intermediate region
Spending L can be according to the length computation of blocking layer of metal silicide 120.
Above-mentioned technical proposal in order to better understand the present invention, the embodiment of the present invention provide one group of polysilicon resistance unit
Resistance value, the resistance value of non-metallic multi-crystal silicon area 111 and the total resistance value of metallization multi-crystal silicon area 112 in 110 are with temperature
The experiment of the variation of degree calculates data.This is the high value polysilicon resistance that a unit resistance is 1000 ohms/square numbers, often
It advises in electric resistance structure, which is presented negative temperature coefficient.It is now made into device again according to structure of the invention, is pushed away by model emulation
Relationship such as the following table 1 of resistance and temperature of the point counting from after.Width (W) is 2 microns, and resistance unit intermediate region length (L) is 0.3
Micron.
Table 1
Temperature value is from subzero 40 DEG C, 25 DEG C above freezing and when 85 DEG C of raisings above freezing change, metallization multi-crystal silicon area resistance value, non-
The experimental data table 1 as above that metallization multi-crystal silicon area resistance value and total resistance value vary with temperature.Secondary series can from table 1
Know, metallization 112 resistance value of multi-crystal silicon area is increased with the raising of temperature, and resistance value is with the raised resistance varying-ratio of temperature
(74.72411-48.16769) ÷ (85+40)=0.2125 DEG C (round up and take four effective digitals), that is, be in positive temperature coefficient
Variation, from table 1 third column it is found that the raising of 111 resistance value temperature of non-metallic multi-crystal silicon area and decline, resistance value is with temperature
Spending raised resistance varying-ratio is that (142.8749-159.7988) ÷ (85+40)=- 0.1354 DEG C (rounds up and takes four and have
Effect number), i.e., change in negative temperature coefficient.It follows that the forward resistance value that metallization multi-crystal silicon area 112 varies with temperature becomes
0.2125 DEG C of rate -0.1354 DEG C of rate of negative sense resistance change varied with temperature greater than non-metallic multi-crystal silicon area 111.Pass through
For table 1 it is found that in each temperature, total resistance value is equal to metallization multi-crystal silicon area resistance value and non-metallic multi-crystal silicon area resistance value
Summation, total resistance value increase as the temperature rises, and total resistance value change rate is (217.5991-207.9665) ÷
(85+40)=0.0771 DEG C.(round up and take four effective digitals) changes in positive temperature coefficient.
Positive temperature coefficient polysilicon resistance structure 100 and its manufacturing method provided in an embodiment of the present invention, being will be traditional
One monolith polysilicon resistance is divided into the fritter polysilicon cell resistance 110 of several rectangular shapes, then by each small
The setting of block polysilicon cell resistance 110 is in the non-metallic multi-crystal silicon area 111 of negative temperature coefficient attribute change and in positive temperature system
The metallization multi-crystal silicon area 112 of number variation, by adjusting non-metallic multi-crystal silicon area 111 relative to metallization multi-crystal silicon area 112
Accounting, make metallize multi-crystal silicon area 112 resistance value with temperature positive change amount be more than or equal to it is non-metallic more
The resistance value in crystal silicon area 111 with temperature negative sense variable quantity, then by the metal wire 140 in positive temperature coefficient variation by phase
Adjacent polysilicon cell resistance 110 connects, to be in by the resistance value that several polysilicon cell resistances 110 form integral structure
The polysilicon resistance structure 100 of positive temperature coefficient variation.Present invention utilizes the ends of ignored resistance device under normal circumstances
Portion region, the specific gravity for keeping it shared in entire electric resistance structure increase, make it after reaching some proportion, change entire resistance
Temperature characterisitic become positive temperature coefficient from negative temperature coefficient.A kind of technology stability has thus been provided designers with better than existing
There is the scheme of the resistance of the positive temperature coefficient obtained in technology using diffusion region resistance or well region resistance.Therefore, can evade
The limitation of performance of semiconductor device, in the case where not increasing technique burden and guaranteeing device technology stability, do not sacrifice area
Obtain the positive temperature coefficient polysilicon resistance structure of higher resistance value.
The present invention is not limited to above-mentioned specific embodiment, all made various changes within protection scope of the present invention
And retouching, it is within the scope of the present invention.
Claims (10)
1. a kind of positive temperature coefficient polysilicon resistance structure, which is characterized in that the polysilicon unit including several rectangular shapes
Resistance, each polysilicon cell resistance include the resistance value positioned at intermediate region in the non-metallic of negative temperature coefficient variation
The resistance value of multi-crystal silicon area and the end regions positioned at both ends is in the metallization multi-crystal silicon area of positive temperature coefficient variation, wherein metal
Change multi-crystal silicon area resistance value with temperature positive change amount be more than or equal to non-metallic multi-crystal silicon area resistance value with
The negative sense variable quantity of temperature, adjacent polysilicon cell resistance is by the contact hole that is formed in end regions and resistance value in positive temperature
Spend the metal wire connection of index variation.
2. positive temperature coefficient polysilicon resistance structure as described in claim 1, which is characterized in that the positive temperature coefficient polycrystalline
Silicon resistor structure both ends are electrically connected by the contact hole and metal wire of end regions and draw to form pin.
3. a kind of manufacturing method of positive temperature coefficient polysilicon resistance structure, which comprises the following steps:
The polysilicon cell resistance that several rectangular shapes are formed using polycrystalline silicon material, by each polysilicon cell resistance
It is divided into intermediate region and the end regions positioned at intermediate region both ends；
Resistance value is formed in the non-metallic more of negative temperature coefficient variation in the intermediate region of each polysilicon cell resistance
It is more in the metallization of positive temperature coefficient variation to form resistance value in the end regions of each polysilicon cell resistance for crystal silicon area
Crystal silicon area, the accounting by adjusting non-metallic multi-crystal silicon area relative to metallization multi-crystal silicon area, makes multi-crystal silicon area of metallizing
Resistance value is more than or equal to the resistance value of non-metallic multi-crystal silicon area with the negative sense of temperature with the positive change amount of temperature
Variable quantity；
Adjacent polysilicon cell resistance is changed by the contact hole and resistance value that are formed in end regions in positive temperature coefficient
Metal wire connection, to form the positive temperature coefficient polysilicon resistance structure of integral structure.
4. the manufacturing method of positive temperature coefficient polysilicon resistance structure as described in claim 1, which is characterized in that by adjusting
Length ratio of the intermediate region of polysilicon cell resistance relative to end regions, to adjust non-metallic multi-crystal silicon area relative to gold
The accounting of categoryization multi-crystal silicon area.
5. the manufacturing method of positive temperature coefficient polysilicon resistance structure as claimed in claim 3, which is characterized in that by every
The blocking layer of metal silicide covered in a polysilicon cell resistance, each polysilicon cell resistance is divided into
Between region and both ends end regions, wherein end regions and the boundary line of intermediate region are contact interface.
6. the manufacturing method of positive temperature coefficient polysilicon resistance structure as claimed in claim 5, which is characterized in that the metal
Silicide barrier layer is one or more of silicon nitride, silica and silicon oxynitride.
7. the manufacturing method of positive temperature coefficient polysilicon resistance structure as claimed in claim 3, which is characterized in that by every
The blocking layer of metal silicide covered in a polysilicon cell resistance is mask, and the intermediate region of covering is made to form resistance value
In the non-metallic multi-crystal silicon area that negative temperature coefficient changes, and exposed end regions is made to form resistance value in positive temperature coefficient
The metallization multi-crystal silicon area of variation.
8. the manufacturing method of positive temperature coefficient polysilicon resistance structure as claimed in claim 7, which is characterized in that by sudden and violent
The end regions deposited metal silicide of dew forms the metallization multi-crystal silicon area that resistance value is in positive temperature coefficient variation.
9. the manufacturing method of positive temperature coefficient polysilicon resistance structure as claimed in claim 8, which is characterized in that the metal
Silicide is one or more of nickle silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, silication erbium and palladium silicide.
10. the manufacturing method of positive temperature coefficient polysilicon resistance structure as claimed in claim 3, which is characterized in that described more
Crystal silicon material is the polysilicon of p-type doping or n-type doping.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910056882.6A CN109686725B (en) | 2019-01-22 | 2019-01-22 | Positive temperature coefficient polysilicon resistance structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910056882.6A CN109686725B (en) | 2019-01-22 | 2019-01-22 | Positive temperature coefficient polysilicon resistance structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109686725A true CN109686725A (en) | 2019-04-26 |
| CN109686725B CN109686725B (en) | 2021-10-01 |
Family
ID=66192650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910056882.6A Active CN109686725B (en) | 2019-01-22 | 2019-01-22 | Positive temperature coefficient polysilicon resistance structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109686725B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433075A (en) * | 2002-01-10 | 2003-07-30 | 精工电子有限公司 | Semiconductor and its manufacture |
| US20140008765A1 (en) * | 2011-08-01 | 2014-01-09 | Fairchild Korea Semiconductor Ltd. | Poly silicon resistor, reference voltage circuit comprising the same, and manufacturing method of poly silicon resistor |
| CN104037058A (en) * | 2013-03-08 | 2014-09-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN105140222A (en) * | 2014-05-30 | 2015-12-09 | 台湾积体电路制造股份有限公司 | Integrated circuit and method of fabricating the same |
| CN105493234A (en) * | 2013-09-27 | 2016-04-13 | 英特尔公司 | Methods of forming tuneable temperature coefficient for embedded resistors |
| CN107104134A (en) * | 2016-02-19 | 2017-08-29 | 三重富士通半导体股份有限公司 | The manufacture method of semiconductor device and semiconductor device |
-
2019
- 2019-01-22 CN CN201910056882.6A patent/CN109686725B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433075A (en) * | 2002-01-10 | 2003-07-30 | 精工电子有限公司 | Semiconductor and its manufacture |
| US20140008765A1 (en) * | 2011-08-01 | 2014-01-09 | Fairchild Korea Semiconductor Ltd. | Poly silicon resistor, reference voltage circuit comprising the same, and manufacturing method of poly silicon resistor |
| CN104037058A (en) * | 2013-03-08 | 2014-09-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN105493234A (en) * | 2013-09-27 | 2016-04-13 | 英特尔公司 | Methods of forming tuneable temperature coefficient for embedded resistors |
| CN105140222A (en) * | 2014-05-30 | 2015-12-09 | 台湾积体电路制造股份有限公司 | Integrated circuit and method of fabricating the same |
| CN107104134A (en) * | 2016-02-19 | 2017-08-29 | 三重富士通半导体股份有限公司 | The manufacture method of semiconductor device and semiconductor device |
Non-Patent Citations (1)
| Title |
|---|
| "《金属线材电阻系数试验方法》国家标准讨论会在津召开 ", 《冶金标准化与质量》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109686725B (en) | 2021-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7696603B2 (en) | Back end thin film capacitor having both plates of thin film resistor material at single metallization layer | |
| US20070262413A1 (en) | E-fuse and method for fabricating e-fuses integrating polysilicon resistor masks | |
| US4948747A (en) | Method of making an integrated circuit resistor | |
| US9461038B2 (en) | Semiconductor device with resistance circuit | |
| US20060255404A1 (en) | Semiconductor resistance element and fabrication method thereof | |
| CN110364507A (en) | Semiconductor element | |
| US10534045B2 (en) | Vertical hall-effect sensor for detecting two-dimensional in-plane magnetic fields | |
| US9496250B2 (en) | Tunable scaling of current gain in bipolar junction transistors | |
| CN104037173B (en) | Polyresistor structure and forming method thereof | |
| US6621404B1 (en) | Low temperature coefficient resistor | |
| CN113644116B (en) | Grid and source parallel adjustable resistor type super junction power device and manufacturing method thereof | |
| US7034653B2 (en) | Semiconductor resistor | |
| CN109686725A (en) | Positive temperature coefficient polysilicon resistance structure and its manufacturing method | |
| CN109686724A (en) | Positive temperature coefficient polysilicon resistance structure and its manufacturing method | |
| US20070176260A1 (en) | Active area resistors and methods for making the same | |
| US5946595A (en) | Method of forming a local interconnect between electronic devices on a semiconductor substrate | |
| CN102122651B (en) | Semiconductor device and manufacture method thereof | |
| CN107895758A (en) | Thin film resistor element and method for manufacturing the same | |
| CN100479162C (en) | Semiconductor component and its making method | |
| CN209963056U (en) | Semiconductor resistor and CMOS device | |
| JP2867934B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN107026164B (en) | Switch improvement using layout optimization | |
| CN105990353B (en) | Memory construction and its manufacturing method | |
| US11646137B2 (en) | Resistor circuit | |
| JP3160954B2 (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |