CN109686721A - A kind of Thick film multilayer wire structures of low thermal resistance and preparation method thereof - Google Patents
A kind of Thick film multilayer wire structures of low thermal resistance and preparation method thereof Download PDFInfo
- Publication number
- CN109686721A CN109686721A CN201910100056.7A CN201910100056A CN109686721A CN 109686721 A CN109686721 A CN 109686721A CN 201910100056 A CN201910100056 A CN 201910100056A CN 109686721 A CN109686721 A CN 109686721A
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- Prior art keywords
- thick film
- substrate
- via hole
- medium
- thermal resistance
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- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 239000004020 conductor Substances 0.000 claims abstract description 54
- 238000003466 welding Methods 0.000 claims abstract description 28
- 239000000463 material Substances 0.000 claims abstract description 10
- 238000001465 metallisation Methods 0.000 claims abstract description 9
- 238000003854 Surface Print Methods 0.000 claims description 15
- 239000011159 matrix material Substances 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 2
- 229910052760 oxygen Inorganic materials 0.000 claims 2
- 239000001301 oxygen Substances 0.000 claims 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- 239000004411 aluminium Substances 0.000 claims 1
- 229910052790 beryllium Inorganic materials 0.000 claims 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 claims 1
- 230000003252 repetitive effect Effects 0.000 claims 1
- 230000017525 heat dissipation Effects 0.000 abstract description 10
- 230000005855 radiation Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 44
- 238000000034 method Methods 0.000 description 8
- 230000008719 thickening Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Abstract
Thick film multilayer wire structures of a kind of low thermal resistance of the invention and preparation method thereof, the technical issues of Thick film multilayer place-and-route product high-power chip poor heat radiation can be solved.Including substrate, the substrate is thick film substrate, and the base lower surface printed back metallization material, the metallization material is thick film conductor, the upper surface of base plate printing inner conductor and top layer welding zone；The inner conductor is thick film conductor, and the inner conductor is N number of, 1≤N≤3, and printed medium between the inner conductor, the medium is thick film dielectric；Thick film via hole conductor is arranged on the via hole for longitudinally disposed via hole on the medium；The top layer welding zone is thick film welding conductors, top layer welding zone upper surface over-assemble power chip.A kind of Thick film multilayer circuit board of low thermal resistance of the invention provides effective heat dissipation channel by array via structure for hydrid integrated circuit power chip, realizes the technical goal that power chip thermal dissipating path thermal resistance is reduced on Thick film multilayer circuit board.
Description
Technical field
The present invention relates to hydrid integrated circuit multilayer wiring fields, and in particular to a kind of Thick film multilayer wire bond of low thermal resistance
Structure and preparation method thereof.
Background technique
Power chip temperature rise is the important parameter for examining thick film hybrid integrated circuit designed reliability, mainly examines circuit
After being powered on work to stable state, circuit internal power chip temperature rise situation.In thick film hybrid integrated circuit, power chip is generallyd use
Welding procedure is soldered on ceramic substrate thick film conductor, and ceramic substrate passes through welding procedure again and is soldered on metal-packaged shell,
To form the heat dissipation channel of power chip.
With the miniaturization demand of thick film hybrid integrated circuit, Thick film multilayer wiring technique is using more and more extensive.
Thick film multilayer wiring technique will be mainly dielectrically separated from using dielectric layer between each layer conductor, and thick film dielectric layer thermal resistance is larger,
Therefore the thermal resistance that Thick film multilayer is routed upper power chip heat dissipation channel will increase, higher so as to cause the final temperature rise of power chip.
Under normal circumstances, designer often separates power section and signal section to solve heat dissipation problem, and limited for layout space
Small-size product, then be not suitable for.
Summary of the invention
A kind of Thick film multilayer wire structures and preparation method thereof of low thermal resistance proposed by the present invention, can solve Thick film multilayer cloth
The technical issues of line product high-power chip poor heat radiation.
To achieve the above object, the invention adopts the following technical scheme:
A kind of Thick film multilayer wire structures of low thermal resistance, including thick film substrate, the thick film substrate lower surface printed back metal
Change material；Successively print inner conductor, medium, interlevel via (via), top layer welding zone and assembling function in the thick film substrate upper surface
Rate chip；
Furthermore alumina substrate can be selected in the preferred beryllium oxide substrate of thick film substrate；
The back metal material is thick film conductor；
The inner conductor of the thick film substrate upper surface printing is thick film conductor；
The medium of the thick film substrate upper surface printing is thick film dielectric；
The interlevel via of the thick film substrate upper surface printing is thick film via hole conductor；
The top layer welding zone of the thick film substrate upper surface printing is thick film welding conductors；
Further, the inner conductor, domain structure should have following characteristics: power chip corresponding internal layer vertically downward
Conductor, figure coverage area should be not less than power chip projected area；
Further, the medium, domain structure should have the following characteristics that complementary with corresponding interlevel via, that is, print
The position medium windowing in hole, remaining position is paved with medium；
Further, the via hole, domain structure should have the following characteristics that power chip corresponding position vertically downward, mistake
Hole is arranged in a matrix；Array via hole realizes that interlayer interconnects between top layer welding zone, inner conductor, and it is logical to provide power chip heat dissipation
Road；Single via size is 0.5mm*0.5mm, each to cross pitch of holes 0.3-0.4mm；
On the other hand, the present invention discloses a kind of preparation method of the Thick film multilayer wire structures of low thermal resistance, comprising the following steps:
S100, in substrate lower surface printed back metallization material；
S200, inner conductor and medium are successively printed in substrate upper surface；
S300, in printing on media via hole；
S400, in top layer's printing on media top layer welding zone；
S500, in top layer welding zone upper surface over-assemble power chip.
Further, the S300 repeats operation successively printed medium and via hole, weight after printing on media via hole
Multiple operation at least 2 times or more.
As shown from the above technical solution, the present invention provides a kind of Thick film multilayer place-and-route product high-power chip heat dissipation technologys
Solution to the problem.The program includes: the design of inner conductor, inter-level dielectric, array interlevel via, top conductors structure
With manufacture.Thick film multilayer circuit board designed by the present invention, process implementing difficulty is low, high reliablity, in thick film printing process
On the basis of, realize a kind of Thick film multilayer wire structures of low thermal resistance.
A kind of Thick film multilayer circuit board of low thermal resistance of the invention is hydrid integrated circuit by array via structure
Power chip provides effective heat dissipation channel, realizes reduction power chip thermal dissipating path thermal resistance on Thick film multilayer circuit board
Technical goal.
Detailed description of the invention
Fig. 1 is structural schematic diagram of the invention；
Fig. 2 is preparation method flow chart of steps of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.
As shown in Figure 1, the Thick film multilayer wire structures of low thermal resistance described in this implementation, including thick film substrate 1, the thick film
1 lower surface printed back metallization material of substrate；1 upper surface of the thick film substrate printing inner conductor 2 and top layer welding zone 5, it is interior
Layer conductor 2 is middle layer, and top layer welding zone 5 is located at top layer, and inner conductor 2 is multiple, printed medium 3 between inner conductor 2, top
Layer 5 upper surface over-assemble power chip 6 of welding zone；
Interlevel via (via) 4 is set on the printed medium 3；
Corresponding position, via hole are arranged in a matrix power chip 6 vertically downward；Array via hole realizes that top layer welding zone 5, internal layer are led
2 interlayer interconnection of body, and 6 heat dissipation channel of power chip is provided；Single via size is 0.5mm*0.5mm, each to cross pitch of holes
0.3-0.4mm；
Furthermore alumina substrate can be selected in the preferred beryllium oxide substrate of the thick film substrate 1.
The metallization material is thick film conductor；
The inner conductor 2 of 1 upper surface of the thick film substrate printing is thick film conductor；The inner conductor 2 of the upper surface printing,
Domain structure should have following characteristics: the corresponding inner conductor 2 vertically downward of power chip 6, figure coverage area Ying Bu little
In power chip projected area；
The medium 3 of 1 upper surface of the thick film substrate printing is thick film dielectric；The medium 3 of the upper surface printing, domain structure
It should have the following characteristics that complementary with corresponding interlevel via, that is, print the position medium windowing of via hole, remaining position is paved with Jie
Matter；
The interlevel via of 1 upper surface of the thick film substrate printing is thick film via hole conductor；The interlevel via of the upper surface printing,
Its domain structure should have the following characteristics that corresponding position, via hole are arranged in a matrix power chip 6 vertically downward；Array mistake
Hole realizes that interlayer interconnects between top layer welding zone, inner conductor, and provides power chip heat dissipation channel；Single via size is 0.5mm*
0.5mm, it is each to cross pitch of holes 0.3-0.4mm；
The top layer welding zone of the thick film substrate upper surface printing is thick film welding conductors.
The present embodiment is illustrated below with reference to manufacture craft of the invention:
As shown in Fig. 2, the specific manufacture craft of the embodiment of the present invention is as follows:
S100, in substrate lower surface printed back metallization material；
S200, inner conductor and medium are successively printed in substrate upper surface；
S300, in printing on media via hole；
S400, in top layer's printing on media top layer welding zone；
S500, in top layer welding zone upper surface over-assemble power chip.
Further, the S300 repeats operation successively printed medium and via hole, weight after printing on media via hole
Multiple operation at least 2 times or more.
Specific the present embodiment uses 3 layers of conductor structure, the specific steps are as follows:
It metallizes in 1 lower surface printed back of substrate；
Surface printing first layer conductor on the substrate 1；
Surface printing first layer medium (medium between first layer conductor and second layer conductor) on the substrate 1；
The corresponding via hole of surface printing first layer medium on the substrate 1；
First layer medium (medium thickening) is printed on surface again on the substrate 1；
The corresponding via hole of first layer medium is printed on surface again on the substrate 1；
Surface third printing first layer medium (medium thickening) on the substrate 1；
Surface third printing second layer conductor on the substrate 1；
Surface printing second layer medium (medium between second layer conductor and third layer conductor) on the substrate 1；
The corresponding via hole of surface printing second layer medium on the substrate 1；
Second layer medium (medium thickening) is printed on surface again on the substrate 1；
The corresponding via hole of second layer medium is printed on surface again on the substrate 1；
Surface third printing second layer medium (medium thickening) on the substrate 1；
Surface printing top layer welding zone 5 on the substrate 1；
The film layer of other functions is printed in substrate upper surface；
Above-mentioned is typical 3 layers of conductor structure preparation step, is usually no more than 4 layers of conductor.
To sum up, the embodiment of the present invention is to have been provided using array via structure for hydrid integrated circuit power chip
The heat dissipation channel of effect realizes the technical goal that power chip thermal dissipating path thermal resistance is reduced on Thick film multilayer circuit board, technique
Enforcement difficulty is low, high reliablity.
The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to the foregoing embodiments
Invention is explained in detail, those skilled in the art should understand that: it still can be to aforementioned each implementation
Technical solution documented by example is modified or equivalent replacement of some of the technical features；And these modification or
Replacement, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (8)
1. a kind of Thick film multilayer wire structures of low thermal resistance, including substrate (1), the substrate (1) is thick film substrate, and feature exists
In substrate (1) lower surface printed back metallization material, the metallization material is thick film conductor, on the substrate (1)
Surface printing inner conductor (2) and top layer welding zone (5)；
The inner conductor (2) be thick film conductor, the inner conductor (2) be N number of, 1≤N≤3, the inner conductor (2) it
Between printed medium (3), the medium (3) be thick film dielectric；
Thick film via hole conductor is arranged on the via hole (4) for longitudinally disposed via hole (4) on the medium (3)；
The top layer welding zone (5) is thick film welding conductors, top layer welding zone (5) the upper surface over-assemble power chip (6).
2. the Thick film multilayer wire structures of low thermal resistance according to claim 1, it is characterised in that: the via hole (4) is more
A, the via hole (4) is arranged in a matrix.
3. the Thick film multilayer wire structures of low thermal resistance according to claim 2, it is characterised in that: the single via hole (4)
Having a size of 0.5mm*0.5mm, each via hole (4) spacing 0.3-0.4mm.
4. the Thick film multilayer wire structures of low thermal resistance according to claim 1, it is characterised in that: the substrate (1) is oxygen
Change beryllium substrate.
5. the Thick film multilayer wire structures of low thermal resistance according to claim 1, it is characterised in that: the substrate (1) is oxygen
Change aluminium substrate.
6. the Thick film multilayer wire structures of low thermal resistance according to claim 1, it is characterised in that: the inner conductor (2)
Number N=2.
7. the preparation method of the Thick film multilayer wire structures of low thermal resistance described in -6 any one according to claim 1, feature
It is: the following steps are included:
S100, in substrate (1) lower surface printed back metallization material；
S200, inner conductor (2) and medium (3) are successively printed in substrate (1) upper surface；
S300, via hole (4) are longitudinally printed on medium (3)；
S400, top layer welding zone (5) are printed on top layer's medium (3)；
S500, in top layer welding zone (5) upper surface over-assemble power chip (6).
8. the preparation method of the Thick film multilayer wire structures of low thermal resistance according to claim 7, it is characterised in that: described
S300 repeats operation successively printed medium (2) and via hole (2) after printing via hole (4) on medium (3), and repetitive operation is at least
2 times or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910100056.7A CN109686721A (en) | 2019-01-31 | 2019-01-31 | A kind of Thick film multilayer wire structures of low thermal resistance and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910100056.7A CN109686721A (en) | 2019-01-31 | 2019-01-31 | A kind of Thick film multilayer wire structures of low thermal resistance and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109686721A true CN109686721A (en) | 2019-04-26 |
Family
ID=66195442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910100056.7A Pending CN109686721A (en) | 2019-01-31 | 2019-01-31 | A kind of Thick film multilayer wire structures of low thermal resistance and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021052125A1 (en) * | 2019-09-20 | 2021-03-25 | 天津大学 | Multiplexer |
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|---|---|---|---|---|
| JPH027596A (en) * | 1988-06-27 | 1990-01-11 | Fujitsu Ltd | Wiring board with interlayered film element |
| WO1991011025A1 (en) * | 1990-01-16 | 1991-07-25 | A.S Micro Electronics | A method for manufacturing of mineature impedance matched interconnection patterns |
| JPH0621589A (en) * | 1992-07-06 | 1994-01-28 | Mitsubishi Materials Corp | Heat dissipating structure for hybrid ic and manufacture thereof |
| US5378313A (en) * | 1993-12-22 | 1995-01-03 | Pace; Benedict G. | Hybrid circuits and a method of manufacture |
| US20070057364A1 (en) * | 2005-09-01 | 2007-03-15 | Wang Carl B | Low temperature co-fired ceramic (LTCC) tape compositions, light emitting diode (LED) modules, lighting devices and method of forming thereof |
| JP2007227881A (en) * | 2005-11-14 | 2007-09-06 | Tdk Corp | Composite wiring board, and method of manufacturing same |
| US20110051375A1 (en) * | 2009-08-31 | 2011-03-03 | Ammar Danny F | Highly Integrated Miniature Radio Frequency Module |
| US20140315345A1 (en) * | 2013-02-01 | 2014-10-23 | Berken Solar LLC | Methods For Thick Films Thermoelectric Device Fabrication |
| RU2536771C1 (en) * | 2013-07-09 | 2014-12-27 | Федеральное государственное унитарное предприятие "Научно-производственное предприятие "Исток" (ФГУП "НПП "Исток" | Method to make hybrid integral circuit of shf band |
| EP2903043A2 (en) * | 2014-01-31 | 2015-08-05 | Berken Energy LLC | Methods for thick film thermoelectric device fabrication |
| CN209544335U (en) * | 2019-01-31 | 2019-10-25 | 中国电子科技集团公司第四十三研究所 | A kind of Thick film multilayer wire structures of low thermal resistance |
-
2019
- 2019-01-31 CN CN201910100056.7A patent/CN109686721A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH027596A (en) * | 1988-06-27 | 1990-01-11 | Fujitsu Ltd | Wiring board with interlayered film element |
| WO1991011025A1 (en) * | 1990-01-16 | 1991-07-25 | A.S Micro Electronics | A method for manufacturing of mineature impedance matched interconnection patterns |
| JPH0621589A (en) * | 1992-07-06 | 1994-01-28 | Mitsubishi Materials Corp | Heat dissipating structure for hybrid ic and manufacture thereof |
| US5378313A (en) * | 1993-12-22 | 1995-01-03 | Pace; Benedict G. | Hybrid circuits and a method of manufacture |
| US20070057364A1 (en) * | 2005-09-01 | 2007-03-15 | Wang Carl B | Low temperature co-fired ceramic (LTCC) tape compositions, light emitting diode (LED) modules, lighting devices and method of forming thereof |
| JP2007227881A (en) * | 2005-11-14 | 2007-09-06 | Tdk Corp | Composite wiring board, and method of manufacturing same |
| US20110051375A1 (en) * | 2009-08-31 | 2011-03-03 | Ammar Danny F | Highly Integrated Miniature Radio Frequency Module |
| US20140315345A1 (en) * | 2013-02-01 | 2014-10-23 | Berken Solar LLC | Methods For Thick Films Thermoelectric Device Fabrication |
| RU2536771C1 (en) * | 2013-07-09 | 2014-12-27 | Федеральное государственное унитарное предприятие "Научно-производственное предприятие "Исток" (ФГУП "НПП "Исток" | Method to make hybrid integral circuit of shf band |
| EP2903043A2 (en) * | 2014-01-31 | 2015-08-05 | Berken Energy LLC | Methods for thick film thermoelectric device fabrication |
| CN209544335U (en) * | 2019-01-31 | 2019-10-25 | 中国电子科技集团公司第四十三研究所 | A kind of Thick film multilayer wire structures of low thermal resistance |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021052125A1 (en) * | 2019-09-20 | 2021-03-25 | 天津大学 | Multiplexer |
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