CN109686316B

CN109686316B - Digital scanning circuit

Info

Publication number: CN109686316B
Application number: CN201910158771.6A
Authority: CN
Inventors: 张建华; 郭爱英
Original assignee: University of Shanghai for Science and Technology
Current assignee: University of Shanghai for Science and Technology
Priority date: 2019-03-04
Filing date: 2019-03-04
Publication date: 2021-03-16
Anticipated expiration: 2039-03-04
Also published as: CN109686316A

Abstract

The invention discloses a digital scanning circuit, comprising: the system comprises a video source module, a bit fusion module, a buffer module and a silicon-based organic light emitting diode panel which are sequentially connected, wherein the video source module is used for sending two continuous images; the position fusion module is used for performing low-position fusion on the data information of two continuous images sent by the video source module to obtain fused data information; the buffer module is used for buffering and storing the fused data information. The invention can improve the scanning efficiency and utilize the transmission bandwidth to the maximum extent on the basis of not additionally increasing the clock frequency, thereby achieving the purpose of improving the image resolution.

Description

Digital scanning circuit

Technical Field

The present invention relates to the field of digital scanning, and more particularly, to a digital scanning circuit.

Background

The gray scale of the research image of the related silicon-based organic light emitting diode micro-display is 256 levels at present, the resolution is generally 640 x 320 resolution stage, the details of the darker or brighter image cannot be displayed, and only very individual products can reach 1920 x 1280 resolution level, mainly because: the scanning imaging technology is constrained by the thinking of the scanning of the traditional electron gun, and a large amount of time redundancy exists according to the scanning principle of following the point-by-point scanning from top to bottom, thereby bringing about the brightness loss and the gray scale loss. Therefore, the clock frequency of the core operation entity increases in a series manner along with the increase of the gray level, and the cost and the power consumption of the system increase along with the increase of the gray level. If the gray scale of the displayed image is increased, the hardware performance and scale are greatly increased, the miniaturization design of the display cannot be realized, and the aim of reducing the power consumption cannot be achieved.

Disclosure of Invention

The invention aims to provide a digital scanning circuit, which aims to improve the scanning efficiency on the basis of not additionally increasing the clock frequency and utilize the transmission bandwidth to the maximum extent so as to achieve the aim of improving the image resolution.

In order to achieve the purpose, the invention provides the following scheme:

a digital scanning circuit, comprising: the system comprises a video source module, a bit fusion module, a buffer module and a silicon-based organic light emitting diode panel which are sequentially connected, wherein the video source module is used for sending two continuous images; the position fusion module is used for performing low-position fusion on the data information of two continuous images sent by the video source module to obtain fused data information; the buffer module is used for buffering and storing the fused data information.

Optionally, the position fusing module includes a position buffering unit, a position judging unit and a position adjusting unit, which are connected in sequence, wherein the position buffering unit is connected with the video source module, and the position adjusting unit is connected with the buffering module; the bit buffer unit is used for storing the data information of two continuous images sent by the video source module in parallel according to bit plane information; the bit judgment unit is used for carrying out merging judgment on the data information stored in the bit buffer unit to obtain judged data information; the bit adjusting unit is used for adjusting the judged data information to obtain the adjusted data information.

Optionally, the judgment principle of the bit judgment unit is as follows: fusing data information of two bits between the 1 st bit and the 5 th bit; the data information of two bits between the 6 th bit and the 8 th bit is not fused.

Optionally, the bit adjusting unit adjusts the scanning sequence of the first image data information in two consecutive images to: 4, 2, 1, 0; adjusting a second image data information scanning sequence in two consecutive images to: 4,2,1,0,1/2,1/4,1/8,1/16.

According to the specific embodiment provided by the invention, the invention discloses the following technical effects: the invention provides a digital scanning circuit, which processes and merges two continuous data sources, and can carry out more optimized designs; according to the invention, the clock frequency is not increased, and only the bits of the existing data source are processed, so that the large-scale increase of hardware resource overhead is avoided, and the hardware cost is reduced while the scanning efficiency is improved; the invention replaces the traditional characteristic of progressive point-by-point scanning, partially combines the information of two continuous data sources, and can increase the imaging display quality of the data sources.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.

FIG. 1 is a block diagram of the digital scanning circuit of the present invention;

FIG. 2 is a block diagram of the bit fusion module according to the present invention;

FIG. 3 is a block diagram of a conventional digital scanning circuit;

FIG. 4 is a diagram illustrating a conventional sub-field scan;

FIG. 5 is a schematic diagram of a bit-fused scan according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention aims to provide a digital scanning circuit, which can improve the scanning efficiency and utilize the transmission bandwidth to the maximum extent on the basis of not additionally increasing the clock frequency, thereby achieving the purpose of improving the image resolution.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

FIG. 1 is a block diagram of the digital scanning circuit according to the present invention. As shown in fig. 1, a digital scanning circuit includes: the device comprises a video source module 1, a bit fusion module 2, a buffer module 3 and a silicon-based organic light emitting diode panel 4 which are connected in sequence. The video source module 1 is used for sending two continuous images; the position fusion module 2 is configured to perform low-order fusion on the data information of two consecutive images sent by the video source module 1 to obtain fused data information; the buffer module 3 is used for buffering and storing the fused data information, and the silicon-based organic light emitting diode panel 4 is used for controlling the light emitting duration of the organic light emitting diode according to the buffered and stored data. Fig. 3 is a structural diagram of a conventional digital scanning circuit.

FIG. 2 is a block diagram of the bit fusion module according to the present invention. As shown in fig. 2, the bit fusion module 2 includes a bit buffer unit 21, a bit judgment unit 22, and a bit adjustment unit 23, which are connected in sequence, where the bit buffer unit 21 is connected to the video source module 1, and the bit adjustment unit 23 is connected to the buffer module 3; the bit buffer unit 21 is configured to store data information of two consecutive images sent by the video source module 1 in parallel according to bit plane information; the bit judgment unit 22 is configured to perform merging judgment on the data information stored in the bit buffer unit 21 to obtain judged data information; the bit adjusting unit 23 is configured to adjust the determined data information to obtain adjusted data information.

The judgment principle of the bit judgment unit is as follows: fusing data information of two bits between the 1 st bit and the 5 th bit; the data information of two bits between the 6 th bit and the 8 th bit is not fused.

The bit adjustment unit adjusts a first image data information scanning sequence of two consecutive images to: 4, 2, 1, 0; adjusting a second image data information scanning sequence in two consecutive images to: 4,2,1,0,1/2,1/4,1/8,1/16.

The traditional data information is 8 bits, the image with 256 gray scale levels, and the algorithm based on sub-field scanning uses 6 bits of ground as basic field for scanning. Then the 8 bits of information correspond to a weight of: 4, 2, 1, 1/2, 1/4, 1/8, 1/16, 1/32, the scan sequence being: 4, 2, 1, 1/2, 1/4, 1/8, 1/16, 1/32, the total scan time is 12 subfields by unit scan subfield time. The scan sub-fields of two consecutive data sources are 24 sub-fields and the scan time is 24 sub-fields times the unit scan sub-field time. The subfields of the first image data information processed by the invention are 7 (7 subfields are 4+2+1 ═ 7, and the total number of the subfields is 7), and the subfields of the second image data information are 11 (11 subfields are 4+2+1+ (1+1+ 1) ═ 11, and the total number of the subfields is 11). The scan sub-fields for two consecutive data sources are 18, then the scan time is 18 times the unit scan sub-field time. The first image data information and the second image data information are displayed in a crossed mode, and time redundancy of line-by-line point-by-point display is reduced.

Compared with the prior art, the invention has the following advantages:

the invention processes and merges with two continuous data sources, and can carry out more optimization designs;

according to the invention, the clock frequency is not increased, and only the bits of the existing data source are processed, so that the large-scale increase of hardware resource overhead is avoided, and the hardware cost is reduced while the scanning efficiency is improved;

the invention replaces the traditional characteristic of progressive point-by-point scanning, partially combines the information of two continuous data sources, and can increase the imaging display quality of the data sources.

Specific embodiment example 1:

fig. 4 is a diagram illustrating a conventional subfield scanning. As shown in fig. 4, in the conventional scanning algorithm, for a data source with 256 gray levels and 8 bits of information source, the scanning sequence has the following weights: 4,2,1,1/2,1/4,1/8,1/16,1/32.

FIG. 5 is a schematic diagram of a bit-fused scan according to the present invention. As shown in fig. 5: after passing through the bit fusion module, the weights of the information source 1 are: 4, 2, 1, 0, data 2 scan sequence is adjusted to: 4,2,1,0,1/2,1/4,1/8,1/16. The

bits

1, 2, 3, and 4 of the information source 1 need to be combined with the information of the information source 2 for display, and the bits 5, 6, 7, and 8 of the data source 1 are independently displayed (shaded subfields in fig. 5).

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.

Claims

1. A digital scanning circuit, comprising: the system comprises a video source module, a bit fusion module, a buffer module and a silicon-based organic light emitting diode panel which are sequentially connected, wherein the video source module is used for sending two continuous images; the position fusion module is used for performing low-position fusion on the data information of two continuous images sent by the video source module to obtain fused data information; the buffer module is used for buffering and storing the fused data information;

the position fusion module comprises a position buffering unit, a position judging unit and a position adjusting unit which are sequentially connected, the position buffering unit is connected with the video source module, and the position adjusting unit is connected with the buffering module; the bit buffer unit is used for storing the data information of two continuous images sent by the video source module in parallel according to bit plane information; the bit judgment unit is used for carrying out merging judgment on the data information stored in the bit buffer unit to obtain judged data information; the bit adjusting unit is used for adjusting the judged data information to obtain adjusted data information;

the judgment principle of the bit judgment unit is as follows: fusing data information of two bits between the 1 st bit and the 5 th bit; the data information of two bits between the 6 th bit and the 8 th bit is not fused;