CN109684745B - 6T &6TPPNN unit layout method based on minimum width constraint - Google Patents

6T &6TPPNN unit layout method based on minimum width constraint Download PDF

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CN109684745B
CN109684745B CN201811608210.3A CN201811608210A CN109684745B CN 109684745 B CN109684745 B CN 109684745B CN 201811608210 A CN201811608210 A CN 201811608210A CN 109684745 B CN109684745 B CN 109684745B
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周汉斌
朱自然
陈建利
陈彬
董森华
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Beijing Empyrean Technology Co Ltd
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Huada Empyrean Software Co Ltd
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Abstract

A minimum width constraint-based 6T &6TPPNN unit layout method comprises the following steps: cell alignment taking into account Vdd/Vss rail alignment constraints; clustering units based on a minimum width constraint; 6TPPNN unit conversion; cell movement based on the slice effect; the quadratic programming problem model and the solution based on the modular iteration method can reduce the line length increase caused by all the minimum width constraints on the premise of not increasing any chip design area, simultaneously reduce the segment effect and improve the circuit performance.

Description

6T &6TPPNN unit layout method based on minimum width constraint
Technical Field
The invention relates to the technical field of Very Large Scale Integration (VLSI) physical design automation, in particular to a unit layout method.
Background
In conventional circuit designs, standard cells having the same height are easier to design and optimize. Then, as the design complexity increases, the general 6T &6TPPNN cell structure with mixed height can achieve better balance of area and routability than the single-height standard cell. Specifically, a smaller cell height can achieve a smaller area and lower power consumption, but its power driving force is lower. Conversely, a higher cell height may enable greater power supply drive and better routability, but it also costs more area and higher power consumption. The circuit design of such mixed height cells is more challenging due to the heterogeneity of the cell structure. Furthermore, in this layout design, additional considerations are needed to align multiple times of row high cells onto the correct power (Vdd) and ground (Vss) rails. The Vdd/Vss rail lines are arranged crosswise in the layout cell rows and each cell must be aligned to the correct power supply rail so that the Vdd/Vss pins match the corresponding rails. For a typical 6T cell, its Vdd/Vss pins are located on both sides of the cell. Thus, for a typical 6T cell that is an even multiple of the row height, the Vdd/Vss pins at both ends are the same, so it can only correspond to a particular row of power rails; for a typical odd-row-height 6T cell, the Vdd/Vss pins at both ends are different, and they can be aligned to any row layout directly or after vertical flipping. For a typical 6TPPNN cell, it is first a double high cell and its Vdd/Vss pin is internal to the cell. Thus, a 6TPPNN cell needs to correspond to a particular layout half-line.
As shown in fig. 1, the 6T cells may occupy one or more rows above an internal layout row of the integrated circuit, with upper and lower boundaries of the layout coinciding with upper and lower boundaries of the row; the 6TPPNN cell is twice as high in height, but it spans three rows across the layout row inside the integrated circuit, with the upper and lower boundaries of the layout coinciding with the middle horizontal line of the row.
In addition, the method of applying multiple threshold voltages is widely used to balance delay and power consumption, which can reduce leakage of power while maintaining good circuit performance. In a 6T &6TPPNN multi-threshold voltage circuit design, there are three voltages, high threshold voltage, low threshold voltage and standard threshold voltage, respectively. In the present patent, we will refer to the high/low threshold voltage cell set as ULVT and the standard threshold voltage cell set as SVT.
However, as cell feature sizes decrease, and due to limitations of photolithography, multi-threshold voltage cells may violate complex minimum width constraints when laid out. The minimum width constraint refers to specifying a lower bound on the width sum of the same voltage cells on each track half-row. A cell incurs a minimum width constraint if the sum of the widths of its adjacent identical voltages in the half-row in which it is located is less than a given minimum width lower bound. In addition, since the 6TPPNN cell is double high and it can only be placed on half a row, each 6TPPNN cell has a half row fragmentation effect on both the top and bottom, which has a significant impact on the circuit layout performance.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide a 6T &6TPPNN unit layout method based on minimum width constraint, which reduces the line length increase caused by the minimum width constraint and reduces the segment effect on the premise of not increasing any chip design area.
In order to achieve the above object, the invention provides a minimum width constraint-based 6T &6TPPNN cell layout method, comprising the following steps:
1) cell alignment taking into account Vdd/Vss rail alignment constraints;
2) clustering units based on a minimum width constraint;
3)6TPPNN unit conversion;
4) cell movement based on the slice effect;
5) and solving a quadratic programming problem model based on a model iteration method.
Further, the step 1) further comprises the following steps:
a) giving a mixed height cell global layout with a plurality of standard cells and a plurality of nets;
b) setting a rectangular frame as a layout area, and setting vertex coordinates of the lower left corner and the upper right corner of the rectangular frame; setting the lower left corner coordinate, the width and the height of the unit;
setting the Vdd/Vss pin of each cell, the width of which is a given constant; setting a set of high and low threshold voltage cells and standard threshold voltage cells; the minimum width is constrained to a given constant;
each cell is placed on its lower left corner coordinates and the following constraints are satisfied: (1) the units are not overlapped; (2) the unit is placed in the layout area; (3) the unit is placed on the corresponding position of the layout row; (4) the cells are matched to the correct Vdd/Vss rails; (5) the 6TPPNN cells all satisfy the minimum width constraint;
c) all 6T &6TPPNN cells are aligned to be closest to the correct power supply rail layout row.
Further, the step 2) further comprises the following steps:
a) giving an initial radius r, and constructing a local search circular area for a minimum width conflict unit by taking the minimum width conflict unit as a center and taking r as the radius;
b) searching all cells having the same voltage as the conflicting cell in the local search circular area, a weight configured to be simultaneously set between the conflicting cell and each of the searched cells;
c) traversing all weights, finding out the unit sequence pair with the minimum weight, and then clustering the units;
d) finding a linear increment optimal area for each cluster;
e) and respectively calculating the bounding boxes of all the units except the unit contained in the cluster in each line net.
Further, the weight formula is:
Figure BDA0001924091600000031
wherein the content of the first and second substances,
(xi,yi) Is a unit ci(w) lower left corner coordinate (d)i,hi) Is a unit ciWidth and height, (x)j,yj) Is a unit cj(w) lower left corner coordinate (d)j,hj) Is a unit cjThe width and the height of the base plate,
if unit ciAnd cjAll violate the minimum width constraint, then θij1, otherwise, θij＝2；|xi-xj|+|yi-yjIs unit ciAnd cjManhattan distance between.
Further, the search formula of the optimal region is as follows:
clustering
Figure BDA0001924091600000032
Wherein
Figure BDA0001924091600000033
Representing a cluster u1The number of the included units and the optimal area are obtained by solving the optimal solution of the following problems:
Figure BDA0001924091600000034
wherein m isiRepresentation and unit uciThe number of units connected.
Further, the step 3) further comprises the following specific steps: the 6TPPNN unit is converted into a unit with three times of height, so that the unit can be conveniently legalized in the subsequent stage.
Further, the step 4) further comprises the following specific steps:
a) performing unit movement based on the segment effect in a segment effect hot spot region, wherein the segment effect hot spot region is a window of a chip layout region and satisfies the following conditions: a. thefrag/Awind≧ τ, where τ is a given constant, AwindIs the total area of the window, AfragIs the sum of the areas of all 6TPPNN cells in the window;
b) in each fragment hotspot area, constructing a weighting table for each 6TPPNN unit, wherein the weight value between any two units is equal to the Manhattan distance between the two units;
c) finding two clustering units with the minimum weight, and moving the 6TPPNN units together through unit movement to form a new cluster;
d) and finding an optimal area for each cluster to place.
Further, the step of moving the 6TPPNN units together by unit movement to form a new cluster by the two cluster units finding the minimum weight value further comprises,
calculating the width sum of 6TPPNN units in each cluster in the unit moving process;
the breadth and small 6TPPNN clusters are moved to breadth and large 6TPPNN clusters and combined into new clusters.
Further, the step 5) further comprises the following specific steps:
a) the 6T &6TPPNN unit legalization problem is converted into a quadratic programming problem, and the corresponding mathematical model is as follows:
Figure BDA0001924091600000041
such that:
(1) for all adjacent cells c of the same rowiAnd cjX'i≥x′jThe method comprises the following steps: x is the number ofi-xj≥wj；
(2) For all units ciHas xi≥0.
Wherein x'iAnd x'jIs a unit ciAnd cjX-coordinate prior to legalization;
b) the legalization problem is efficiently solved by applying a modular iterative method (MMSIM) solver.
To achieve the above object, the present invention also provides a computer readable storage medium having stored thereon computer instructions which, when executed, perform the steps of the minimum width constraint-based 6T &6TPPNN cell placement method as described above.
Compared with the prior art, the 6T &6TPPNN unit layout method based on the minimum width constraint has the following technical effects:
(1) the processing of the units causing the minimum width constraint conflict is realized by clustering the 6T &6TPPNN units with the same voltage into a compact structure through a graph-based clustering algorithm. In order to minimize the increase of line length in the clustering process, an optimal area is searched for each cluster by using a median formula to serve as an optimal placement position after unit clustering;
(2) the unit moving method based on the segment effect is used for moving the 6TPPNN unit in the segment effect hotspot area, so that the reduction of the segment effect is realized;
(3) after a 6TPPNN unit is converted into a triple high unit, converting a 6T &6TPPNN unit legalization problem into a Quadratic Programming (QP) problem, and solving the problem by using a model-based iteration method (MMSIM);
the experimental result shows that the method of the invention can cause 3.6% of line length increase on the basis of completely solving all minimum width constraints on the premise of not increasing any chip design area, and simultaneously averagely reduces the fragment effect to 40900nm, thereby obviously improving the circuit performance.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
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The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of the distribution of 6T cells and 6TPPNN cells across layout rows within an integrated circuit, and the generation and reduction of the fragmentation effect;
fig. 2 is a flowchart of a minimum width constraint based 6T &6TPPNN cell placement method according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Fig. 2 is a flowchart of a minimum width constraint-based 6T &6TPPNN cell layout method according to the present invention, and the minimum width constraint-based 6T &6TPPNN cell layout method of the present invention will be described in detail with reference to fig. 2.
The mathematical model of the minimum width constraint-based 6T &6TPPNN unit layout method of the invention is described as follows:
firstly, a standard unit C containing n is given as ═ C1,c2,…,cnAnd m lines E ═ E1,e2,…,e m6T of }&6TPPNN unit global layout. The layout area is a rectangular frame, whose (0,0) and (W, H) are the vertex coordinates of the lower left corner and the upper right corner of the rectangular frame, respectively. Let (x)i,yi) Is a unit ci(w) lower left corner coordinate (d)i,hi) Is its width and height. The width of each site is sitew. Each cell has a corresponding Vdd/Vss pin. Is provided with CULAnd CSRespectively, a collection of high/low threshold voltage cells (ULVT) and standard threshold voltage cells (LVT). The minimum width ω is a given constant.
6T based on minimum width constraint&The 6TPPNN cell layout target is to place each cell ciPut to the coordinate (x)i,yi) In the above, the total displacement of the unit is minimized, no area overflow is generated, and the following 5 constraint conditions are satisfied: (1) the units do not overlap each other; (2) the unit is placed in the layout area; (3) the unit is placed on the corresponding position of the layout row; (4) the cells are matched to the correct Vdd/Vss rails; (5) the 6TPPNN cells each satisfy the minimum width constraint. The mathematical model is as follows:
Figure BDA0001924091600000061
and satisfies the following constraints:
1)
Figure BDA0001924091600000062
2)
Figure BDA0001924091600000063
Figure BDA0001924091600000064
3)
Figure BDA0001924091600000065
4)
Figure BDA0001924091600000066
wherein the unit
Figure BDA0001924091600000067
In the same half row and adjacent to each other.
First, in step 201, the cell alignment will be considered for the Vdd/Vss rail alignment constraint. The specific implementation method is described in detail as follows:
to achieve high quality legalization results, it is important to maintain an initial global layout. We first align all cells to the nearest layout row. Since the Vdd/Vss pin of the 6TPPNN cell is internal to the cell and its two internal pins are the Vdd pin and Vss pin, respectively, we can treat the 6TPPNN cell as an odd multiple high cell when considering the Vdd/Vss rail alignment constraint. Thus, for odd multiple high cell (6TPPNN) cells, the nearest row (half row) is the row closest to its ordinate; for even-times-tall cells, the nearest row is the layout row of the correct power supply rail closest to its ordinate. By updating the vertical coordinates of the cells, we can achieve the alignment of all 6T &6TPPNN cells to the most recent correct power supply rail layout row (half row).
At step 202, the cells are clustered based on the minimum width constraint. The specific implementation method is described in detail as follows:
the element clustering algorithm based on the minimum width constraint is performed in a dynamic local area, and an initial radius r is given. For a minimum width collision cell, we first construct a local search circle region centered on it, with r as the radius. Then we search in this area for all cells with the same voltage as the conflicting cell, while setting an appropriate weight between the conflicting cell and each searched cell. The weight formula is given as follows:
Figure BDA0001924091600000071
if unit ciAnd cjAll violate the minimum width constraint, then θij1, otherwise, θij＝2.|xi-xj|+|yi-yjIs unit ciAnd cjManhattan distance between. Obviously, our weight formula has the following two features: the closer the unit distance is, the more likely it is to be clustered; the same cell height is more likely to be clustered because the closer the cell height is, the less filler it needs to be inserted.
By traversing all weights, we find the smallest weighted cell ordered pair (cell c)iAnd cj) Then we will unit ciAnd cjAnd (6) clustering. This minimum-width-constraint-based element clustering algorithm terminates if and only if no minimum-width conflicting elements exist. Then, we find an area (optimal area) with the minimum linear increment for each cluster, and specifically find the optimal area as follows: clustering
Figure BDA0001924091600000072
(wherein
Figure BDA0001924091600000073
Representing a cluster ulThe number of units involved), then solving its corresponding optimal region can be obtained by solving the optimal solution of the following problem:
Figure BDA0001924091600000074
wherein m isiRepresentation and unit uciThe number of units connected.
The solving process is to calculate each netiWith the exception of the unit uciAnd a bounding box that encompasses all other cells. And for each boundary box, respectively sorting the abscissa and ordinate of all the boundary boxes from small to large, and then calculating the median of the sorted abscissas and ordinates. Obviously, the area formed by the median of the bounding box coordinates is the optimal solution of the above problem, i.e. the area (optimal area) with the minimum increment of the unit line length.
In step 203, the 6TPPNN unit is converted. In the 6TPPNN unit conversion stage, the 6TPPNN cluster (unit) is converted into a triple high unit, so that the unit is legalized in the subsequent stage.
In step 204, the cell moves based on the slice effect. The specific implementation method is described in detail as follows:
at this stage, to avoid excessive cell displacement, the inventive fragmentation-based cell movement process is only performed in fragmentation hot spot regions.
First, the definition of the segment effect hot spot region is given as follows:
fragmentation effect hot spot region: the segment effect hot spot region is a window of the chip layout region, and satisfies the following conditions: a. thefrag/Awind≧ τ, where τ is a given constant, AwindIs the total area of the window, AfragIs the sum of the areas of all 6TPPNN cells in the window.
In each segment hot spot area, an empowerment table is constructed for each 6TPPNN unit (cluster). The weight between any two cells is equal to the manhattan distance between them. Once we find the two units (clusters) of the smallest weight, we reduce the fragmentation effect by moving the 6TPPNN units together by unit movement to form a new cluster. In the unit moving process, the width sum of the 6TPPNN units in each cluster is calculated, then the 6TPPNN clusters with the smaller width sum are moved to the 6TPPNN clusters with the larger width sum and combined into a new cluster, and therefore the phenomenon that the unit internal overlapping is caused in the process of reducing the fragment effect can be avoided. After that, we still use the median formula to find an optimal region for each cluster to place. Due to the heterogeneous unit structure, once two clusters are used for clustering to reduce the fragmentation effect, the two units will not be involved in the subsequent process.
In step 205, the quadratic programming problem model and the solution based on the modular iteration method are described in detail as follows:
through the processing process, all the minimum width constraint conflict units are processed completely, and the fragment effect is reduced. At this stage we convert the general 6T &6TPPNN unit legalization problem into a Quadratic Programming (QP) problem, whose mathematical model is as follows:
Figure BDA0001924091600000081
such that:
(1) for all adjacent cells c of the same rowiAnd cjX'i≥x′jThe method comprises the following steps: x is the number ofi-xj≥wj；
(2) For all units ciHas xi≥0.
Wherein x'iAnd x'jIs a unit ciAnd cjX-coordinate before legalization.
Since we have converted the 6TPPNN unit to a triple high unit through our 6TPPNN unit conversion stage, we can directly apply a modulo iteration based method (MMSIM) to efficiently solve this legalization problem. And we can get the following theorem.
Theorem 1: the MMSIM can solve the optimal solution of the problem (3) under the time complexity of O (n), wherein n is the number of unit variables.
The present invention also provides a computer readable storage medium having stored thereon computer instructions which when executed perform the steps of the minimum width constraint based 6T &6TPPNN cell placement method as described above.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. A6T &6TPPNN unit layout method based on minimum width constraint comprises the following steps:
1) cell alignment taking into account Vdd/Vss rail alignment constraints;
2) clustering units based on a minimum width constraint;
3)6TPPNN unit conversion;
4) cell movement based on the slice effect;
5) solving a quadratic programming problem model based on a model iteration method;
the step 4) further comprises the following specific steps:
a) performing unit movement based on the segment effect in a segment effect hot spot region, wherein the segment effect hot spot region is a window of a chip layout region and satisfies the following conditions:
Figure 275957DEST_PATH_IMAGE001
wherein
Figure 934471DEST_PATH_IMAGE002
Is a given constant that is constant for each of the two,
Figure 303135DEST_PATH_IMAGE003
is the total area of the window(s),
Figure 72508DEST_PATH_IMAGE004
is the sum of the areas of all 6TPPNN cells in the window;
b) in each fragment hotspot area, constructing a weighting table for each 6TPPNN unit, wherein the weight value between any two units is equal to the Manhattan distance between the two units;
c) finding two clustering units with the minimum weight, and moving the 6TPPNN units together through unit movement to form a new cluster;
d) and finding an optimal area for each cluster to place.
2. The minimum width constraint-based 6T &6TPPNN cell placement method according to claim 1, wherein the step 1) further comprises the steps of:
a) giving a mixed height cell global layout with a plurality of standard cells and a plurality of nets;
b) setting a rectangular frame as a layout area, and setting vertex coordinates of the lower left corner and the upper right corner of the rectangular frame; setting the lower left corner coordinate, the width and the height of the unit;
setting the Vdd/Vss pin of each cell, the width of which is a given constant; setting a set of high and low threshold voltage cells and standard threshold voltage cells; the minimum width is constrained to a given constant;
each cell is placed on its lower left corner coordinates and satisfies the following constraints: (1) the units are not overlapped; (2) the unit is placed in the layout area; (3) the unit is placed on the corresponding position of the layout row; (4) the cells are matched to the correct Vdd/Vss rails; (5) the 6TPPNN cells all satisfy the minimum width constraint;
c) all 6T &6TPPNN cells are aligned to be closest to the correct power supply rail layout row.
3. The minimum width constraint-based 6T &6TPPNN cell placement method according to claim 1, wherein the step 2) further comprises the steps of:
a) giving an initial radius r, and constructing a local search circular area for a minimum width conflict unit by taking the minimum width conflict unit as a center and taking r as the radius;
b) searching all cells having the same voltage as the conflicting cell in the local search circular area, a weight configured to be simultaneously set between the conflicting cell and each of the searched cells;
c) traversing all weights, finding out the unit sequence pair with the minimum weight, and then clustering the units;
d) finding a linear increment optimal area for each cluster;
e) and respectively calculating the bounding boxes of all the units except the unit contained in the cluster in each line net.
4. The minimum width constraint-based 6T &6TPPNN cell placement method according to claim 3, wherein the weight formula is:
Figure DEST_PATH_IMAGE005
wherein the content of the first and second substances,
Figure 311860DEST_PATH_IMAGE006
is a unit
Figure 141276DEST_PATH_IMAGE007
The coordinates of the lower left corner of (c),
Figure 793974DEST_PATH_IMAGE008
is a unit
Figure 827090DEST_PATH_IMAGE007
The width and the height of the base plate,
Figure 186527DEST_PATH_IMAGE009
is a unit
Figure 249161DEST_PATH_IMAGE010
The coordinates of the lower left corner of (c),
Figure 326839DEST_PATH_IMAGE011
is a unit
Figure 969172DEST_PATH_IMAGE010
The width and the height of the base plate,
if unit
Figure 183116DEST_PATH_IMAGE012
And
Figure 619914DEST_PATH_IMAGE013
all violate the minimum width constraint, then
Figure 184887DEST_PATH_IMAGE014
And if not, the step (B),
Figure 365333DEST_PATH_IMAGE015
is a unit
Figure 699362DEST_PATH_IMAGE012
And
Figure 307061DEST_PATH_IMAGE013
manhattan distance between.
5. The minimum width constraint-based 6T &6TPPNN unit layout method according to claim 3, wherein the optimal region search formula is:
clustering
Figure 359331DEST_PATH_IMAGE016
Wherein
Figure 343467DEST_PATH_IMAGE017
Representing clusters
Figure 797582DEST_PATH_IMAGE018
The number of the included units and the optimal area are obtained by solving the optimal solution of the following problems:
Figure 310603DEST_PATH_IMAGE019
wherein
Figure 850169DEST_PATH_IMAGE020
Representation and unit
Figure 369488DEST_PATH_IMAGE021
The number of units connected.
6. The minimum width constraint-based 6T &6TPPNN cell placement method according to claim 1, characterized in that: the step 3) further comprises the following specific steps: the 6TPPNN unit is converted into a unit with three times of height, so that the unit can be conveniently legalized in the subsequent stage.
7. The minimum width constraint-based 6T &6TPPNN cell placement method according to claim 1, characterized in that: the step of moving the 6TPPNN units together to form a new cluster by unit movement of the two cluster units finding the minimum weight further comprises,
calculating the width sum of 6TPPNN units in each cluster in the unit moving process;
the breadth and small 6TPPNN clusters are moved to breadth and large 6TPPNN clusters and combined into new clusters.
8. The minimum width constraint-based 6T &6TPPNN cell placement method according to claim 1, characterized in that: the step 5) further comprises the following specific steps:
a) the 6T &6TPPNN unit legalization problem is converted into a quadratic programming problem, and the corresponding mathematical model is as follows:
Figure 678109DEST_PATH_IMAGE022
such that:
(1) for all adjacent cells of the same row
Figure 893190DEST_PATH_IMAGE007
And
Figure 654472DEST_PATH_IMAGE010
if, if
Figure 980412DEST_PATH_IMAGE023
The method comprises the following steps:
Figure 877960DEST_PATH_IMAGE024
；
(2) for all units
Figure 998363DEST_PATH_IMAGE007
Is provided with
Figure 512521DEST_PATH_IMAGE025
.
Wherein
Figure 376572DEST_PATH_IMAGE026
And
Figure 394206DEST_PATH_IMAGE027
is a unit
Figure 951090DEST_PATH_IMAGE007
And
Figure 686965DEST_PATH_IMAGE010
before legalisation
Figure 354706DEST_PATH_IMAGE028
Coordinates;
b) the legalization problem is efficiently solved by applying a modular iterative method (MMSIM) solver.
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