CN109684670B - High-frequency clock fan-out device - Google Patents
High-frequency clock fan-out device Download PDFInfo
- Publication number
- CN109684670B CN109684670B CN201811434033.1A CN201811434033A CN109684670B CN 109684670 B CN109684670 B CN 109684670B CN 201811434033 A CN201811434033 A CN 201811434033A CN 109684670 B CN109684670 B CN 109684670B
- Authority
- CN
- China
- Prior art keywords
- npn
- resistor
- emitter
- port
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Abstract
The invention discloses a high-frequency clock fan-out device, and belongs to the technical field of clock circuits. The high frequency clock fanout includes an input selection module, an amplification module, a fanout module, and a plurality of output drive modules. The input selection module selects an input clock channel; the amplifying module is used for recovering and amplifying differential clock signals; the fan-out module distributes one path of differential clock signals to a plurality of paths of clock channels; the output driving modules respectively convert the multi-path clock signals into LVPECL level output, and the loading capacity of a clock driving belt is improved. The high-frequency clock fan-out device has the functions of multi-path selection input and multi-path driving output, can improve the flexibility of clock selection and distribution, realizes low-noise and high-frequency clock fan-out, and meets the strict requirements of systems such as multi-channel high-speed high-precision data conversion and the like on clock performance.
Description
Technical Field
The invention relates to the technical field of clock circuits, in particular to a high-frequency clock fan-out device.
Background
Clock fanout is a technique for multiplexing a clock signal out of a buffer. The clock fan-out directly influences the performance of systems such as multichannel data receiving and transmitting, data conversion and the like, and is widely applied to the fields of signal processing, military communication, radars, electronic countermeasure and the like.
With the continuous improvement of the application requirements of the whole system, the data conversion technology is continuously developed towards high speed and high precision. The clock is used as a key factor of the high-speed high-precision digital-to-analog converter and the analog-to-digital converter, and the performance of the clock directly determines the performances of the data converter, such as the signal-to-noise ratio, the dynamic range and the like.
When the conversion clock speed is required to reach more than 5GHz, the clock period is less than 200ps, and the influence of clock skew of nearly 100ps caused by typical process, power supply voltage and temperature change on the performance of the converter is very obvious. In particular, in a multi-channel data conversion system, the larger the delay variation between channels, the lower the effective accuracy of the system, and the limited conversion speed. Therefore, it is necessary to design a high frequency low noise clock fanout in the system.
Disclosure of Invention
The invention aims to provide a high-frequency clock fan-out device to solve the problem that the existing multi-output and high-frequency high performance cannot be achieved at the same time.
To solve the above technical problem, the present invention provides a high frequency clock fan-out device, comprising:
the input selection module selects an input clock channel;
the amplifying module is used for recovering and amplifying the differential clock signal;
the fan-out module distributes one path of differential clock signals to a plurality of paths of clock channels;
and the output driving modules are used for respectively converting the multi-path clock signals into LVPECL level output so as to improve the loading capacity of a clock driving belt.
Optionally, the high-frequency clock fan-out device further includes a band gap reference module and a bias module, the band gap reference module is connected to the input selection module, the amplification module and the fan-out module, respectively, and the bias module is connected to the band gap reference module.
Optionally, the input selection module includes NPN-type bipolar tubes N1-N10, PNP-type bipolar tubes P1-P4, and resistors R1-R12; wherein the content of the first and second substances,
the base of the NPN type diode N1 is connected with a reference voltage input end V REF (ii) a One end of the resistor R12 is connected with an input selection port SEL, and the other end is connected with the base electrode of the NPN type bipolar transistor N2; the base electrode of the NPN bipolar transistor N3, the base electrode of the NPN bipolar transistor N6, the base electrode of the NPN bipolar transistor N7 and the first bias voltage input port V BIAS1 The base of the NPN type diode N10 is connected with a second bias voltage input port V BIAS2 The collector of the PNP type diode P1 is connected with the first clock channel bias current output port I0, and the collector of the PNP type diode P4 is connected with the second clock channel bias current output port I1; a collector of the NPN type diode N1 is respectively connected with a base of the NPN type diode N4 and one end of a resistor R1, and the other end of the resistor R1 is connected with a power supply VDD; the collector of the NPN type diode N2 is respectively connected with the base of the NPN type diode N5 and one end of a resistor R2, and the other end of the resistor R2 is connected with a power supply VDD; an emitter of the NPN type bipolar tube N1 is respectively connected with an emitter of the NPN type bipolar tube N2 and a collector of the NPN type bipolar tube N3, an emitter of the NPN type bipolar tube N3 is connected with one end of a resistor R8, and the other end of the resistor R8 is grounded GND; a collector of the NPN-type bipolar tube N4 is connected to a collector of the NPN-type bipolar tube N5 and one end of a resistor R3, respectively, the other end of the resistor R3 is connected to the power supply VDD, and an emitter of the NPN-type bipolar tube N4 is connected to a collector of the NPN-type bipolar tube N6 and a base of the NPN-type bipolar tube N9, respectively; an emitter of the NPN-type bipolar tube N5 is respectively connected with a collector of the NPN-type bipolar tube N7 and a base of the NPN-type bipolar tube N8, an emitter of the NPN-type bipolar tube N6 is connected with one end of the resistor R9, the other end of the resistor R9 is connected with a power supply GND, an emitter of the NPN-type bipolar tube N7 is connected with one end of the resistor R10, and the other end of the resistor R10 is connected with the GND; an emitter of the NPN type bipolar tube N8 is respectively connected with an emitter of the NPN type bipolar tube N9 and a collector of the NPN type bipolar tube N10, an emitter of the NPN type bipolar tube N10 is connected with one end of a resistor R11, and the other end of the resistor R11 is grounded to GND; the base electrode of the PNP type bipolar tube P1 is respectively connected with the base electrode of the PNP type bipolar tube P2, the collector electrode of the PNP type bipolar tube P2 and the collector electrode of the NPN type bipolar tube N8; the emitter of the PNP type bipolar tube P1 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with a power supply VDD, the emitter of the PNP type bipolar tube P2 is connected with one end of a resistor R5, and the other end of the resistor R5 is connected with the power supply VDD; the base of PNP type bipolar tube P4 connects PNP type bipolar tube P3's base, PNP type bipolar tube P3's collector and NPN type bipolar tube N9's collector respectively, and PNP type bipolar tube P4's emitter meets resistance R7's one end, resistance R7's another termination power VDD, PNP type bipolar tube P3's emitter meets resistance R6's one end, resistance R6's another termination power VDD.
Optionally, the fan-out module includes NPN bipolar transistors N11-N14, resistors R13-R16, and fan-out submodules FO 1-FON, where N may be any integer between 1 and 4; wherein the content of the first and second substances,
the base electrode of the NPN type bipolar transistor N11 and one end of the resistor R13 are both connected with the positive port INP of the differential clock input, and the other end of the resistor R13 is connected with the power supply VDD; the base electrode of the NPN type bipolar transistor N12 and one end of the resistor R14 are both connected with the negative port INN of the differential clock input, and the other end of the resistor R14 is connected with the power supply VDD; NPN type bipolarThe collector of the tube N11 and the collector of the NPN bipolar tube N12 are both connected with a power supply VDD, the base of the NPN bipolar tube N13, the base of the NPN bipolar tube N14 and VB ports of the fan-out sub-modules FO 1-FON are all connected with a third bias voltage input port V BIAS3 (ii) a An emitter of the NPN type diode N13 is connected with one end of a resistor R15, and the other end of the resistor R15 is connected with the GND; an emitter of the NPN type diode N14 is connected with one end of a resistor R16, and the other end of the resistor R16 is connected with the GND; an emitter of the NPN type diode N11 is respectively connected with a collector of the NPN type diode N13 and IP ports of the fan-out submodules FO 1-FON; an emitter of the NPN type diode N12 is respectively connected with a collector of the NPN type diode N14 and IN ports of the fan-out submodules FO 1-FON; the OP port of the fan-out submodule FO1 is connected with a fan-out submodule differential clock output positive port FOP1, and the ON port of the fan-out submodule FO1 is connected with a fan-out submodule differential clock output negative port FON 1; ...; the OP port of the fan-out submodule FON is connected with the positive output port FOPN of the fan-out submodule differential clock, and the ON port of the fan-out submodule FON is connected with the negative output port FONN of the fan-out submodule differential clock.
Optionally, each fan-out submodule has the same structure and includes NPN bipolar transistors N15 to N17 and a resistor R17; wherein the content of the first and second substances,
the base of the NPN type bipolar tube N16 is connected with the input differential clock positive port IP, the base of the NPN type bipolar tube N15 is connected with the input differential clock negative port IN, the base of the NPN type bipolar tube N17 is connected with the bias voltage port VB, the emitter of the NPN type bipolar tube N17 is connected with one end of the resistor R17, the other end of the resistor R17 is grounded GND, and the collector of the NPN type bipolar tube N17 is respectively connected with the emitter of the NPN type bipolar tube N15 and the emitter of the NPN type bipolar tube N16; the collector of the NPN-type diode N15 is connected to the positive output differential clock port OP, and the collector of the NPN-type diode N16 is connected to the negative output differential clock port ON.
Optionally, each of the output driving modules includes an emitter follower sub-module EF and driving sub-modules ECL0 to ECL 2; wherein the content of the first and second substances,
the EF _ INP port of the emitter follower sub-module EF is connected with the emitter follower differential clock input positive port EFP, and the EF _ INN port of the emitter follower sub-module EF is connected with the emitter follower differential clock input negative port EFN; the emitter following differential clock output positive port OP1 end of the emitter following sub-module EF is respectively connected with EIP ends of the driving sub-module ECL0, the driving sub-module ECL1 and the driving sub-module ECL2, and the emitter following differential clock output negative port ON1 end of the emitter following sub-module EF is respectively connected with EIN ends of the driving sub-module ECL0, the driving sub-module ECL1 and the driving sub-module ECL 2; the EOP end of the driving sub-module ECL0 is connected with an ECL driving differential clock output positive end QP0, and the EON end thereof is connected with an ECL driving differential clock output negative end QN 0; the EOP end of the driving sub-module ECL1 is connected with an ECL driving differential clock output positive end QP1, and the EON end thereof is connected with an ECL driving differential clock output negative end QN 1; the ECL driving submodule ECL2 has its EOP terminal ECL driving positive differential clock output terminal QP2 and its EON terminal ECL driving negative differential clock output terminal QN 2.
Optionally, the emitter follower submodule EF includes NPN bipolar transistors N18 to N21 and resistors R18 to R21; the base electrode of the NPN type bipolar transistor N18 and one end of the resistor R18 are both connected with the emitter following differential clock input positive sub-port EF _ INP, and the other end of the resistor R18 is connected with the power supply VDD; the base electrode of the NPN type bipolar transistor N19 and one end of the resistor R19 are both connected with an emitter following differential clock input negative sub-port EF _ INN, and the other end of the resistor R19 is connected with a power supply VDD; the base electrode of the NPN type bipolar tube N20 and the base electrode of the NPN type bipolar tube N21 are connected with a fourth bias voltage input port V BIAS4 The emitter of the NPN bipolar transistor N18 and the collector of the NPN bipolar transistor N20 are both connected to the emitter follower differential clock output positive port OP1, and the emitter of the NPN bipolar transistor N19 and the collector of the NPN bipolar transistor N21 are both connected to the emitter follower differential clock output negative port ON 1.
Optionally, each driving submodule has the same structure and includes NPN bipolar transistors N22 to N27, resistors R20 to R26, and a capacitor C1; wherein the content of the first and second substances,
the base electrode of the NPN type bipolar tube N24 is connected with the ECL driving submodule differential clock input positive port EIP; an emitter of the NPN bipolar transistor N24 is connected to one end of a resistor R24, one end of a capacitor C1 and a collector of the NPN bipolar transistor N22, respectively, and the other end of the resistor R24 is connected to the other end of a capacitor C1, an emitter of the NPN bipolar transistor N25 and a collector of the NPN bipolar transistor N23, respectively; the base electrode of the NPN bipolar tube N25 is connected with the ECL drive submodule differential clock input negative port EIN; NPThe base electrode of the N-type diode N22 and the base electrode of the NPN-type diode N23 are both connected with a fifth bias voltage input port V BIAS5 (ii) a An emitter of the NPN type diode N22 is connected with one end of a resistor R20, and the other end of the resistor R20 is grounded GND; an emitter of the NPN type diode N23 is connected with one end of a resistor R21, and the other end of the resistor R21 is grounded GND; a collector of the NPN-type diode N24 is connected to a base of the NPN-type diode N26 and one end of the resistor R22, respectively, the other end of the resistor R22 is connected to the power supply VDD, a collector of the NPN-type diode N25 is connected to a base of the NPN-type diode N27 and one end of the resistor R23, respectively, and the other end of the resistor R23 is connected to the power supply VDD; the collector of the NPN type bipolar tube N26 and the collector of the NPN type bipolar tube N27 are both connected with a power supply VDD; an emitter of the NPN bipolar transistor N26 is connected with an ECL driving submodule differential clock output negative port EON through a resistor R25; the emitter of the NPN bipolar transistor N27 is connected with the positive port EOP of the differential clock output of the ECL driving submodule through a resistor R26.
Optionally, the high-frequency clock fanout device is designed based on a high-performance SiGe HBT device.
The invention provides a high-frequency clock fanout device which comprises an input selection module, an amplification module, a fanout module and a plurality of output driving modules. The input selection module selects an input clock channel; the amplifying module is used for recovering and amplifying differential clock signals; the fan-out module distributes one path of differential clock signals to a plurality of paths of clock channels; the output driving modules respectively convert the multi-path clock signals into LVPECL level output, and the loading capacity of a clock driving belt is improved.
The invention has the following beneficial effects:
(1) the high-frequency clock fan-out device has the advantages that two paths of differential input clock signals can be selected and are selected through the SEL signal ports. When SEL is 0, selecting a first clock channel for input; when SEL is 1, selecting a second clock channel for input, so that the flexibility of clock input selection is improved, and the application is convenient;
(2) the invention improves the channel number and the driving capability of the fan-out clock by a mode of twice clock fan-out. The selected input clock is fanned out in a fanout stage for the first time and is respectively input to the output driving module; and in the output driving stage for the second time, the clock firstly passes through the emitter follower submodule to adjust the direct current working point and then enters a plurality of ECL driving submodules to form a plurality of paths of high-speed LVPECL level clock signal outputs. The emitter follower sub-module isolates the two-stage amplification circuit, so that the bandwidth can be effectively expanded;
(3) the flow sheet is designed based on the SiGe HBT device, the advantages of high characteristic frequency and low noise of the HBT device are fully exerted, and the high-frequency low-noise clock fan-out device with frequency above 5GHz, extremely low additional phase noise and jitter can be realized through verification.
Drawings
FIG. 1 is a schematic diagram of a high frequency clock fanout configuration provided by the present invention;
FIG. 2 is a schematic diagram of an input selection module;
FIG. 3 is a schematic structural diagram of a fan-out module;
FIG. 4 is a schematic diagram of a fan-out sub-module;
FIG. 5 is a schematic diagram of an output driver module;
fig. 6 is a schematic diagram of the structure of emitter follower submodule EF;
fig. 7 is a schematic structural diagram of the driving submodule.
Detailed Description
The high frequency clock fanout proposed by the present invention is further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a high-frequency clock fanout device, and the whole structure of the high-frequency clock fanout device is shown in figure 1. The high-frequency clock fanout device comprises an input selection module 1, an amplification module 2, a fanout module 3 and a plurality of output driving modules 4. The input selection module 1 is used for selecting an input clock channel; the amplifying module 2 is used for recovering and amplifying differential clock signals; the fan-out module 3 distributes one path of differential clock signals to a plurality of paths of clock channels; the output driving modules 4 respectively convert the multi-path clock signals into LVPECL level output, and the loading capacity of a clock driving belt is improved. Further, the high-frequency clock fan-out device further comprises a band gap reference module 5 and a bias module 6, wherein the band gap reference module 5 is connected with the input selection module 1, the amplification module 2 and the fan-out module 3 respectively, and the bias module 5 is connected with the band gap reference module 6. The bias module 5 and the bandgap reference module 6 provide stable bias voltage and current to the selection module 1, the amplification module 2 and the fan-out module 3.
Specifically, as shown in fig. 2, a schematic structural diagram of the input selection module 1 is shown. The input selection module 1 comprises NPN type bipolar tubes N1-N10, PNP type bipolar tubes P1-P4 and resistors R1-R12; wherein, the base of NPN type diode N1 is connected with reference voltage input end V REF (ii) a One end of the resistor R12 is connected with an input selection port SEL, and the other end is connected with the base electrode of the NPN type bipolar transistor N2; the base electrode of the NPN bipolar transistor N3, the base electrode of the NPN bipolar transistor N6, the base electrode of the NPN bipolar transistor N7 and the first bias voltage input port V BIAS1 The base of the NPN type diode N10 is connected with a second bias voltage input port V BIAS2 The collector of the PNP type diode P1 is connected with the first clock channel bias current output port I0, and the collector of the PNP type diode P4 is connected with the second clock channel bias current output port I1; a collector of the NPN type diode N1 is respectively connected with a base of the NPN type diode N4 and one end of a resistor R1, and the other end of the resistor R1 is connected with a power supply VDD; a collector of the NPN type diode N2 is respectively connected with a base of the NPN type diode N5 and one end of a resistor R2, and the other end of the resistor R2 is connected with a power supply VDD; an emitter of the NPN type bipolar tube N1 is respectively connected with an emitter of the NPN type bipolar tube N2 and a collector of the NPN type bipolar tube N3, an emitter of the NPN type bipolar tube N3 is connected with one end of a resistor R8, and the other end of the resistor R8 is grounded GND; a collector of the NPN-type bipolar tube N4 is connected to a collector of the NPN-type bipolar tube N5 and one end of a resistor R3, respectively, the other end of the resistor R3 is connected to the power supply VDD, and an emitter of the NPN-type bipolar tube N4 is connected to a collector of the NPN-type bipolar tube N6 and a base of the NPN-type bipolar tube N9, respectively; the emitter of the NPN type bipolar tube N5 is respectively connected with the collector of the NPN type bipolar tube N7 and the base of the NPN type bipolar tube N8, and the emitter of the NPN type bipolar tube N6The other end of the resistor R9 is connected with a power supply GND, the emitter of the NPN-type diode N7 is connected with one end of the resistor R10, and the other end of the resistor R10 is grounded GND; an emitter of the NPN type bipolar tube N8 is respectively connected with an emitter of the NPN type bipolar tube N9 and a collector of the NPN type bipolar tube N10, an emitter of the NPN type bipolar tube N10 is connected with one end of a resistor R11, and the other end of the resistor R11 is grounded to GND; the base electrode of the PNP type bipolar tube P1 is respectively connected with the base electrode of the PNP type bipolar tube P2, the collector electrode of the PNP type bipolar tube P2 and the collector electrode of the NPN type bipolar tube N8; the emitter of the PNP type bipolar tube P1 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with a power supply VDD, the emitter of the PNP type bipolar tube P2 is connected with one end of a resistor R5, and the other end of the resistor R5 is connected with the power supply VDD; the base of PNP type bipolar tube P4 connects PNP type bipolar tube P3's base, PNP type bipolar tube P3's collector and NPN type bipolar tube N9's collector respectively, and PNP type bipolar tube P4's emitter meets resistance R7's one end, resistance R7's another termination power VDD, PNP type bipolar tube P3's emitter meets resistance R6's one end, resistance R6's another termination power VDD.
Referring to fig. 3, the fan-out module 2 includes NPN bipolar transistors N11 to N14, resistors R13 to R16, and fan-out submodules FO1 to FON, where N may be any integer between 1 to 4; the base electrode of the NPN type diode N11 and one end of the resistor R13 are both connected with the positive port INP of the differential clock input, and the other end of the resistor R13 is connected with the power supply VDD; the base electrode of the NPN type bipolar transistor N12 and one end of the resistor R14 are both connected with the negative port INN of the differential clock input, and the other end of the resistor R14 is connected with the power supply VDD; the collector of the NPN bipolar transistor N11 and the collector of the NPN bipolar transistor N12 are both connected with a power supply VDD, the base of the NPN bipolar transistor N13, the base of the NPN bipolar transistor N14 and VB ports of the fan-out sub-modules FO 1-FON are both connected with a third bias voltage input port V BIAS3 (ii) a An emitter of the NPN type diode N13 is connected with one end of a resistor R15, and the other end of the resistor R15 is grounded GND; an emitter of the NPN type diode N14 is connected with one end of a resistor R16, and the other end of the resistor R16 is connected with the GND; an emitter of the NPN type diode N11 is respectively connected with a collector of the NPN type diode N13 and IP ports of the fan-out submodules FO 1-FON; the emitters of the NPN type diodes N12 are respectively connected with the collectors of the NPN type diodes N14The IN ports of the pole and fan-out submodules FO 1-FON; the OP port of the fan-out submodule FO1 is connected with a fan-out submodule differential clock output positive port FOP1, and the ON port of the fan-out submodule FO1 is connected with a fan-out submodule differential clock output negative port FON 1; ...; the OP port of the fan-out submodule FON is connected with the positive output port FOPN of the fan-out submodule differential clock, and the ON port of the fan-out submodule FON is connected with the negative output port FONN of the fan-out submodule differential clock.
The fan-out module 3 comprises fan-out submodules FO 1-FON, N can be any integer between 1-4, and the driving capability of a rear-stage clock is improved in a first clock fan-out mode. The fan-out submodules are identical in structure and respectively comprise NPN bipolar transistors N15-N17 and a resistor R17, as shown in FIG. 4. The base of the NPN type bipolar tube N16 is connected with the input differential clock positive port IP, the base of the NPN type bipolar tube N15 is connected with the input differential clock negative port IN, the base of the NPN type bipolar tube N17 is connected with the bias voltage port VB, the emitter of the NPN type bipolar tube N17 is connected with one end of the resistor R17, the other end of the resistor R17 is grounded GND, and the collector of the NPN type bipolar tube N17 is respectively connected with the emitter of the NPN type bipolar tube N15 and the emitter of the NPN type bipolar tube N16; the collector of the NPN-type diode N15 is connected to the positive output differential clock port OP, and the collector of the NPN-type diode N16 is connected to the negative output differential clock port ON.
The high-frequency clock fan-out device comprises a plurality of output driving modules 4, the number of the output driving modules 4 is the same as that of fan-out submodules, and in the first embodiment, the number of the output driving modules 4 is 4. Each output drive module comprises an emitter follower submodule EF and drive submodules ECL 0-ECL 2. And through a second clock fan-out mode, the driving capability of a rear-stage clock is further improved, and the fan-out function of a plurality of paths of high-frequency clocks is realized. Referring to fig. 5, the EF _ INP port of the emitter follower sub-module EF is connected to the emitter follower differential clock input positive port EFP, and the EF _ INN port thereof is connected to the emitter follower differential clock input negative port EFN; the emitter following differential clock output positive port OP1 end of the emitter following sub-module EF is respectively connected with EIP ends of the driving sub-module ECL0, the driving sub-module ECL1 and the driving sub-module ECL2, and the emitter following differential clock output negative port ON1 end of the emitter following sub-module EF is respectively connected with EIN ends of the driving sub-module ECL0, the driving sub-module ECL1 and the driving sub-module ECL 2; the EOP end of the driving sub-module ECL0 is connected with an ECL driving differential clock output positive end QP0, and the EON end thereof is connected with an ECL driving differential clock output negative end QN 0; the EOP end of the driving sub-module ECL1 is connected with an ECL driving differential clock output positive end QP1, and the EON end thereof is connected with an ECL driving differential clock output negative end QN 1; the ECL driving submodule ECL2 has its EOP terminal ECL driving positive differential clock output terminal QP2 and its EON terminal ECL driving negative differential clock output terminal QN 2.
Further, fig. 6 is a schematic structural diagram of the emitter follower sub-module EF. The emitter follower submodule EF comprises NPN bipolar tubes N18-N21 and resistors R18-R21; the base electrode of the NPN type bipolar transistor N18 and one end of the resistor R18 are both connected with the emitter following differential clock input positive sub-port EF _ INP, and the other end of the resistor R18 is connected with the power supply VDD; the base electrode of the NPN type bipolar transistor N19 and one end of the resistor R19 are both connected with an emitter following differential clock input negative sub-port EF _ INN, and the other end of the resistor R19 is connected with a power supply VDD; the base electrode of the NPN type bipolar tube N20 and the base electrode of the NPN type bipolar tube N21 are connected with a fourth bias voltage input port V BIAS4 The emitter of the NPN bipolar transistor N18 and the collector of the NPN bipolar transistor N20 are both connected to the emitter following differential clock output positive port OP1, and the emitter of the NPN bipolar transistor N19 and the collector of the NPN bipolar transistor N21 are both connected to the emitter following differential clock output negative port ON 1. Furthermore, each driving submodule has the same structure and comprises NPN bipolar transistors N22-N27, resistors R20-R26 and a capacitor C1, as shown in fig. 7. The base electrode of the NPN type bipolar tube N24 is connected with the ECL driving submodule differential clock input positive port EIP; an emitter of the NPN bipolar transistor N24 is connected to one end of a resistor R24, one end of a capacitor C1 and a collector of the NPN bipolar transistor N22, respectively, and the other end of the resistor R24 is connected to the other end of a capacitor C1, an emitter of the NPN bipolar transistor N25 and a collector of the NPN bipolar transistor N23, respectively; the base electrode of the NPN bipolar tube N25 is connected with the ECL drive submodule differential clock input negative port EIN; the base electrode of the NPN type bipolar tube N22 and the base electrode of the NPN type bipolar tube N23 are connected with a fifth bias voltage input port V BIAS5 (ii) a An emitter of the NPN type diode N22 is connected with one end of a resistor R20, and the other end of the resistor R20 is grounded GND; of NPN type diode N23One end of an emitter electrode connecting resistor R21, and the other end of the resistor R21 is grounded GND; a collector of the NPN-type diode N24 is connected to a base of the NPN-type diode N26 and one end of the resistor R22, respectively, the other end of the resistor R22 is connected to the power supply VDD, a collector of the NPN-type diode N25 is connected to a base of the NPN-type diode N27 and one end of the resistor R23, respectively, and the other end of the resistor R23 is connected to the power supply VDD; the collector of the NPN type bipolar tube N26 and the collector of the NPN type bipolar tube N27 are both connected with a power supply VDD; an emitter of the NPN bipolar transistor N26 is connected with an ECL driving submodule differential clock output negative port EON through a resistor R25; the emitter of the NPN bipolar transistor N27 is connected with the positive port EOP of the differential clock output of the ECL driving submodule through a resistor R26.
In the high-frequency clock fan-out device of the first embodiment, a 0.18 μm SiGe HBT device is adopted to design a tape, the voltage of a power supply VDD is 3.3V, the output voltage of the bandgap reference module 6 is 2.1V, the gain of the amplification module 2 is 6dB, when the clock frequency is 7.5GHz, 12 clocks are fanned out, the differential output swing is greater than 1.6V, the rise time of the output clock is 61ps, the fall time is 57ps, the skew between the clocks is less than 20ps, the additional phase noise performance is-160.75 dBc/Hz @1MHz, and the additional jitter is 50 fs.
The high-frequency clock fan-out circuit provided by the invention is suitable for designing a high-frequency high-performance clock fan-out buffer with the frequency of more than 5GHz, and can realize the compromise between high frequency and multi-path fan-out, low noise and low jitter performance based on the existing mature SiGe HBT process platform.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (7)
1. A high frequency clock fanout, comprising:
the input selection module selects an input clock channel;
the amplifying module is used for recovering and amplifying the differential clock signal;
the fan-out module distributes one path of differential clock signals to a plurality of paths of clock channels;
the output driving modules are used for converting the multi-path clock signals into LVPECL level output respectively and improving the loading capacity of a clock driving belt;
the high-frequency clock fan-out device also comprises a band gap reference module and a bias module, wherein the band gap reference module is respectively connected with the input selection module, the amplification module and the fan-out module, and the bias module is connected with the band gap reference module;
the input selection module comprises NPN type bipolar tubes N1-N10, PNP type bipolar tubes P1-P4 and resistors R1-R12; wherein, the base of NPN type diode N1 is connected with reference voltage input end V REF (ii) a One end of the resistor R12 is connected with an input selection port SEL, and the other end is connected with the base electrode of the NPN type bipolar transistor N2; the base electrode of the NPN bipolar transistor N3, the base electrode of the NPN bipolar transistor N6, the base electrode of the NPN bipolar transistor N7 and the first bias voltage input port V BIAS1 The base of the NPN type diode N10 is connected with a second bias voltage input port V BIAS2 The collector of the PNP type diode P1 is connected with the first clock channel bias current output port I0, and the collector of the PNP type diode P4 is connected with the second clock channel bias current output port I1; a collector of the NPN type diode N1 is respectively connected with a base of the NPN type diode N4 and one end of a resistor R1, and the other end of the resistor R1 is connected with a power supply VDD; a collector of the NPN type diode N2 is respectively connected with a base of the NPN type diode N5 and one end of a resistor R2, and the other end of the resistor R2 is connected with a power supply VDD; an emitter of the NPN type bipolar tube N1 is respectively connected with an emitter of the NPN type bipolar tube N2 and a collector of the NPN type bipolar tube N3, an emitter of the NPN type bipolar tube N3 is connected with one end of a resistor R8, and the other end of the resistor R8 is grounded GND; a collector of the NPN-type bipolar tube N4 is connected to a collector of the NPN-type bipolar tube N5 and one end of a resistor R3, respectively, the other end of the resistor R3 is connected to the power supply VDD, and an emitter of the NPN-type bipolar tube N4 is connected to a collector of the NPN-type bipolar tube N6 and a base of the NPN-type bipolar tube N9, respectively; the emitter of the NPN-type bipolar tube N5 is respectively connected with the collector of the NPN-type bipolar tube N7 and the base of the NPN-type bipolar tube N8, the emitter of the NPN-type bipolar tube N6 is connected with one end of a resistor R9, the other end of the resistor R9 is connected with a power supply GND, the emitter of the NPN-type bipolar tube N7 is connected with one end of a resistor R10, and the other end of the resistor R10 is connected with the other end of the resistor R10The end is grounded GND; an emitter of the NPN type bipolar tube N8 is respectively connected with an emitter of the NPN type bipolar tube N9 and a collector of the NPN type bipolar tube N10, an emitter of the NPN type bipolar tube N10 is connected with one end of a resistor R11, and the other end of the resistor R11 is grounded to GND; the base electrode of the PNP type bipolar tube P1 is respectively connected with the base electrode of the PNP type bipolar tube P2, the collector electrode of the PNP type bipolar tube P2 and the collector electrode of the NPN type bipolar tube N8; the emitter of the PNP type bipolar tube P1 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with a power supply VDD, the emitter of the PNP type bipolar tube P2 is connected with one end of a resistor R5, and the other end of the resistor R5 is connected with the power supply VDD; the base of PNP type bipolar tube P4 connects PNP type bipolar tube P3's base, PNP type bipolar tube P3's collector and NPN type bipolar tube N9's collector respectively, and PNP type bipolar tube P4's emitter meets resistance R7's one end, resistance R7's another termination power VDD, PNP type bipolar tube P3's emitter meets resistance R6's one end, resistance R6's another termination power VDD.
2. The high frequency clock fanout of claim 1, wherein the fan-out module comprises NPN bipolar transistors N11-N14, resistors R13-R16 and fan-out submodules FO 1-FON, wherein N is any integer between 1-4; wherein the content of the first and second substances,
the base electrode of the NPN type bipolar transistor N11 and one end of the resistor R13 are both connected with the positive port INP of the differential clock input, and the other end of the resistor R13 is connected with the power supply VDD; the base electrode of the NPN type bipolar transistor N12 and one end of the resistor R14 are both connected with the negative port INN of the differential clock input, and the other end of the resistor R14 is connected with the power supply VDD; the collector of the NPN bipolar transistor N11 and the collector of the NPN bipolar transistor N12 are both connected with a power supply VDD, the base of the NPN bipolar transistor N13, the base of the NPN bipolar transistor N14 and VB ports of the fan-out sub-modules FO 1-FON are both connected with a third bias voltage input port V BIAS3 (ii) a An emitter of the NPN type diode N13 is connected with one end of a resistor R15, and the other end of the resistor R15 is connected with the GND; an emitter of the NPN type diode N14 is connected with one end of a resistor R16, and the other end of the resistor R16 is connected with the GND; an emitter of the NPN type diode N11 is respectively connected with a collector of the NPN type diode N13 and IP ports of the fan-out submodules FO 1-FON; the emitter of the NPN type diode N12 is respectively connected with the collector of the NPN type diode N14 andthe fan-out submodules FO 1-IN ports of FON; the OP port of the fan-out submodule FO1 is connected with a fan-out submodule differential clock output positive port FOP1, and the ON port of the fan-out submodule FO1 is connected with a fan-out submodule differential clock output negative port FON 1; ...; the OP port of the fan-out submodule FON is connected with the positive output port FOPN of the fan-out submodule differential clock, and the ON port of the fan-out submodule FON is connected with the negative output port FONN of the fan-out submodule differential clock.
3. The high frequency clock fanout of claim 2, wherein each fan-out sub-module is identical in structure and includes NPN bipolar transistors N15-N17 and resistors R17; wherein the content of the first and second substances,
the base of the NPN type bipolar tube N16 is connected with the input differential clock positive port IP, the base of the NPN type bipolar tube N15 is connected with the input differential clock negative port IN, the base of the NPN type bipolar tube N17 is connected with the bias voltage port VB, the emitter of the NPN type bipolar tube N17 is connected with one end of the resistor R17, the other end of the resistor R17 is grounded GND, and the collector of the NPN type bipolar tube N17 is respectively connected with the emitter of the NPN type bipolar tube N15 and the emitter of the NPN type bipolar tube N16; the collector of the NPN-type diode N15 is connected to the positive output differential clock port OP, and the collector of the NPN-type diode N16 is connected to the negative output differential clock port ON.
4. The high frequency clock fanout of claim 1, wherein each of said output drive modules includes an emitter follower sub-module EF and drive sub-modules ECL 0-ECL 2; wherein the content of the first and second substances,
the EF _ INP port of the emitter follower sub-module EF is connected with the emitter follower differential clock input positive port EFP, and the EF _ INN port of the emitter follower sub-module EF is connected with the emitter follower differential clock input negative port EFN; the emitter following differential clock output positive port OP1 end of the emitter following sub-module EF is respectively connected with EIP ends of the driving sub-module ECL0, the driving sub-module ECL1 and the driving sub-module ECL2, and the emitter following differential clock output negative port ON1 end of the emitter following sub-module EF is respectively connected with EIN ends of the driving sub-module ECL0, the driving sub-module ECL1 and the driving sub-module ECL 2; the EOP end of the driving sub-module ECL0 is connected with an ECL driving differential clock output positive end QP0, and the EON end thereof is connected with an ECL driving differential clock output negative end QN 0; the EOP end of the driving sub-module ECL1 is connected with an ECL driving differential clock output positive end QP1, and the EON end thereof is connected with an ECL driving differential clock output negative end QN 1; the EOP terminal of the driving sub-module ECL2 is connected with the ECL driving differential clock output positive terminal QP2, and the EON terminal thereof is connected with the ECL driving differential clock output negative terminal QN 2.
5. The high frequency clock fanout of claim 4, wherein said emitter follower submodule EF includes NPN bipolar transistors N18-N21, resistors R18-R21; the base electrode of the NPN bipolar transistor N18 and one end of the resistor R18 are both connected with the emitter following differential clock input positive sub-port EF _ INP, and the other end of the resistor R18 is connected with the power supply VDD; the base electrode of the NPN type bipolar transistor N19 and one end of the resistor R19 are both connected with an emitter following differential clock input negative sub-port EF _ INN, and the other end of the resistor R19 is connected with a power supply VDD; the base electrode of the NPN type bipolar tube N20 and the base electrode of the NPN type bipolar tube N21 are connected with a fourth bias voltage input port V BIAS4 The emitter of the NPN bipolar transistor N18 and the collector of the NPN bipolar transistor N20 are both connected to the emitter follower differential clock output positive port OP1, and the emitter of the NPN bipolar transistor N19 and the collector of the NPN bipolar transistor N21 are both connected to the emitter follower differential clock output negative port ON 1.
6. The high frequency clock fanout of claim 4, wherein each driving submodule is identical in structure and comprises NPN bipolar transistors N22-N27, resistors R20-R26 and a capacitor C1; wherein the content of the first and second substances,
the base electrode of the NPN type bipolar tube N24 is connected with the ECL driving submodule differential clock input positive port EIP; an emitter of the NPN bipolar transistor N24 is connected to one end of a resistor R24, one end of a capacitor C1 and a collector of the NPN bipolar transistor N22, respectively, and the other end of the resistor R24 is connected to the other end of a capacitor C1, an emitter of the NPN bipolar transistor N25 and a collector of the NPN bipolar transistor N23, respectively; the base electrode of the NPN bipolar tube N25 is connected with the ECL drive submodule differential clock input negative port EIN; the base electrode of the NPN type bipolar tube N22 and the base electrode of the NPN type bipolar tube N23 are connected with a fifth bias voltage input port V BIAS5 (ii) a The emitter of the NPN diode N22 is connected to one end of a resistor R20, which is connected to the emitter of the NPN diode N22The other end of R20 is grounded GND; an emitter of the NPN type diode N23 is connected with one end of a resistor R21, and the other end of the resistor R21 is grounded GND; a collector of the NPN-type diode N24 is connected to a base of the NPN-type diode N26 and one end of the resistor R22, respectively, the other end of the resistor R22 is connected to the power supply VDD, a collector of the NPN-type diode N25 is connected to a base of the NPN-type diode N27 and one end of the resistor R23, respectively, and the other end of the resistor R23 is connected to the power supply VDD; the collector of the NPN type bipolar tube N26 and the collector of the NPN type bipolar tube N27 are both connected with a power supply VDD; an emitter of the NPN bipolar transistor N26 is connected with an ECL driving submodule differential clock output negative port EON through a resistor R25; the emitter of the NPN bipolar transistor N27 is connected with the positive port EOP of the differential clock output of the ECL driving submodule through a resistor R26.
7. The high frequency clock fanout of any of claims 1-6, wherein the high frequency clock fanout is based on a high performance SiGe HBT device design.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811434033.1A CN109684670B (en) | 2018-11-28 | 2018-11-28 | High-frequency clock fan-out device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811434033.1A CN109684670B (en) | 2018-11-28 | 2018-11-28 | High-frequency clock fan-out device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109684670A CN109684670A (en) | 2019-04-26 |
| CN109684670B true CN109684670B (en) | 2022-08-02 |
Family
ID=66184449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811434033.1A Active CN109684670B (en) | 2018-11-28 | 2018-11-28 | High-frequency clock fan-out device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109684670B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1838538A (en) * | 2005-03-21 | 2006-09-27 | 半导体元件工业有限责任公司 | Fan out buffer and method therefor |
| CN106603045A (en) * | 2016-12-16 | 2017-04-26 | 中国电子科技集团公司第五十四研究所 | Clock transmission switching and quick stop/restart circuit |
| CN108616272A (en) * | 2018-05-15 | 2018-10-02 | 原时（荆门）电子科技有限公司 | A kind of high-precision low jitter time frequency signal switching device |
-
2018
- 2018-11-28 CN CN201811434033.1A patent/CN109684670B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1838538A (en) * | 2005-03-21 | 2006-09-27 | 半导体元件工业有限责任公司 | Fan out buffer and method therefor |
| CN106603045A (en) * | 2016-12-16 | 2017-04-26 | 中国电子科技集团公司第五十四研究所 | Clock transmission switching and quick stop/restart circuit |
| CN108616272A (en) * | 2018-05-15 | 2018-10-02 | 原时（荆门）电子科技有限公司 | A kind of high-precision low jitter time frequency signal switching device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109684670A (en) | 2019-04-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7321242B2 (en) | Integrated circuit with breakdown voltage multiplier | |
| US7982538B2 (en) | Differential output circuit and communication device | |
| US6297685B1 (en) | High-speed fully-compensated low-voltage differential driver/translator circuit arrangement | |
| US6144234A (en) | Sample hold circuit and semiconductor device having the same | |
| CN112019176A (en) | H-bridge integrated laser driver | |
| EP1625656B1 (en) | Circuit for improved differential amplifier and other applications | |
| CN114124092A (en) | Analog front end circuit of analog-to-digital converter and control method | |
| CN109684670B (en) | High-frequency clock fan-out device | |
| EP3350945A1 (en) | An optical receiver with a cascode front end | |
| WO2005119916A1 (en) | Low voltage high-speed differential logic devices and method of use thereof | |
| CN111313228B (en) | Laser driving circuit and light emitting system | |
| Wang et al. | A new current-mode incremental signaling scheme with applications to Gb/s parallel links | |
| GB2402277A (en) | Current mode logic driver with adjustable common-mode level | |
| CN112994623B (en) | Power detection circuit applied to power amplifier | |
| JP2881304B2 (en) | Line driver design method and integrated circuit transceiver | |
| CN111756343B (en) | Rail-to-rail output circuit for high-speed operational amplifier | |
| Shi et al. | A 112Gb/s low-noise PAM-4 linear optical receiver in 28nm CMOS | |
| Dash | A variable bandwidth, power-scalable optical receiver front-end | |
| JPH0452654B2 (en) | ||
| WO2023226152A1 (en) | Dac direct-current coupling output circuit | |
| CN115021694B (en) | Large-output swing driving circuit | |
| US6157255A (en) | High performance operational amplifier | |
| Quigley et al. | Current mode transceiver logic,(Cmtl) for reduced swing CMOS, chip to chip communication | |
| Kishishita et al. | Prototype of simultaneous bidirectional data-transmitter in 65 nm CMOS | |
| CN117955572A (en) | Optical modulator driver and optical transmitter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |