CN109684248A - RS-422 interface adapter towards picogram bus - Google Patents
RS-422 interface adapter towards picogram bus Download PDFInfo
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- CN109684248A CN109684248A CN201811594241.8A CN201811594241A CN109684248A CN 109684248 A CN109684248 A CN 109684248A CN 201811594241 A CN201811594241 A CN 201811594241A CN 109684248 A CN109684248 A CN 109684248A
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- 230000005540 biological transmission Effects 0.000 abstract description 13
- 238000004891 communication Methods 0.000 description 7
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- 238000013461 design Methods 0.000 description 4
- 230000006855 networking Effects 0.000 description 4
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- 238000005516 engineering process Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 208000033748 Device issues Diseases 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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- General Engineering & Computer Science (AREA)
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Abstract
The invention discloses a kind of RS-422 interface adapters towards picogram bus, including FPGA control module and LVDS signal transmitting and receiving module, RS-422 interface is equipped in FPGA control module, using FPGA control module as control core, the bus logic signal that RS-422 terminal is passed to is converted into LVDS bus level signal and the level signal for controlling LVDS signal transmitting and receiving module is received and sent, while the level signal received from LVDS signal transmitting and receiving module is converted into RS-422 bus logic signal and is sent to RS-422 terminal；LVDS signal transmitting and receiving module includes the DS92LV1023 chip for sending signal and the DS92LV1224 chip for receiving signal, it receives and is passed to FPGA control module after chip receives bus level signal and is converted to RS-422 bus logic signal, the present invention realizes the transmission of the data in terminal and bus with RS-422 interface between other equipment.
Description
Technical field
The present invention relates to RS-422 interface adapter design field, specially a kind of RS-422 towards picogram bus
Interface adapter.
Background technique
The limited cascade developed by Northcentral University from network forming network instrument bus (picogram bus), be by fieldbus and
Instrument bus fusion generates the Networked Instrument bus of novel concept, and the number of being disclosed is CN106059927A's to the technology
Patent application publication, the bus have the following characteristics that 1. high-speed: due to the network structure using special designing, it can be achieved that end
Opposite end high rate data transmission；And support multiterminal parallel transmission in network, infinitely promote aggregate network throughput；2. medium is unrelated: can
LVDS, optical fiber, twisted pair etc. is selected to be used as transmission medium according to project characteristic, it might even be possible to be used in mixed way, adaptability is extremely strong；③
High testability: it is accessed from any one terminal interface, any equipment of the whole network can be rapidly completed with all terminal calleds of the whole network
Detection, thoroughly changes existing test pattern and effect；4. multi-selection: optional -422 interface of High-Speed RS of terminal interface connects parallel
Mouthful.
Serial line interface is realized by RS-422 bussing technique in picogram bus.RS-422(Serial Peripheral Interface (SPI)) total linear system
System is a kind of synchronous serial Peripheral Interface communicated for handling various peripheral equipments with main equipment, is communicated in a serial fashion
Information exchange.It is worked in a manner of principal and subordinate, a main equipment is usually had under this operating mode and multiple from equipment,
When main equipment from equipment with carrying out data exchange and communicating, RS-422 bus is usually made of four lines, it may be assumed that is set based on SDI
Standby serial data in line, SDO serial data out line, four bars of SCLK synchronous serial clock line and CS slave selection line
Line is controlled by host.
The advantages of serial protocol RS-422 has line few, and speed is fast, high reliablity, but its to be suitable only for short distance logical
Letter, between carrying out plate or when long haul communication on plate, rate and stability are difficult to meet communication requirement, and LVDS(low voltage difference
Sub-signal) bussing technique is a kind of serial physical link technology, it may be implemented to transmit between the remote plate of 500Mbps or more,
And have many advantages, such as high speed, low in energy consumption, inhibition noise.RS- when in order to realize the long range communication between plates towards picogram bus
422 buses are directly communicated with terminal, and RS-422 bus is converted by LVDS bus, and rate and stability is made to reach logical
A kind of letter demand, it is desirable to provide interface adapter.
Summary of the invention
When the present invention is in order to solve towards picogram bus, the data of terminal device carry out long range string by RS-422 interface
Row transmission problem provides a kind of RS-422 interface adapter towards picogram bus.
The present invention is achieved by the following technical solution: a kind of RS-422 interface adapter towards picogram bus,
Including FPGA control module and LVDS signal transmitting and receiving module, RS-422 interface, the FPGA are equipped in the FPGA control module
Control module is control core, and the bus logic signal for RS-422 terminal to be passed to is converted to LVDS bus level signal simultaneously
The level signal for controlling LVDS signal transmitting and receiving module is received and is sent, while the level that will be received from LVDS signal transmitting and receiving module
Signal is converted to RS-422 bus logic signal and is sent to RS-422 terminal；The LVDS signal transmitting and receiving module includes sending signal
DS92LV1023 chip and receive the DS92LV1224 chip of signal, the DS92LV1224 chip receives bus level signal
It is passed to FPGA control module afterwards and is converted to RS-422 bus logic signal, the FPGA control module is by RS-422 bus
Logical signal is converted to LVDS bus level signal and is issued by DS92LV1023 chip.
It is invented the present invention be directed to the transmission of the data of picogram bus, according to a variety of advantages and feature of picogram bus,
It is designed to make the terminal connection device diversification of picogram bus.RS-422 towards picogram bus proposed by the invention
Interface adapter mainly includes FPGA control module and LVDS signal transmitting and receiving module, is equipped with RS- in the FPGA control module
422 interfaces, FPGA control module are the control core of entire interface adapter, mainly play control action, can be by RS-422 terminal
Incoming bus logic signal is converted to LVDS bus level signal and controls the level signal reception of LVDS signal transmitting and receiving module
With transmission, while the level signal received from LVDS signal transmitting and receiving module is converted into RS-422 bus logic signal and is sent to
RS-422 terminal, the process can be realized by the programming inside FPGA with customization；LVDS signal transmitting and receiving module mainly plays letter
Number transmitting-receiving effect comprising send signal DS92LV1023 chip and receive signal DS92LV1224 chip, both
Signal is passed to FPGA control module after receiving bus level signal and is converted to RS-422 bus by chip DS92LV1224 chip
RS-422 bus logic signal is converted to LVDS bus level signal and passed through by logical signal, FPGA control module
DS92LV1023 chip issues, in this way, the interface adapter of this RS-422 can realize the terminal with RS-422 interface
It is transmitted with the data in bus between other equipment.Concrete operations of the present invention are as follows: when RS-422 terminal issues bus logic signal
When, it is sent to the FPGA control module of interface adapter, is converted to LVDS bus level signal, then passes through DS92LV1023 core
Piece issues level signal；It, will when the DS92LV1224 chip of LVDS signal transmitting and receiving module receives LVDS bus level signal
Signal inputs FPGA control module, and is converted to RS-422 bus logic signal, then exports from FPGA control module to RS-
422 terminals.This process realizes the transmission of the data in terminal and bus with RS-422 interface between other equipment.
Compared with prior art the invention has the following advantages: the RS- provided by the present invention towards picogram bus
422 interface adapters have the advantage that (1) present invention can make the terminal connection device diversification of picogram bus.Although RS-
422 bussing techniques are not suitable for long haul communication, but due to the versatility of its technology, so that many chips are all integrated with RS-422
Interface, such as single-chip microcontroller, FPGA etc..So terminal device has lower threshold requirement when being connected to the networking of picogram bus, make
The terminal connection device of picogram bus is obtained not excessively by the constraint of technical conditions, to embody picogram bus termination connection equipment
The characteristics of diversification；(2) distance of the group network data transmission of picogram bus can be improved in the present invention.RS-422 bus is electrical
Signal is converted to the distance that data can be made to transmit after LVDS electric signal and obtains significantly being promoted very much.To improve sand
The distance of gram bus group network data transmission；(3) main equipment may be implemented to multiple parallel deployments from equipment.Due to bus networking
The application demand of middle intelligent terminal and combining unit is more and more, and performance and functional requirement are higher and higher, and RS-422 bus is to more
It has been difficult meet the needs of field application from the mode of series arrangement, and RS-422 interface can only at a time be realized to list
The configuration of one equipment.The RS-422 adaptor interface towards picogram bus researched and developed of the present invention can make RS-422 interface with
Bus networking is effectively combined, and can connect in the terminal with RS-422 interface different from equipment, and passes through picogram
Bus networking may be implemented to arbitrarily from the configuration of equipment.
Detailed description of the invention
Fig. 1 is master-plan block diagram of the invention.
Order packet format defines when Fig. 2 is data of the present invention transmission.
Fig. 3 is picogram bus system composition figure.
Specific embodiment
Below in conjunction with specific embodiment, the invention will be further described.
A kind of RS-422 interface adapter towards picogram bus includes that FPGA control module and LVDS believe as shown in Figure 1:
Number transceiver module is equipped with RS-422 interface in the FPGA control module, and the FPGA control module is control core, for will
The incoming bus logic signal of RS-422 terminal is converted to LVDS bus level signal and controls the electricity of LVDS signal transmitting and receiving module
Ordinary mail number is received and is sent, while the level signal received from LVDS signal transmitting and receiving module is converted to RS-422 bus logic
Signal is sent to RS-422 terminal；The LVDS signal transmitting and receiving module includes sending the DS92LV1023 chip of signal and receiving to believe
Number DS92LV1224 chip, the DS92LV1224 chip is passed to FPGA control module simultaneously after receiving bus level signal
RS-422 bus logic signal is converted to, RS-422 bus logic signal is converted to LVDS bus electricity by the FPGA control module
Ordinary mail number is simultaneously issued by DS92LV1023 chip.
Fig. 1 when the terminal device with RS-422 interface is connected to RS-422 interface adapter, terminal device issue
Bus logic signal accesses the RS-422 interface in FPGA control module by the RS-422 interface of itself, inside FPGA
The bus logic signal of RS-422 interface is converted to LVDS Low Voltage Differential Signal by agreement, will by DS92LV1023 transmission chip
LVDS signal is sent in picogram bus network；There is signal to need to the terminal hair with RS-422 interface in picogram bus network
It loses one's life when enabling, LVDS signal receives chip by DS92LV1224 and LVDS bus level signal is transferred in FPGA control module
LVDS signal is converted into RS-422 signal by fpga chip internal agreement, it then will by the RS-422 interface carried on FPGA
RS-422 bus logic signal is transmitted on the terminal device with RS-422 interface.
It in the present embodiment, is defined referring to fig. 2 for the format of basic command packet, data are pressed when transmitting in picogram bus network
Order packet format shown in Fig. 2 is transmitted.It is 72 packet length, i.e. 9 bytes that data, which transmit basic packet length,.All orders,
The order packet format definition that data transport behavior uses includes: mode field: indicating effect and state of order etc.；Source address
Domain: since each terminal device requires one network node of connection, when terminal device sends signal, source address field will be
The address of equipment connecting node；The node address received where the equipment issues the equipment of signal is destination address domain；Parameter
Word: the state of contained signal in register, size etc. are indicated；Verification domain: the accuracy of the order packet is examined.
It is picogram bus system composition figure referring to Fig. 3.After picogram bus, whole system is changed into tree-shaped and is coupled
Structure.Core network is gone out by the completely the same router framework of state, the idle interface of all-router can directly mount end
End equipment.Equipment with RS-422 interface directly passes through network and the communication of other terminal, and data are arrived by the automatic pathfinding of network
Up to any one equipment.The fully automated reconstruct of picogram bus, is designed without user, and network is transparent to user.Network terminal user
Interface protocol is very simple, and all command operations are all the standard frames of 9 bytes, and the threshold that user carries out product design is no more than
5 orders.As long as entire data transmission network backbone equipment is all the completely the same router of state --- it goes all out to improve routing
This kind of reliability of product of device, so that it may ensure the reliability of entire core network.Router be it is general, with model without
It closes.Originally equipment room data communication interface is by measurement master-plan, responsible under framework, and workload is huge, easily designs
Mistake.Present single machine completes the bridge joint of data between network and device core using the interface module of a standard.Equipment end communication
Interface and agreement become the internal interface agreement of stand-alone device, without measuring overall care.One router of every increase, at most may be used
To increase by 15 terminal device accesses；All signals and data, which pass through primary synthesis or gather and edit, can be directly entered network.Entirely
Net total interface equity is general, is convenient for electrical equipment integral layout.Terminal and router break down, can be from any one road
Detection device is accessed by the vacant interface of device, test and malfunction elimination directly are carried out to failed terminals.
The scope of protection of present invention is not limited to the above specific embodiment, and for those skilled in the art and
Speech, the present invention can there are many deformation and change, it is all within design and principle of the invention it is made it is any modification, improve and
Equivalent replacement should be all included within protection scope of the present invention.
Claims (1)
1. a kind of RS-422 interface adapter towards picogram bus, it is characterised in that: believe including FPGA control module and LVDS
Number transceiver module is equipped with RS-422 interface in the FPGA control module, and the FPGA control module is control core, for will
The incoming bus logic signal of RS-422 terminal is converted to LVDS bus level signal and controls the electricity of LVDS signal transmitting and receiving module
Ordinary mail number is received and is sent, while the level signal received from LVDS signal transmitting and receiving module is converted to RS-422 bus logic
Signal is sent to RS-422 terminal；The LVDS signal transmitting and receiving module includes sending the DS92LV1023 chip of signal and receiving to believe
Number DS92LV1224 chip, the DS92LV1224 chip is passed to FPGA control module simultaneously after receiving bus level signal
RS-422 bus logic signal is converted to, RS-422 bus logic signal is converted to LVDS bus electricity by the FPGA control module
Ordinary mail number is simultaneously issued by DS92LV1023 chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811594241.8A CN109684248A (en) | 2018-12-25 | 2018-12-25 | RS-422 interface adapter towards picogram bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811594241.8A CN109684248A (en) | 2018-12-25 | 2018-12-25 | RS-422 interface adapter towards picogram bus |
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| CN109684248A true CN109684248A (en) | 2019-04-26 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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-
2018
- 2018-12-25 CN CN201811594241.8A patent/CN109684248A/en active Pending
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| CN103777529A (en) * | 2012-10-24 | 2014-05-07 | 北京强度环境研究所 | Fast varying signal collector |
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| CN105262658A (en) * | 2015-10-30 | 2016-01-20 | 北京交控科技有限公司 | Switching device, field-bus topological structure, and data transmission method |
| CN105429764A (en) * | 2015-11-05 | 2016-03-23 | 山东超越数控电子有限公司 | FPGA chip, and remote transmission system and method |
| CN106059927A (en) * | 2016-05-17 | 2016-10-26 | 中北大学 | Router device enabling star configured limited cascade automatic reconstruction network and network thereof |
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