CN109672461B - DC offset compensation system and method - Google Patents
DC offset compensation system and method Download PDFInfo
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- CN109672461B CN109672461B CN201710953326.XA CN201710953326A CN109672461B CN 109672461 B CN109672461 B CN 109672461B CN 201710953326 A CN201710953326 A CN 201710953326A CN 109672461 B CN109672461 B CN 109672461B
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- H—ELECTRICITY
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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Abstract
The invention discloses a DC offset compensation system, comprising: the device comprises a signal processing path, a first compensation module, a second compensation module and a third compensation module. The first compensation module is used for compensating the direct current offset of the second sub-processing path in the signal processing path so as to enable a first direct current offset value output by the signal processing path to be smaller than or equal to a first threshold value; the second compensation module is used for compensating the direct current offset of the first sub-processing path based on the first direct current offset value so as to enable a second direct current offset value output by the signal processing path to be smaller than or equal to a second threshold value; and the third compensation module is used for compensating the direct current offset of the signal processing path based on the second direct current offset value so as to enable a third direct current offset value output by the signal processing path to be smaller than or equal to a third threshold value. The invention also discloses a DC offset compensation method.
Description
Technical Field
The present invention relates to a receiver technology of wireless communication, and in particular, to a dc offset compensation system and method.
Background
In recent years, wireless communication technology is rapidly developed, and devices with wireless communication functions, such as smart phones, tablet computers, notebook computers and the like, are more and more widely applied, so that the daily work and life of people are greatly facilitated. The need for portability of wireless devices makes low power consumption and high integration increasingly important in wireless transceiver design; in a wireless transceiver, the design of the receiver is often critical.
In a common wireless receiver structure, a zero intermediate frequency receiver has great advantages in terms of low power consumption and high integration, and is very suitable for being applied to wireless equipment of today. However, since the if signal of the zero if receiver is located at baseband, dc offsets of the mixer and if amplifier in the receiver are directly superimposed on the desired signal, which seriously affects the dynamic range of the circuit. Therefore, in order to enable the receiver to work normally, a sampling direct current offset compensation technology is needed, so that direct current offset is effectively compensated, and low-frequency noise is reduced.
In the related art, the dc offset compensation technique mainly includes ac coupling and dc negative feedback. Because the alternating current coupling technology is difficult to apply in a zero intermediate frequency receiver, a circuit for simulating a negative feedback scheme in direct current negative feedback is complex and has poor stability, and a circuit for a digital negative feedback scheme in direct current negative feedback is simple; therefore, zero intermediate frequency receivers typically employ a digital negative feedback scheme to compensate for dc offset. However, the digital negative feedback scheme is limited by the performance of the dc offset compensation system when compensating the dc offset, resulting in low compensation accuracy.
Disclosure of Invention
In order to solve the problems in the prior art, embodiments of the present invention are expected to provide a dc offset compensation system and method, which can improve the compensation accuracy of the dc offset in the receiver.
The technical scheme of the embodiment of the invention is realized as follows:
the embodiment of the invention also provides a direct current offset compensation system, which comprises: the signal processing path comprises a first sub-processing path and a second sub-processing path, and the output end of the first sub-processing path is connected with the input end of the second sub-processing path; the system further comprises: the device comprises a first compensation module, a second compensation module and a third compensation module; wherein the content of the first and second substances,
the first compensation module is used for compensating the direct current offset of the second sub-processing path so that a first direct current offset value output by the signal processing path is smaller than or equal to a first threshold value;
the second compensation module is configured to compensate for the dc offset of the first sub-processing path based on the first dc offset value, so that a second dc offset value output by the signal processing path is smaller than or equal to a second threshold;
the third compensation module is configured to compensate for the dc offset of the signal processing path based on the second dc offset value, so that a third dc offset value output by the signal processing path is smaller than or equal to a third threshold; the third threshold is less than the second threshold.
In the above solution, the system further includes: a direct current offset discrimination module; wherein the content of the first and second substances,
the direct current offset judgment module is used for detecting whether a first direct current offset value output by the signal processing path is smaller than or equal to a first threshold value or not in real time; when the first constant loss adjusting value is larger than a first threshold value, triggering the first compensation module;
the direct current offset judgment module is also used for detecting whether a second direct current offset value output by the signal processing channel is smaller than or equal to a second threshold value in real time; when the second direct current offset value is larger than a second threshold value, triggering the second compensation module;
the direct current offset judgment module is also used for detecting whether a third direct current offset value output by the signal processing path is smaller than or equal to a third threshold value in real time; and when the third direct current offset value is larger than a third threshold value, triggering the third compensation module.
In the foregoing solution, the first compensation module is specifically configured to compensate for dc offset of the second sub-processing path by injecting dc into an input end of the second sub-processing path;
the second compensation module is specifically configured to compensate for dc offset of the first sub-processing path by injecting dc into an input end of the first sub-processing path;
the third compensation module is specifically configured to compensate for dc offset of the signal processing path by injecting dc into the input end of the second sub-processing path.
In the foregoing scheme, the second compensation module is further configured to compensate for the dc offset of the first sub-processing path when the dc amount injected by the input end of the second sub-processing path is the first dc amount, so that a second dc offset value output by the signal processing path is smaller than or equal to a second threshold; the first direct current is the direct current injected by the input end of the second sub-processing path when the direct current offset value output by the signal processing path is the first direct current offset value;
the third compensation module is further configured to compensate for a dc offset of the signal processing path when the dc quantity injected at the input end of the first sub-processing path is a second dc quantity, so that a third dc offset value output by the signal processing path is smaller than or equal to a third threshold; and the second direct current quantity is the direct current quantity injected by the input end of the first sub-processing path when the direct current loss regulating value output by the signal processing path is the second direct current loss regulating value.
In the above scheme, the gain of the first sub-processing path is greater than the gain of the second sub-processing path.
The embodiment of the invention provides a direct current offset compensation method, which is applied to a signal processing path comprising a first sub-processing path and a second sub-processing path, wherein the output end of the first sub-processing path is connected with the input end of the second sub-processing path; the method comprises the following steps:
compensating the direct current offset of the second sub-processing path to enable a first direct current offset output by the signal processing path to be smaller than or equal to a first threshold value;
compensating the direct current offset of the first sub-processing path based on the first direct current offset value, so that a second direct current offset value output by the signal processing path is smaller than or equal to a second threshold value;
compensating the direct current offset of the signal processing path based on the second direct current offset value so as to enable a third direct current offset value output by the signal processing path to be smaller than or equal to a third threshold value; the third threshold is less than the second threshold.
In the foregoing solution, before the compensating for the dc offset of the second sub-processing path to make the first dc offset output by the signal processing path smaller than or equal to the first threshold, the method further includes:
detecting whether a first constant loss adjusting value output by the signal processing channel is smaller than or equal to a first threshold value in real time;
when the first dc offset is greater than a first threshold, performing compensation on the dc offset of the second sub-processing path to make the first dc offset output by the signal processing path less than or equal to the first threshold;
before the compensating the dc offset of the first sub-processing path based on the second dc offset value so that the second dc offset value output by the signal processing path satisfies a second threshold, the method further includes:
detecting whether a second direct current offset value output by the signal processing channel is smaller than or equal to a second threshold value in real time;
when the second dc offset value is greater than a first threshold, performing a step of compensating the dc offset of the first sub-processing path based on the first dc offset value, so that the second dc offset value output by the signal processing path is less than or equal to a second threshold;
before the compensating the dc offset of the signal processing path based on the second dc offset value so that the second dc offset value output by the signal processing path is less than or equal to a third threshold, the method further includes:
detecting whether a third direct current offset value output by the signal processing path is smaller than or equal to a third threshold value in real time;
when the third dc offset value is greater than a third threshold, performing compensation on the dc offset of the signal processing path based on the second dc offset value, so that the third dc offset value output by the signal processing path is less than or equal to the third threshold; and the third threshold is smaller than the second threshold.
In the foregoing solution, the compensating for the dc offset of the second sub-processing path includes: compensating the DC offset of a second sub-processing path in a mode of injecting DC into the input end of the second sub-processing path;
the compensating the dc offset of the first sub-processing path includes: compensating for DC offset of the first sub-processing path by injecting DC into an input of the first sub-processing path;
the compensating the dc offset of the signal processing path includes: and compensating the DC offset of the signal processing path by injecting DC into the input end of the second sub-processing path.
In the foregoing solution, the compensating the dc offset of the first sub-processing path based on the first dc offset value, so that a second dc offset value output by the signal processing path is smaller than or equal to a second threshold value includes:
when the direct current quantity injected into the input end of the second sub-processing path is the first direct current quantity, compensating the direct current offset of the first sub-processing path so as to enable a second direct current offset value output by the signal processing path to be smaller than or equal to a second threshold value; the first direct current is the direct current injected by the input end of the second sub-processing path when the direct current offset value output by the signal processing path is the first direct current offset value;
the compensating, based on the second dc offset value, the dc offset of the signal processing path so that a third dc offset value output by the signal processing path is less than or equal to a third threshold includes:
when the direct current quantity injected into the input end of the first sub-processing path is a second direct current quantity, compensating the direct current offset of the signal processing path so as to enable a third direct current offset value output by the signal processing path to be smaller than or equal to a third threshold value; and the second direct current quantity is the direct current quantity injected by the input end of the first sub-processing path when the direct current loss regulating value output by the signal processing path is the second direct current loss regulating value.
In the above scheme, the gain of the first sub-processing path is greater than the gain of the second sub-processing path.
It can be seen that the dc offset compensation system and method provided in the embodiments of the present invention are applied to a signal processing path including a first sub-processing path and a second sub-processing path, and an output terminal of the first sub-processing path is connected to an input terminal of the second sub-processing path. Firstly, compensating the direct current offset of the second sub-processing path to enable a first direct current offset output by the signal processing path to be smaller than or equal to a first threshold value; then, based on the first direct current offset value, compensating the direct current offset of the first sub-processing path so as to enable a second direct current offset value output by the signal processing path to be smaller than or equal to a second threshold value; finally, based on the second direct current offset value, compensating the direct current offset of the signal processing path so as to enable a third direct current offset value output by the signal processing path to be smaller than or equal to a third threshold value; the third threshold is less than the second threshold.
In this embodiment of the present invention, firstly, the dc offset of the second sub-processing path is compensated to reduce the dc offset of the second sub-processing path; then, compensating the direct current offset of the first sub-processing path to reduce the direct current offset of the first sub-processing path; and finally, integrally compensating the direct current offset of the signal processing path to reduce the direct current offset of the signal processing path to a range which does not influence the normal operation of the signal processing path.
Because the DC offset of the second sub-processing path is compensated before the DC offset of the first sub-processing path is superposed on the DC offset of the second sub-processing path; and after compensating the first sub-processing path, also performing overall compensation on the signal processing path. Therefore, by segmenting the signal processing path and compensating the DC offset of the segmented signal processing path in three stages, compared with the prior art, the performance index of the compensation module in the DC offset compensation system can be reduced under the condition that the working state of the signal processing path is constant. Accordingly, under the condition that the performance of the direct current offset compensation system is the same as that of the existing direct current offset compensation system, even under the condition of reducing the performance requirement, the compensation precision of the direct current offset can be improved. In addition, the compensation speed can be improved, the realization difficulty of a direct current offset compensation system is reduced, the system scale is reduced, and the power consumption and the area are reduced.
Drawings
FIG. 1 is a schematic diagram of a DC offset compensation system based on an AC coupling scheme;
FIG. 2 is a schematic diagram of a single-path DC offset compensation system based on a digital negative feedback scheme;
FIG. 3 is a schematic diagram of a sectional DC offset compensation system based on a digital negative feedback scheme;
FIG. 4 is a schematic diagram of an implementation of a conventional DC offset compensation method based on a segmented DC offset compensation system;
FIG. 5 is a schematic diagram of a flow chart of a first implementation of the DC offset compensation method according to the present invention;
FIG. 6 is a schematic diagram of another structure of a segmented DC offset compensation system based on a digital negative feedback scheme;
FIG. 7 is a schematic diagram illustrating an implementation of a DC offset compensation method according to an embodiment of the present invention;
fig. 8 is a schematic diagram of an alternative structure of the dc offset compensation system according to the embodiment of the present invention;
fig. 9 is a schematic diagram of another optional component structure of the dc offset compensation system according to the embodiment of the present invention.
Detailed Description
As can be seen from the background, the dc offset compensation scheme in the related art has a problem of low compensation accuracy when compensating the dc offset of the receiver.
For example, fig. 1 is a schematic structural diagram of a dc offset compensation system based on an ac coupling scheme, and as can be seen from fig. 1, a receiver includes a signal processing path, which includes a mixer, a filter and an intermediate frequency amplifier; a dc blocking capacitor may be added to the signal processing path to compensate for dc loss. However, this solution requires a large number of discrete capacitors and a large volume of capacitors, and therefore it is not practical to integrate these capacitors, resulting in a difficult application of the ac coupling solution in a zero intermediate frequency receiver.
Fig. 2 is a schematic structural diagram of a single-path dc offset compensation system based on a digital negative feedback scheme, and as shown in fig. 2, the scheme is to feed back a dc offset value output by a signal processing path to an input end of a filter in a digital feedback manner, so as to reduce a dc offset value to be compensated. Due to the fact that the overall gain of the signal processing channel is large, the compensation module in the system needs to compensate the direct current offset value very finely, the performance index of the compensation module needs to be very high, and therefore the realization difficulty of the single-path direct current offset compensation system is large.
For example, in a 1000-gain signal processing path, when the dc offset at the input of the signal processing path is 1mv, the dc offset at the output of the signal processing path will reach 1000 mv. If the DC offset of the signal processing path is compensated at the output end, the DC offset value output by the signal processing path is reduced to 10mv, so that the reverse DC value is required to be injected at the output end and is 990 mv; if the DC offset of the signal processing path is compensated at the input end, the DC offset value output by the signal processing path is reduced to 10mv, so that only the reverse DC value of 0.99mv needs to be injected at the input end, and the DC offset value output by the signal processing path can be fed back to the input end of the filter in a digital feedback mode, thereby reducing the DC offset value needing to be compensated.
Further, if the dc offset value output by the signal processing path is to be reduced to 10mv, the dc offset value at the input end of the signal processing path is to be compensated to 0.01mv, which has very strict requirements on performance indexes of the compensation module in the system, and thus the implementation difficulty of the single-path dc offset compensation system is relatively large. Therefore, the single-path direct current offset compensation system needs to make a compromise between the performance index and the compensation precision.
For a single-path dc offset compensation system based on a digital negative feedback scheme, a sectional dc offset compensation system based on a digital negative feedback scheme is proposed in the related art, as shown in fig. 3, the sectional dc offset compensation system includes front and rear compensation modules, and the two compensation modules divide a signal processing path in a receiver into a first sub-processing path and a second sub-processing path. Fig. 4 is a schematic diagram of an implementation of a conventional dc offset compensation method based on a segmented dc offset compensation system, and referring to fig. 3 and 4, in the prior art, the dc offset compensation method based on the segmented dc offset compensation system respectively compensates for only the dc offsets of the first sub-processing path and the signal processing path. However, after the dc offset of the first sub-processing path is compensated, the dc offset output by the first sub-processing path after compensation will also pass through the second sub-processing path, so the dc offset output by the first sub-processing path after compensation will be superimposed on the second sub-processing path, resulting in a larger dc offset compensation range for the signal processing path, and thus the compensation accuracy is limited by the performance of the compensation module in the segmented dc offset compensation system, and the compensation accuracy is not high.
Based on this, the scheme provided in the embodiment of the present invention is used for compensating for dc offset of a signal processing path in a receiver, where the signal processing path includes a first sub-processing path and a second sub-processing path, and an output end of the first sub-processing path is connected to an input end of the second sub-processing path. Firstly, compensating the direct current offset of the second sub-processing path to reduce the direct current offset of the second sub-processing path; then, compensating the direct current offset of the first sub-processing path to reduce the direct current offset of the first sub-processing path; and finally, integrally compensating the direct current offset of the signal processing path to reduce the direct current offset of the signal processing path to a range which does not influence the normal operation of the signal processing path.
Because the DC offset of the second sub-processing path is compensated before the DC offset of the first sub-processing path is superposed on the DC offset of the second sub-processing path; and after compensating the first sub-processing path, also performing overall compensation on the signal processing path. Therefore, by segmenting the signal processing path and compensating the DC offset of the segmented signal processing path in three stages, compared with the prior art, the performance index of the compensation module in the DC offset compensation system can be reduced under the condition that the working state of the signal processing path is constant. Accordingly, under the condition that the performance of the direct current offset compensation system is the same as that of the existing direct current offset compensation system, even under the condition of reducing the performance requirement, the compensation precision of the direct current offset can be improved.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 5 is a schematic view of an implementation flow of a first embodiment of the dc offset compensation method of the present invention, and referring to fig. 5, the dc offset compensation method of the present embodiment includes the following steps:
the dc offset compensation method of this embodiment is applied to a dc offset compensation system, and is used to compensate for dc offset of a signal processing path in a receiver. The dc offset compensation system may include the signal processing path or may not include the signal processing path, and the following description will take the case where the dc offset compensation system includes the signal processing path as an example. The direct current offset compensation system can also comprise a rough compensation module, a fine compensation module and a direct current offset judgment module besides the signal processing path. The signal processing path may comprise a mixer, a filter and an intermediate frequency amplifier, and an output of the mixer is connected to an input of the filter and an output of the filter is connected to an input of the intermediate frequency amplifier.
Here, the coarse compensation module and the fine compensation module are connected in parallel at different positions of the signal processing path and are used for compensating the dc offset of the signal processing path. Generally, depending on the direction of the signal processing path signal, the coarse compensation module may be connected before the fine compensation module; and, according to the position where the coarse compensation module and the fine compensation module are connected in parallel to the signal processing path, the signal processing path may be divided into a first sub-processing path and a second sub-processing path, the portion of the signal processing path between the coarse compensation module and the fine compensation module is the first sub-processing path, and the portion of the signal processing path after the fine compensation module is the second sub-processing path.
Specifically, the coarse compensation module may be connected in parallel to an input end of the mixer, or may be connected in parallel to an input end of the filter; accordingly, the fine compensation module can be connected in parallel to the input end of the filter, and also can be connected in parallel to the input end of the intermediate frequency amplifier. The dc offset determining module is configured to detect a dc offset value output by the signal processing path, so that the dc offset determining module may be connected in series to the output terminal of the signal processing path, or connected in parallel to the output terminal of the mixer or connected in parallel to the output terminal of the filter.
For example, as shown in fig. 3, the coarse compensation module may be connected in parallel to an input terminal of the mixer, the fine compensation module may be connected in parallel to an input terminal of the intermediate frequency amplifier, and the dc offset determination module is connected in series to an output terminal of the intermediate frequency amplifier; in the system, the first sub-processing path includes a mixer and a filter, and the second sub-processing path includes an intermediate frequency amplifier. Fig. 6 is another structural diagram of a segmented dc offset compensation system based on a digital negative feedback scheme, and referring to fig. 6, the coarse compensation module may be connected in parallel to an input terminal of a mixer, the fine compensation module may be connected in parallel to an input terminal of a filter, and the dc offset determination module is connected in series to an output terminal of an if amplifier; in the system, the first sub-processing path includes a mixer and the second sub-processing path includes a filter and an intermediate frequency amplifier.
The frequency mixer can be divided into a passive frequency mixing switch circuit and an active frequency mixing switch circuit according to the active or passive state; depending on the architecture, a single-balanced mixer and a double-balanced mixer can be used. Whichever mixer is used, the conversion from radio frequency signals to intermediate frequency signals is realized; specifically, the mixer shifts the radio frequency voltage signal or the radio frequency current signal to an intermediate frequency under the drive of the local oscillation signal, so as to output the intermediate frequency voltage signal or the intermediate frequency current signal.
The filter can be divided into an active filter circuit and a passive filter circuit according to the active or passive state; according to different modes, the filter can be divided into a current mode filter and a voltage mode filter; the filter can be divided into a filter with fixed gain and a filter with variable gain according to the gain type of the filter. Either filter is used to implement frequency selective filtering of the intermediate frequency signal.
The intermediate frequency amplifier can be divided into an intermediate frequency amplifier in a current mode and an intermediate frequency amplifier in a voltage mode according to different modes; according to different gain types, the intermediate frequency amplifier can be divided into an intermediate frequency amplifier with continuously adjustable gain and an intermediate frequency amplifier with discretely adjustable gain. Whatever the intermediate frequency amplifier, the intermediate frequency amplifier is used for amplifying the intermediate frequency signal.
Of course, the signal processing path may include other modules besides the mixer, the filter and the intermediate frequency amplifier, which will not be described here.
The dc offset compensation method according to the embodiment of the present invention will be described in detail below with reference to fig. 3 or fig. 6.
In an embodiment, the dc offset of the signal processing path may refer to a dc voltage offset, and may also refer to a dc current offset. When the direct current offset of the signal processing path is direct current voltage offset, compensating the direct current offset of the signal processing path in a mode of injecting direct current voltage; correspondingly, when the direct current offset of the signal processing path is the direct current loss adjustment, the direct current offset of the signal processing path is compensated in a direct current injection mode. In the following embodiments, the dc offset of the signal processing path is described in detail by taking a dc offset as an example.
When the fine compensation module compensates for the dc offset of the second sub-processing path, the fine compensation module may be performed on the premise that the first sub-processing path and the coarse compensation module are turned off, or may be performed on the premise that the first sub-processing path and the coarse compensation module are not turned off. In this embodiment, in order to reduce the performance of the dc offset determination module when compensating the dc offset of the signal processing path, the fine compensation module will be described in detail by taking as an example that the dc offset of the second sub-processing path is compensated on the premise that the first sub-processing path and the coarse compensation module are turned off.
In an embodiment, the fine compensation module is used to compensate the dc offset of the second sub-processing path, and the second sub-processing path, the fine compensation module and the dc offset determination module need to be turned on, and the first sub-processing path and the coarse compensation module need to be turned off. Here, each module may be controlled by a switching power supply, so that the module may be turned on when the module is powered on, and turned off when the module is powered off.
In an embodiment, the dc offset determining module may detect a dc offset value output by the signal processing path in real time, and may generate a corresponding control signal according to the detected dc offset value in each stage of dc offset compensation. For example, when the dc offset value detected by the dc offset discrimination module is greater than a preset threshold, a first control signal is generated, where the first control signal represents that the dc offset of the signal processing path or the corresponding sub-processing path in the signal processing path needs to be compensated; and when the direct current offset value detected by the direct current offset judgment module is smaller than or equal to a preset threshold value, generating a second control signal, wherein the second control signal represents that the direct current offset compensation of the signal processing path or the corresponding sub-processing path in the signal processing path is stopped.
In each stage of the dc offset compensation, the dc offset discrimination module may send the generated control signal to the corresponding compensation module; and after receiving the control signal, the corresponding compensation module executes corresponding compensation operation according to the received control signal.
For example, the dc offset determination module may send the generated first control signal to the coarse compensation module, and the coarse compensation module compensates the dc offset of the first sub-processing path after receiving the first control signal; or, the dc offset discrimination module sends the generated second control signal to the coarse compensation module, and the coarse compensation module stops compensating the dc offset of the first sub-processing path after receiving the second control signal. The direct current offset judgment module can also send the generated first control signal to the fine compensation module, and the fine compensation module compensates the direct current offset of the second sub-processing path or the whole signal processing path after receiving the first control signal; or, the dc offset discrimination module sends the generated second control signal to the fine compensation module, and the fine compensation module stops compensating the dc offset of the second sub-processing path or the entire signal processing path after receiving the second control signal.
It should be noted that, the dc offset determining module specifically sends the generated control signal to which compensating module, and needs to first determine which compensating stage is at first.
Specifically, in a first compensation stage, the dc offset discrimination module detects a first constant-current loss adjustment value output by the signal processing path in real time, and determines whether the first constant-current loss adjustment value is less than or equal to a first threshold; and when the first constant current loss adjusting value is larger than the first threshold value, the direct current offset judgment module feeds the generated first control information back to the fine compensation module. And after receiving the first control information, the fine compensation module injects a direct-current voltage opposite to the direct-current offset of the second sub-processing path into the input end of the second sub-processing path to compensate the direct-current offset of the second sub-processing path.
And when the direct current offset judgment module detects that the output first direct current offset value is smaller than or equal to the first threshold value in the process that the fine compensation module injects direct current voltage into the input end of the second sub-processing path, the direct current offset judgment module feeds back the generated second control signal to the fine compensation module. After receiving the second control signal, the fine compensation module does not inject dc voltage into the input end of the second sub-processing path any more, and stores the first dc injected into the input end of the second sub-processing path, so that the fine compensation module can keep the injected first dc unchanged during the compensation process for the dc offset of the first sub-processing path.
For example, the first threshold is 1mv, and when the dc offset discrimination module detects that the first dc offset adjustment value is less than or equal to 1mv, the dc offset discrimination module generates a first control signal and sends the first control signal to the fine compensation module.
The first threshold value can be set according to actual needs, and the specific setting takes the performance of the second sub-processing path as a reference standard without being influenced; that is, a certain dc offset may be allowed to exist in the second sub-processing path as long as the existing dc offset does not affect the performance of the second sub-processing path. Therefore, the normal operation of the receiver can be ensured on the premise of reducing the performance index of the fine compensation module, so that the realization difficulty of the direct current offset compensation system can be reduced, the system scale is reduced, and the power consumption and the area are reduced.
102, compensating the dc offset of the first sub-processing path based on the first dc offset value, so that a second dc offset value output by the signal processing path is less than or equal to a second threshold;
here, the first sub-processing path and the coarse compensation module are turned on, and when the dc amount injected at the input end of the second sub-processing path is the first dc amount, the dc offset of the first sub-processing path is compensated, so that the second dc offset value output by the signal processing path is smaller than or equal to the second threshold value. When the first sub-processing path is in an off state and the dc offset value output by the signal processing path is the first dc offset value, the first dc amount is injected from the input end of the second sub-processing path.
Specifically, in a second compensation stage, on the premise of maintaining the first dc flow, the dc offset determination module detects a second dc offset value output by the signal processing path in real time, and determines whether the second dc offset value is less than or equal to a second threshold; and when the second direct current offset value is larger than the second threshold value, the direct current offset judgment module feeds the generated first control signal back to the rough compensation module. The rough compensation module compensates the DC offset of the first sub-processing path by injecting a DC voltage opposite to the DC offset of the first sub-processing path at an input end of the first sub-processing path.
When the direct current offset judgment module detects that the output second direct current offset value is smaller than or equal to a second threshold value in the process that the rough compensation module injects direct current voltage into the input end of the first sub-processing path, the direct current offset judgment module feeds back the generated second control signal to the rough compensation module. After receiving the second control signal, the rough compensation module does not inject dc voltage into the input end of the first sub-processing path any more, and stores a second dc quantity injected into the input end of the first sub-processing path, so that the rough compensation module can keep the injected second dc quantity unchanged during the compensation process for the dc offset of the signal processing path.
The second threshold value can be set according to actual needs, and the specific setting takes the performance of the first sub-processing path as a reference standard without being influenced; that is, a certain dc offset may be allowed to exist in the first sub-processing path as long as the existing dc offset does not affect the performance of the first sub-processing path. Therefore, the normal operation of the receiver can be ensured on the premise of reducing the performance index of the rough compensation module, so that the realization difficulty of the direct current offset compensation system can be reduced, the system scale is reduced, and the power consumption and the area are reduced.
103, compensating the dc offset of the signal processing path based on the second dc offset value, so that a third dc offset value output by the signal processing path is smaller than or equal to a third threshold; the third threshold is less than the second threshold.
When the input end of the first sub-processing path injects a second dc quantity, the dc offset of the whole signal processing path is compensated, so that the third dc offset value output by the signal processing path is smaller than or equal to a third threshold value. And when the second direct current quantity is the direct current quantity injected by the input end of the first sub-processing path when the direct current loss regulating value output by the signal processing path is the second direct current loss regulating value.
Specifically, in a third compensation stage, the dc offset determination module detects a third dc offset value output by the signal processing path in real time, and determines whether the third dc offset value is less than or equal to a third threshold; and when the third direct current offset value is larger than the third threshold value, the direct current offset judgment module feeds the generated first control information back to the fine compensation module. After the fine compensation module receives the first control information, on the basis of keeping the first direct current, direct current voltage opposite to the direct current offset of the second sub-processing path is injected into the input end of the second sub-processing path, so that the direct current offset of the whole signal processing path is compensated.
And when the direct current offset judgment module detects that the output third direct current offset value is smaller than or equal to a third threshold value in the process of injecting direct current voltage into the input end of the second sub-processing path by the fine compensation module, the direct current offset judgment module feeds back the generated second control signal to the fine compensation module. After receiving the second control signal, the fine compensation module does not inject dc voltage into the input end of the second sub-processing path any more, and stores a third dc amount injected into the input end of the second sub-processing path in the whole compensation stage, so as to ensure subsequent normal operation of the signal processing path in the receiver.
The third threshold value can be set according to actual needs, and the specific setting takes the performance of the whole signal processing path as a reference standard without being influenced; that is, certain dc offsets may be allowed in the signal processing path as long as the existing dc offsets do not affect the performance of the signal processing path.
The following describes an example of the dc offset compensation method according to the embodiment of the present invention in detail with reference to fig. 3 for a segment-based dc offset compensation system.
Fig. 7 is a schematic diagram illustrating an implementation of the dc offset compensation method according to the embodiment of the present invention, and referring to fig. 7, the dc offset compensation method according to the embodiment of the present invention is performed in three stages.
Let the gain of the signal processing path be 1000, wherein the gain of the first sub-processing path is 100, and the gain of the second sub-processing path is 10. Before compensating the DC offset of the signal processing path, the initial DC offset of the output of the signal processing path is adjusted to 1010mv, wherein 1mv of DC offset exists at the input end of the first sub-processing path, and 1mv of DC offset also exists at the input end of the second sub-processing path.
In the first compensation stage, the second sub-processing path, the fine compensation module and the direct current offset judgment module are started, and the rough compensation module and the first sub-processing path are simultaneously turned off; the fine compensation module compensates the direct current offset of the second sub-processing path according to the first control signal generated by the direct current offset judgment module, and feeds the generated second control signal back to the fine compensation module when the direct current offset judgment module detects that the first direct current offset adjustment value output by the signal processing path is smaller than or equal to the first threshold value, so that the fine compensation module stops compensating the direct current offset of the second sub-processing path. Here, the first threshold may be set to 1mv, since the gain of the second sub-processing path is 10; therefore, the dc offset value at the input end of the second sub-processing path is compensated to 0.1mv, and accordingly, the first dc amount injected by the fine compensation module to the input end of the second sub-processing path is 0.9mv, and the compensation range is 0.9 mv. After the first stage compensation is finished, the first sub-processing path and the coarse compensation module are started, and at this time, the dc offset value output by the signal processing path is 1001 mv.
And in a second compensation stage, starting the first sub-processing path and the rough compensation module, keeping the first direct current constant, compensating the direct current offset of the first sub-processing path by the rough compensation module according to a first control signal generated by the direct current offset judgment module, and feeding back a generated second control signal to the rough compensation module when the direct current offset judgment module detects that a second direct current offset value output by the signal processing path is less than or equal to a second threshold value, so that the rough compensation module stops compensating the direct current offset of the first sub-processing path. Here, the second threshold may be 11mv, since the gain of the first sub-processing path is 100, the gain of the second sub-processing path is 10, and the second dc offset value is not completely the dc offset of the first sub-processing path, and the second sub-processing path also overlaps with the dc offset of 1 mv; therefore, the dc offset value at the input terminal of the first sub-processing path is compensated to 0.01mv, and accordingly, the second dc amount injected by the coarse compensation module to the input terminal of the first sub-processing path is 0.99mv, and the compensation range is 0.99 mv.
In a third compensation stage, the second direct current quantity is kept unchanged, the fine compensation module compensates the direct current offset of the whole signal processing channel according to the first control signal generated by the direct current offset judgment module, and when the direct current offset judgment module detects that a third direct current offset value output by the signal processing channel is smaller than or equal to a third threshold value, the generated second control signal is fed back to the fine compensation module, so that the fine compensation module stops compensating the direct current offset of the whole signal processing channel. Here, the third threshold may be set to 10mv, since the gain of the first sub-processing path is 100, the gain of the second sub-processing path is 10; therefore, before the third compensation stage, the dc offset value at the input end of the second sub-processing path is 1.1mv, so that the fine compensation module injects 0.1mv at the input end of the second sub-processing path on the basis of the first dc amount injected to the input end of the second sub-processing path, that is, the third dc offset value output by the signal processing path is less than or equal to the third threshold.
From the above description, it can be seen that, the dc offset value output by the signal processing path is 1010mv, and with the dc offset compensation method according to the embodiment of the present invention, if the dc offset value output by the signal processing path is to be reduced to 10mv, the coarse compensation module only needs to be reduced to 0.01mv, and the compensation range of the fine compensation module is 0.9mv (i.e. at most 0.9mv is injected in the first stage). And by adopting the direct current offset compensation method based on the single-path direct current offset compensation system, if the direct current offset value output by the signal processing path is reduced to 10mv, the compensation module needs to be reduced to 0mv under the same working state of the signal processing path, so that the realization difficulty of the single-path direct current offset compensation system is very high. And by adopting the existing direct current offset compensation method based on the sectional direct current offset compensation system, if the direct current offset value output by the signal processing channel is reduced to 10mv, the rough compensation module needs to be reduced to 0.01mv, and the compensation range of the fine compensation module is 1mv, so that when the existing direct current offset compensation method is used for compensating the direct current offset of the signal processing channel, the required compensation range is larger, and the compensation speed is slower.
Therefore, according to the dc offset compensation method provided in the embodiment of the present invention, before the dc offset of the first sub-processing path is compensated, the dc offset of the second sub-processing path is compensated, so that the compensation range of the compensation module in the dc offset compensation system can be reduced, and the compensation speed is increased. Meanwhile, after the direct current offset of the first sub-processing path is compensated, the direct current offset of the signal processing path is integrally compensated, so that the compensation precision can be higher. In addition, in the direct current offset compensation process of the sub-processing passage, certain direct current offset is allowed to exist on the premise of not influencing the performance of the sub-processing passage, so that the performance index of a compensation module in a direct current compensation system can be reduced, the realization difficulty of the direct current offset compensation system is further reduced, the system scale is reduced, and the power consumption and the area are reduced.
In addition, the gain of the first sub-processing path may be greater than the gain of the second sub-processing path, may also be smaller than the gain of the second sub-processing path, or may be equal to the gain of the second sub-processing path; the relative magnitude of the gain of the first sub-processing path and the gain of the second sub-processing path is not limited in the embodiment of the present invention.
In order to implement the method according to the embodiment of the present invention, an embodiment of the present invention further provides a dc offset compensation system, which is used for implementing the details of the dc offset compensation method to achieve the same effect.
Fig. 8 is a schematic diagram of an optional composition structure of the dc offset compensation system according to the embodiment of the present invention, and referring to fig. 8, the dc offset compensation system according to the embodiment of the present invention includes: a signal processing path 21, said signal processing path 21 comprising a first sub-processing path 211 and a second sub-processing path 212, an output of said first sub-processing path 211 being connected to an input of said second sub-processing path 212; the system further comprises: a first compensation module 22, a second compensation module 23 and a third compensation module 24; wherein the content of the first and second substances,
the first compensation module 22 is configured to compensate for dc offset of the second sub-processing path, so that a first dc offset output by the signal processing path is smaller than or equal to a first threshold;
the second compensation module 23 is configured to compensate for the dc offset of the first sub-processing path based on the first dc offset adjustment value, so that a second dc offset value output by the signal processing path is smaller than or equal to a second threshold;
the third compensation module 24 is configured to compensate the dc offset of the signal processing path based on the second dc offset value, so that a third dc offset value output by the signal processing path is smaller than or equal to a third threshold; the third threshold is less than the second threshold.
Optionally, the dc offset compensation system of this embodiment further includes: a direct current offset discrimination module 25; wherein the content of the first and second substances,
the direct current offset discrimination module 25 is configured to detect whether a first direct current offset value output by the signal processing path is smaller than or equal to a first threshold value in real time; when the first constant loss value is greater than a first threshold, triggering the first compensation module 22;
the dc offset discrimination module 25 is further configured to detect whether a second dc offset value output by the signal processing path is smaller than or equal to a second threshold in real time; when the second dc offset value is greater than a second threshold, triggering the second compensation module 23;
the dc offset determination module 25 is further configured to detect whether a third dc offset value output by the signal processing path is smaller than or equal to a third threshold in real time; and when the third dc offset value is greater than a third threshold, triggering the third compensation module 24.
Optionally, the first compensation module 22 is specifically configured to compensate for dc offset of the second sub-processing path by injecting dc into an input end of the second sub-processing path;
the second compensation module 23 is specifically configured to compensate for dc offset of the first sub-processing path by injecting dc into an input end of the first sub-processing path;
the third compensation module 24 is specifically configured to compensate for dc offset of the signal processing path by injecting dc into the input end of the second sub-processing path.
It should be noted that the first compensation module 22, the second compensation module 23, and the third compensation module 24 are hereinafter referred to as compensation modules, and the compensation modules may be modules combined by some electronic devices for processing analog signals, or modules combined by mixing and superimposing some electronic devices for processing analog signals and some electronic devices for processing digital signals. In this embodiment, the compensation module will briefly explain the implementation method for compensating the dc offset by taking a module formed by mixing, superposing and combining some electronic devices for processing analog signals and some electronic devices for processing digital signals as an example.
Wherein, the compensation module can comprise a digital logic control unit and an analog-to-digital conversion unit. Firstly, the digital logic control unit performs code word control on the analog-digital conversion unit based on the direct current offset discrimination value fed back by the direct current offset discrimination module, so that the analog-digital conversion unit generates corresponding direct current or direct current voltage and injects the direct current or direct current voltage into the signal processing path, and further the direct current offset of the signal processing path is compensated.
Optionally, the second compensation module 23 is further configured to compensate for the dc offset of the first sub-processing path when the dc amount injected by the input end of the second sub-processing path is the first dc amount, so that a second dc offset value output by the signal processing path is smaller than or equal to a second threshold; the first direct current is the direct current injected by the input end of the second sub-processing path when the direct current offset value output by the signal processing path is the first direct current offset value;
the third compensation module 24 is further configured to compensate for the dc offset of the signal processing path when the dc quantity injected at the input end of the first sub-processing path is the second dc quantity, so that a third dc offset value output by the signal processing path is smaller than or equal to a third threshold; and the second direct current quantity is the direct current quantity injected by the input end of the first sub-processing path when the direct current loss regulating value output by the signal processing path is the second direct current loss regulating value.
Optionally, the gain of the first sub-processing path 211 is larger than the gain of the second sub-processing path 212.
In this embodiment, the third compensation module 24 may specifically implement its function by using the first compensation module 22, as shown in fig. 9, which is another optional structural schematic diagram of the dc offset compensation system according to the embodiment of the present invention. Specifically, the first compensation module 22 is configured to compensate for dc offset of the second sub-processing path, so that a first dc offset output by the signal processing path is smaller than or equal to a first threshold; the first compensation module 22 is further configured to compensate the dc offset of the signal processing path based on the second dc offset value, so that a third dc offset value output by the signal processing path is smaller than or equal to a third threshold; the third threshold is less than the second threshold.
In the dc offset compensation system provided in the above embodiment, only the division of the program modules is illustrated when performing dc offset compensation, and in practical applications, the processing distribution may be completed by different program modules according to needs, that is, the internal structure of the apparatus is divided into different program modules to complete all or part of the processing described above. In addition, the dc offset compensation system and the dc offset compensation method provided by the above embodiments belong to the same concept, and specific implementation processes thereof are detailed in the method embodiments and will not be described herein again.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and scope of the present invention are included in the protection scope of the present invention.
Claims (10)
1. A dc offset compensation system, the system comprising: the signal processing path comprises a first sub-processing path and a second sub-processing path, and the output end of the first sub-processing path is connected with the input end of the second sub-processing path; the system further comprises: the device comprises a first compensation module, a second compensation module and a third compensation module; wherein the content of the first and second substances,
the first compensation module is used for compensating the direct current offset of the second sub-processing path so that a first direct current offset value output by the signal processing path is smaller than or equal to a first threshold value;
the second compensation module is configured to compensate for the dc offset of the first sub-processing path based on the first dc offset value, so that a second dc offset value output by the signal processing path is smaller than or equal to a second threshold;
the third compensation module is configured to compensate for the dc offset of the signal processing path based on the second dc offset value, so that a third dc offset value output by the signal processing path is smaller than or equal to a third threshold; the third threshold is less than the second threshold.
2. The system of claim 1, further comprising: a direct current offset discrimination module; wherein the content of the first and second substances,
the direct current offset judgment module is used for detecting whether a first direct current offset value output by the signal processing path is smaller than or equal to a first threshold value or not in real time; when the first constant loss adjusting value is larger than a first threshold value, triggering the first compensation module;
the direct current offset judgment module is also used for detecting whether a second direct current offset value output by the signal processing channel is smaller than or equal to a second threshold value in real time; when the second direct current offset value is larger than a second threshold value, triggering the second compensation module;
the direct current offset judgment module is also used for detecting whether a third direct current offset value output by the signal processing path is smaller than or equal to a third threshold value in real time; and when the third direct current offset value is larger than a third threshold value, triggering the third compensation module.
3. The system according to claim 1, wherein the first compensation module is configured to compensate for dc offsets of the second sub-processing path by injecting dc at an input of the second sub-processing path;
the second compensation module is specifically configured to compensate for dc offset of the first sub-processing path by injecting dc into an input end of the first sub-processing path;
the third compensation module is specifically configured to compensate for dc offset of the signal processing path by injecting dc into the input end of the second sub-processing path.
4. The system according to claim 3, wherein the second compensation module is further configured to compensate the dc offset of the first sub-processing path when the dc amount injected at the input end of the second sub-processing path is the first dc amount, so that the second dc offset value output by the signal processing path is smaller than or equal to a second threshold value; the first direct current is the direct current injected by the input end of the second sub-processing path when the direct current offset value output by the signal processing path is the first direct current offset value;
the third compensation module is further configured to compensate for a dc offset of the signal processing path when the dc quantity injected at the input end of the first sub-processing path is a second dc quantity, so that a third dc offset value output by the signal processing path is smaller than or equal to a third threshold; and the second direct current quantity is the direct current quantity injected by the input end of the first sub-processing path when the direct current loss regulating value output by the signal processing path is the second direct current loss regulating value.
5. The system of claim 1, wherein the gain of the first sub-processing path is greater than the gain of the second sub-processing path.
6. The direct current offset compensation method is applied to a signal processing path comprising a first sub-processing path and a second sub-processing path, wherein an output end of the first sub-processing path is connected with an input end of the second sub-processing path; the method comprises the following steps:
compensating the direct current offset of the second sub-processing path to enable a first direct current offset output by the signal processing path to be smaller than or equal to a first threshold value;
compensating the direct current offset of the first sub-processing path based on the first direct current offset value, so that a second direct current offset value output by the signal processing path is smaller than or equal to a second threshold value;
compensating the direct current offset of the signal processing path based on the second direct current offset value so as to enable a third direct current offset value output by the signal processing path to be smaller than or equal to a third threshold value; the third threshold is less than the second threshold.
7. The method of claim 6, wherein before compensating for the dc offset of the second sub-processing path such that the first dc offset of the signal processing path output is less than or equal to the first threshold, the method further comprises:
detecting whether a first constant loss adjusting value output by the signal processing channel is smaller than or equal to a first threshold value in real time;
when the first dc offset is greater than a first threshold, performing compensation on the dc offset of the second sub-processing path to make the first dc offset output by the signal processing path less than or equal to the first threshold;
before the compensating the dc offset of the first sub-processing path based on the first dc offset value so that a second dc offset value output by the signal processing path is less than or equal to a second threshold value, the method further includes:
detecting whether a second direct current offset value output by the signal processing channel is smaller than or equal to a second threshold value in real time;
when the second dc offset value is greater than a second threshold, performing a step of compensating the dc offset of the first sub-processing path based on the first dc offset value, so that the second dc offset value output by the signal processing path is less than or equal to the second threshold;
before the compensating the dc offset of the signal processing path based on the second dc offset value so that a third dc offset value output by the signal processing path is less than or equal to a third threshold, the method further includes:
detecting whether a third direct current offset value output by the signal processing path is smaller than or equal to a third threshold value in real time;
when the third dc offset value is greater than a third threshold, performing compensation on the dc offset of the signal processing path based on the second dc offset value, so that the third dc offset value output by the signal processing path is less than or equal to the third threshold; and the third threshold is smaller than the second threshold.
8. The method of claim 6, wherein the compensating for DC offsets of the second sub-processing path comprises: compensating the DC offset of a second sub-processing path in a mode of injecting DC into the input end of the second sub-processing path;
the compensating the dc offset of the first sub-processing path includes: compensating for DC offset of the first sub-processing path by injecting DC into an input of the first sub-processing path;
the compensating the dc offset of the signal processing path includes: and compensating the DC offset of the signal processing path by injecting DC into the input end of the second sub-processing path.
9. The method of claim 8, wherein the compensating the dc offset of the first sub-processing path based on the first dc offset value to make a second dc offset value output by the signal processing path less than or equal to a second threshold value comprises:
when the direct current quantity injected into the input end of the second sub-processing path is the first direct current quantity, compensating the direct current offset of the first sub-processing path so as to enable a second direct current offset value output by the signal processing path to be smaller than or equal to a second threshold value; the first direct current is the direct current injected by the input end of the second sub-processing path when the direct current offset value output by the signal processing path is the first direct current offset value;
the compensating, based on the second dc offset value, the dc offset of the signal processing path so that a third dc offset value output by the signal processing path is less than or equal to a third threshold includes:
when the direct current quantity injected into the input end of the first sub-processing path is a second direct current quantity, compensating the direct current offset of the signal processing path so as to enable a third direct current offset value output by the signal processing path to be smaller than or equal to a third threshold value; and the second direct current quantity is the direct current quantity injected by the input end of the first sub-processing path when the direct current loss regulating value output by the signal processing path is the second direct current loss regulating value.
10. The method of claim 6, wherein the gain of the first sub-processing path is greater than the gain of the second sub-processing path.
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| CN102244523A (en) * | 2011-06-23 | 2011-11-16 | 上海中科高等研究院 | Zero intermediate frequency receiver and method for eliminating DC offset of same |
| CN105763491A (en) * | 2016-01-31 | 2016-07-13 | 天津大学 | Direct current imbalance suppression circuit for wireless receiver |
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| CN102244523A (en) * | 2011-06-23 | 2011-11-16 | 上海中科高等研究院 | Zero intermediate frequency receiver and method for eliminating DC offset of same |
| CN105763491A (en) * | 2016-01-31 | 2016-07-13 | 天津大学 | Direct current imbalance suppression circuit for wireless receiver |
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