CN109672445B - R-2R resistor network low-area high-linearity switch array - Google Patents
R-2R resistor network low-area high-linearity switch array Download PDFInfo
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Abstract
An R-2R resistor network low-area high-linearity switch array relates to an integrated circuit. The invention comprises a reference voltage access line, an output line and a GND line, a zero-position switch unit and at least two switch units arranged in a cascading way, wherein in a low-position switch unit group, the high-position cascading point of the switch unit adjacent to the high-position switch unit group is connected with the low-position cascading point of the switch unit adjacent to the high-position side through a cascading switch tube Z. The invention can reduce the layout area and ensure the conversion accuracy.
Description
Technical Field
The invention relates to an integrated circuit, in particular to a 12-bit and higher-precision R-2R type D/A converter circuit.
Background
The R-2R resistor network DAC is a classical design scheme of the current mainstream high-precision D/A converter, and the core units of the DAC are the R-2R resistor network, the output selection switch array, the control logic and the like. The equivalent resistance matching precision of the resistor network and the switch array is a core unit for influencing the conversion linearity performance of the whole DAC.
According to the design rules of the current mainstream wafer manufacturers, for a high-precision pure resistor network, the high-precision matching of the resistors can be realized by reasonably setting the width-to-length ratio of the resistors and performing layout design according to the matching rules, and the natural matching precision of a process plant is generally about 10 bits to 12 bits.
The design difficulty is usually that of switched capacitor arrays for 12-bit precision resistive DACs. In the invention, for convenience of understanding and description, the switch is described by adopting an equivalent resistance model in part of the content, and in order to ensure the high linearity requirement of the R-2R resistor array, a current output type classical R-2R resistor conversion network is shown in figure 1.
In FIG. 1, for arbitrary P M The points each include 3 branches, and the direction of the high weight bit is set as branch I (V REF Direction) for the low weight bit direction is the branch II (switch S 0 Direction), for switch group S M The direction is branch III.
According to the basic theory of analog circuits, the requirements of high linear conversion performance of the R-2R resistor network shown in fig. 1 are as follows:
for any P M At this point, the equivalent resistance of branch II is always equal to the equivalent resistance of branch III.
In the classical current output type resistor network shown in fig. 1, the same group of switches S are used in the normal conversion process M In S M1 And S is M2 While only one switch is on and the other switch must be off.
To ensure optimal conversion linearity performance, S is typically M1 And S is M2 Are NMOS tubes, and have the same size, and when the conduction state is ensured, S M1 Is turned on V of GS1 Voltage is equal to S M2 Is turned on V of GS2 A voltage. And all the switches are in a linear region when in a conducting state, and according to the basic theory of an analog circuit, the equivalent resistance of the NMOS tube in the linear region is as follows:
R on ＝1 / (k*(V GS -V TH )*W/L) (1)
due to S M1 And S is M2 Is of the size and conduction V GS The voltages are uniform, so S M1 And S is M2 The on-resistance of (c) is the same. In the normal conversion process of FIG. 1, a switch set S is provided M Is R M The resistance equivalent model of fig. 1 is shown in fig. 2.
In order to ensure the linear performance of the R-2R resistor network conversion to the maximum extent, all the switch equivalent resistors in FIG. 2 need to satisfy the following relation:
R 0 ＝R N ＝2*R N-1 ＝2 2 *R N-2 ＝···＝2 N-2 *R 02 ＝2 N-1 *R 01 (2)
let S in FIG. 1 M The width-to-length ratio of the switch is (W/L) M As can be seen from formulas (1) and (2), all the switch sizes in fig. 1 need to satisfy the following relationship:
(W/L) 0 ＝(W/L) N ＝ (W/L) N-1 /2＝···＝ (W/L) 02 /2 N-2 ＝ (W/L) 01 /2 N-1 (3)
in summary, for a 12-bit R-2R DAC, the lowest weight bit S is set 12 The width-to-length ratio of W/L, the highest weight bit S 01 The switch size of the switch is 2048 xW/L, and the layout area is too large at the moment, which is unfavorable for layout design. Therefore, for a 12-bit and higher-precision R-2R DAC, the layout area of the classical structure shown in fig. 1 is too large and can not be realized almost, and a switch array scheme is required to be reasonably arranged, so that the conversion linearity performance is ensured to the maximum extent while the layout area is reduced.
Disclosure of Invention
The invention aims to solve the technical problem of providing a switch array capable of reducing layout area and guaranteeing conversion accuracy.
The invention solves the technical problems by adopting a technical scheme that the R-2R resistor network low-area high-linearity switch array comprises a reference low-voltage access line, a reference high-voltage access line, an output line, a GND line, a zero-position switch tube and at least two switch units which are arranged in cascade, wherein each switch unit comprises a first resistor, a second resistor and an MOS tube group, and the MOS tube group consists of two MOS tubes which are connected in parallel; the current output ends of two MOS tubes in the MOS tube group are connected to the parallel connection point, wherein the current input end of one MOS tube is connected with a reference low-voltage access line, and the current input end of the other MOS tube is connected with a reference high-voltage access line; the second resistor is arranged between a parallel connection point in the MOS tube group and the first resistor, the connection point of the first end of the first resistor and the second resistor is a high-order cascade point, the second end of the first resistor is a low-order cascade point, the resistance value of the second resistor is twice that of the first resistor, the switch unit comprises a low-order section switch unit group and a high-order section switch unit group, the number of switch units in the low-order section switch unit group is N, the number of switch units in the high-order section switch unit group is M, the first output end of each switch unit is connected with an output line, and M and N are positive integers;
the method is characterized in that:
in the low-level section switch unit group, the high-level cascade point of the switch unit adjacent to the high-level section switch unit group is connected with the low-level cascade point of the switch unit adjacent to the high-level side through a cascade switch tube Z, and the width-to-length ratio of all switches satisfies the following relation:
(W/L) 0 ＝(W/L) (M+K) /2 N-K k is any integer which is more than or equal to 0 and less than or equal to N;
(W/L) (M-X) /2 M-X ＝(W/L) (M-Y) /2 M-Y x is any integer which satisfies 0.ltoreq.X.ltoreq.N, Y is any integer which satisfies 0.ltoreq.Y.ltoreq.N;
(W/L) Z ＝(W/L) 0 *2 N /(2 N -1)
wherein, (W/L) 0 Representing the width-to-length ratio of the zero-position switching tube (W/L) Z For the width-to-length ratio of the cascade switching tube Z, the other subscripts (W/L) represent the serial numbers of the switching units, the serial numbers sequentially increment from the highest weight bit, and the highest weight bit is 1.
The invention can effectively reduce the number of unit switches in the switch array on the premise of ensuring the conversion linearity performance of the R-2R resistor network to the maximum extent, thereby achieving the best effect of the best circuit performance and the best comprehensive performance of the minimum layout area.
Drawings
FIG. 1 is a diagram of a classical current output R-2R resistor switching network.
FIG. 2 is a diagram of a classical current output type R-2R network equivalent resistance model.
FIG. 3 is a diagram of a classical 12-bit current output R-2R resistor switching network.
Fig. 4 shows a first embodiment: an improved M+N-bit current output type R-2R circuit schematic diagram.
Fig. 5 shows a first embodiment: an improved M+N-bit current output type R-2R equivalent resistance model diagram.
Fig. 6 shows a second embodiment: and an improved M+N-bit current output type R-2R circuit schematic diagram after optimization.
Fig. 7 shows a first embodiment: and (3) an improved M+N-bit current output type R-2R equivalent resistance model diagram after optimization.
Detailed Description
For convenience of description, the following description will take a 12-bit DAC as an example, and the classical current output type R-2R resistor array shown in fig. 1 is shown in fig. 3.
As can be seen from FIG. 3, the lowest weight bit S is set 12 The width-to-length ratio of W/L, the highest weight bit S 01 The switch size of (a) is 2048 x W/L if all S in FIG. 4 01 ～S 12 The switches all adopt the same unit switch, and the width-to-length ratio is increased by only increasing the number of the unit switches, namely S 12 The number of the required unit switches is 2 x 1, S 01 The number of unit switches required is 2 x 2048. The total number of unit switches required by the switch array in fig. 3 is about 2×4096, and the layout area is too large to be realized.
The solution proposed by the present invention is to divide the switch array into two sections m+n, wherein M sections are high weight bits, N ends are low weight bits, and m+n=12. In the scheme, the high M-bit circuit is kept consistent with the circuit shown in fig. 3, but an additional long-term on switch unit is added in the low N bits, so that the application number of the unit switches is reduced to the maximum extent while the R-2R circuit meets the requirement of optimal conversion linearity performance. The principle of the improved M+N bit segment R-2R circuit is shown in figure 4.
As can be seen from comparing fig. 1 and fig. 2, the equivalent resistance model of fig. 4 is shown in fig. 5.
In order to ensure the linear performance of the R-2R resistor network conversion to the maximum extent, all the switch equivalent resistors in FIG. 5 need to satisfy the following relation:
R 0 ＝R 12 ＝ R 11 ＝···＝ R (14-N) ＝ R (13-N) (4)
R 0 ＝2*R 123 ＝··· ＝ 2*R (14-N)3 ＝2* R (13-N)3 (5)
R 0 ＝R M ＝2*R M-1 ＝2 2 *R M-2 ＝···＝2 M-2 *R 02 ＝2 M-1 *R 01 (6)
in fig. 5, if the control switch logic unit is properly set, all switches in fig. 5 have the same V when in the on state GS Voltage, all switches are in linear region when being conducted, S is set M The width-to-length ratio of the switch is (W/L) M As can be seen from formulas (1), (4), (5) and (6), all the switch sizes in fig. 4 need to satisfy the following relationship:
(W/L) 0 ＝ (W/L) 12 ＝ (W/L) 11 ＝···＝ (W/L) (14-N) ＝(W/L) (13-N) (7)
(W/L) 123 ＝ (W/L) 113 ＝···＝ (W/L) (14-N)3 ＝(W/L) (13-N)3 ＝2*(W/L) 0 (8)
(W/L) 0 ＝(W/L) M ＝···＝ (W/L) 02 /2 M-2 ＝ (W/L) 01 /2 M-1 (9)
in the schematic diagram shown in FIG. 4, P is the factor of normal operation (13-N) 、P (14-N) 、···、P 12 The voltage at the point is not exactly equal to GND, and P (13-N) The voltage value is maximum, and the maximum value is (V REFH -V REFL )/2 M . In practical circuits, to simplify the design of digital circuits, the switch S is usually set in the on state (13-N)3 、S (14-N)3 、···、S 123 The gate voltages of (a) are the same. From the formula (1), R 123 ～R (13-N)3 Will have a slight difference in on-resistance value, and R (13-N)3 The resistance that deviates from the ideal value by the maximum.
From the formula (1), R (13-N)3 The maximum offset ratio of (2) is about:
△R (13-N)3 /R (13-N)3 ≈((V REFH -V REFL )/2 M )/(V GS3 -V TH )(10)
in the formula (10), V GS3 Is S (13-N)3 On-state voltage of V TH Is at its threshold level, and S (13-N)3 And in the linear region when on.
In order to ensure that the R-2R resistor network meets the 12-bit conversion precision requirement, only the change range of the unit resistor R in the graph 4 is ensured to be less than or equal to 1/2 12 And (3) obtaining the product. After the parasitic resistance of the switch is increased, as can be seen from fig. 4 and 5, in order to meet the 12-bit conversion accuracy requirement, R+R needs to be ensured (13-N)3 The maximum variation range is less than or equal to 1/2 12 。
In general, in FIG. 4, the resistance of the unit resistor R in the resistor network will be much larger than that of the parasitic switch R 0 If R is greater than or equal to 20 x R 0 Is estimated for V (the actual situation may be much higher than the ratio) REFH ＝2.5V，V REFL When in the conduction state, =0v, V of all switches GS The voltages are all 2.5V, the threshold voltage V TH =0.7v. For a 12-bit current output DAC,
R (13-N)3 the maximum offset ratio of (2) is:
△R (13-N)3 /R (13-N)3 ≈(2.5/2 M )/1.8
R+R (13-N)3 is about
△R (13-N)3 /(R+R (13-N)3 )＝△R (13-N)3 /(41*R (13-N)3 )
△R (13-N)3 /(41*R (13-N)3 )≈(2.5/2 M )/(1.8*41)≤1/2 12
After solving the above formula, under the condition of satisfying 12-bit effective conversion accuracy, M takes the smallest integer, and its smallest value is 8 (M value can be obtained by increasing R and R 0 Is reduced).
In the schematic diagram shown in FIG. 4, P is the result of normal operation (13-N) 、P (14-N) 、···、P 12 The voltages at the points are different, so as to reduce the influence of the parasitic resistance variation to the maximum extent, the voltage can be only P (13-N) The long-term conduction switch is added, and all switches of the high M section and the low N section are independently weighted by binaryIn the form of a schematic diagram as shown in figure 6.
As can be seen from comparing fig. 1 and fig. 2, the equivalent resistance model of fig. 6 is shown in fig. 7.
To ensure the linearity performance of the R-2R resistor network conversion to the maximum extent, all the switch equivalent resistors in fig. 7 need to satisfy the following relationship:
R 0 ＝R 12 ＝2*R 11 ＝···＝2 N-2 *R (14-N) ＝2 N-1 *R (13-N) (11)
R (13-N) /2+R (13-N)3 ＝R M (12)
R M ＝2*R M-1 ＝2 2 *R M-2 ＝···＝2 M-2 *R 02 ＝2 M-1 *R 01 (13)
in fig. 7, if the control switch logic unit is properly set, all switches in fig. 7 have the same V when in the on state GS Voltage, all switches are in linear region when being conducted, S is set M The width-to-length ratio of the switch is (W/L) M As can be seen from formulas (1), (11), (12) and (13), all the switch sizes in fig. 7 need to satisfy the following relationship:
(W/L) 0 ＝ (W/L) 12 /2 0 ＝···＝ (W/L) (14-N) /2 N-2 ＝(W/L) (13-N) /2 N-1 (14)
(W/L) M ＝···＝ (W/L) 02 /2 M-2 ＝ (W/L) 01 /2 M-1 (15)
1/(2*(W/L) (13-N) )+ 1/(W/L) (13-N)3 ＝1/(W/L) M (16)
to minimize layout area, a switch S is typically provided 0 And S is M Is of the same size, i.e. (W/L) 0 ＝(W/L) M 。
The equivalent formula of formula (16) is as follows:
(W/L) (13-N)3 ＝(W/L) 0 *2 N /(2 N -1) (17)
in order to ensure that the R-2R resistor network meets the 12-bit conversion precision requirement, only the change range of the unit resistor R in the graph 6 is ensured to be less than or equal to 1/2 12 And (3) obtaining the product. After increasing the parasitic resistance of the switch, the circuit external conditions in FIG. 6 are kept consistent with those in FIG. 4, the deducing principle in FIG. 6 is consistent with that in FIG. 4, and the minimum value of M is 8 after finishing rounding (M can be increased by increasing R and R 0 Is reduced).
In summary, in the present invention, through the two m+n resistor switch segmentation schemes of fig. 4 and 6, the number of unit switches in the capacitor array can be increased from 2×2 on the premise of maximally ensuring the conversion linearity performance of the current output type R-2R resistor network 12 Effectively reduced to 2 x 2 M The number is about, so that the requirements of the optimal performance of the circuit and the minimum area of the layout are simultaneously considered.
In the invention, a 12-bit DAC is taken as an example as part of the content, and the content can be extended to a DAC with higher precision of 12 bits and more; part of the content is R is more than or equal to 20 x R 0 Is estimated at a minimum of 8. If the unit resistance R and the parasitic switch R in the resistance network are further improved 0 The minimum requirement for the M value can be further reduced.
Claims (1)
- The R-2R resistor network low-area high-linearity switch array comprises a reference low-voltage access line, a reference high-voltage access line, an output line, a GND line, a zero-position switch tube and at least two switch units which are arranged in a cascading manner, wherein each switch unit comprises a first resistor, a second resistor and an MOS tube group, and the MOS tube group consists of two MOS tubes which are connected in parallel; the current output ends of two MOS tubes in the MOS tube group are connected to the parallel connection point, wherein the current input end of one MOS tube is connected with a reference low-voltage access line, and the current input end of the other MOS tube is connected with a reference high-voltage access line; the second resistor is arranged between a parallel connection point in the MOS tube group and the first resistor, the connection point of the first end of the first resistor and the second resistor is a high-order cascade point, the second end of the first resistor is a low-order cascade point, the resistance value of the second resistor is twice that of the first resistor, the switch unit comprises a low-order section switch unit group and a high-order section switch unit group, the number of switch units in the low-order section switch unit group is N, the number of switch units in the high-order section switch unit group is M, the first output end of each switch unit is connected with an output line, and M and N are positive integers;the method is characterized in that:in the low-level section switch unit group, the high-level cascade point of the switch unit adjacent to the high-level section switch unit group is connected with the low-level cascade point of the switch unit adjacent to the high-level side through a cascade switch tube Z, and the width-to-length ratio of all switches satisfies the following relation:(W/L) 0 ＝(W/L) (M+K) /2 N-K k is any integer which is more than or equal to 0 and less than or equal to N;(W/L) (M-X) /2 M-X ＝(W/L) (M-Y) /2 M-Y x is any integer which satisfies 0.ltoreq.X.ltoreq.N, Y is any integer which satisfies 0.ltoreq.Y.ltoreq.N;(W/L) Z ＝(W/L) 0 *2 N /(2 N -1)；wherein, (W/L) 0 Representing the width-to-length ratio of the zero-position switching tube (W/L) Z For the width-to-length ratio of the cascade switching tube Z, the other subscripts (W/L) represent the serial numbers of the switching units, the serial numbers sequentially increment from the highest weight bit, and the highest weight bit is 1.
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