CN109660477B - FPGA-based dual-transmission and dual-reception baseband algorithm modulation and demodulation system - Google Patents
FPGA-based dual-transmission and dual-reception baseband algorithm modulation and demodulation system Download PDFInfo
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- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
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- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
- H04B7/0837—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station using pre-detection combining
- H04B7/0842—Weighted combining
- H04B7/0848—Joint weighting
- H04B7/0854—Joint weighting using error minimizing algorithms, e.g. minimum mean squared error [MMSE], "cross-correlation" or matrix inversion
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- H04B7/00—Radio transmission systems, i.e. using radiation field
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- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
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- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
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- H04L27/266—Fine or fractional frequency offset determination and synchronisation
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- H—ELECTRICITY
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- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0024—Carrier regulation at the receiver end
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Abstract
The invention discloses a FPGA-based dual-transmission and dual-reception baseband algorithm modulation and demodulation system, which comprises an MAC module, a baseband capture module, a baseband receiving module and a baseband transmitting module, wherein the FPGA-based dual-transmission and dual-reception baseband algorithm modulation and demodulation system adopts dual-antenna diversity transmission and then dual-antenna diversity reception at a receiving end, namely, signals carrying the same message and having small correlation are received on two receiving branches, and then the two branch signals are combined and output through a combining technology, so that the probability of deep fading is greatly reduced at a receiving terminal to obtain diversity gain, and the receiving sensitivity is greatly improved.
Description
Technical Field
The invention relates to the technical field of mobile communication, in particular to a dual-transmitting and dual-receiving baseband algorithm modulation and demodulation system based on an FPGA (field programmable gate array).
Background
At present, digital modulation refers to a technique of controlling a parameter in a sinusoidal carrier by using 0 and 1 of a digital baseband signal, and then transmitting and processing all information through some devices. In mobile communications, fading effects are one of the main factors affecting the quality of communications. The fast fading depth can reach 30-40 dB. If the deep fading is to be overcome by increasing the transmission power, increasing the size and height of the antenna, etc., the method is not easy to be realized in many application scenarios and causes interference to other stations.
An effective solution to the problems in the related art has not been proposed yet.
Disclosure of Invention
Aiming at the technical problems in the related art, the invention provides a FPGA-based dual-transmission and dual-reception baseband algorithm modulation and demodulation system.
The technical scheme of the invention is realized as follows:
the FPGA-based dual-transmission and dual-reception baseband algorithm modulation and demodulation system comprises an MAC module and a modem module
The baseband capturing module is connected with the MAC module and the external double antennas and is used for receiving two paths of input I/Q signals carrying the same message in a diversity mode through the double antennas and filtering and performing offset frequency correction on one path of input I/Q signals;
the baseband receiving module is respectively connected with the baseband capturing module and the MAC module and is used for receiving the signal output by the baseband capturing module and demodulating the signal;
wherein: the MAC module is used for receiving the receiving data output by the baseband receiving module and the capture indication output by the baseband capture module, and analyzing and processing the receiving data and the capture indication to output MAC data and MAC signaling;
and the baseband sending module is connected with the MAC module and used for receiving the MAC data and the MAC signaling, and performing coding scrambling and composite output on the received data.
Further, the baseband capture module includes:
the data multiplexing module is connected with the two external receiving antennas and is used for carrying out time division multiplexing on the two I/Q signals and multiplexing the two I/Q signals into a path of serial data;
the shaping matched filter is connected with the data multiplexing module and is used for carrying out shaping matched filtering on the signal output by the data multiplexing module; dividing the signal after the forming matching filtering into two paths, and transmitting one path to the baseband receiving module;
the digital AGC is connected with the forming matched filter and used for receiving the other path of output signal of the forming matched filter and gaining the signal;
a secondary multiplexing module: the digital AGC is connected and used for receiving the signals after the gain output by the digital AGC and changing the multiplexing sequence of the signals;
a leading matched filter: the secondary multiplexing module is connected with the signal processing module and is used for carrying out differential matched filtering on the leader sequence of each burst in the signal output by the secondary multiplexing module;
a first stage capture module: the device is connected with the preamble matched filter and used for receiving the filtered signal output by the preamble matched filter and carrying out first-stage capture judgment according to the result of the preamble matched filter;
a first frequency offset estimation module: the frequency offset estimation module is connected with the first-stage acquisition module and used for receiving the signal output by the first-stage acquisition module and performing frequency offset estimation according to the maximum path acquired for the first time in the signal;
a second frequency offset estimation module: the second frequency offset estimation module is connected with the first frequency offset estimation module and the second multiplexing module respectively and used for carrying out frequency offset correction on the signal input by the second multiplexing module according to the result of the first frequency offset estimation and carrying out second frequency offset estimation on the preamble symbol;
a second stage capture module: the second frequency offset estimation module and the second multiplexing module are respectively connected and used for carrying out frequency offset correction on the signal input by the second multiplexing module according to the result of the second frequency offset estimation, carrying out second-stage capture on the joint detection of the preamble symbol and the first pilot frequency block, and carrying out third frequency offset estimation when the capture is successful; and according to the result of the third frequency offset estimation, carrying out frequency offset correction on the signal input by the secondary multiplexing module, generating a capture instruction and transmitting the capture instruction to the MAC module.
Further, the baseband receiving module includes:
the data delay module is used for receiving the signals transmitted by the baseband capture module, and recombining and outputting the signal pilot frequency block and the data block after different delays according to the signal processing time sequence relation diagram;
the offset frequency correction module is connected with the data delay module and is used for performing pilot frequency offset correction on a pilot frequency block in the recombined signal output by the data delay module and performing data frequency offset correction on a data block in the recombined signal output by the data delay module;
the channel estimation module is connected with the offset frequency correction module and is used for carrying out channel estimation on the pilot signal or the preamble signal corrected by the offset frequency correction module;
the RAKE merging module is respectively connected with the offset frequency correction module and the channel estimation module and is used for receiving the data signals corrected by the offset frequency correction module and the channel estimation result output by the channel estimation module; and according to the channel estimation result, carrying out multipath combination and receiving antenna combination on the received signals;
a TFCI descrambling module connected with the RAKE merging module and used for descrambling TFCI receiving signals of the two transmitting antennas respectively and performing transmitting antenna merging on the descrambled signals;
the TFCI decoding module is connected with the TFCI descrambling module and is used for decoding RM codes of output signals of the TFCI descrambling module;
the data descrambling module is connected with the RAKE combination module and is used for descrambling the data block receiving signals of the two transmitting antennas respectively;
and the de-spreading and interleaving module is connected with the data descrambling module and used for obtaining a spreading ratio according to the decoding result of the TFCI and de-spreading and interleaving the data descrambled by the data descrambling module:
the de-STBC module is connected with the de-spread spectrum interleaving module and is used for STBC combination of the signals of the two transmitting antennas processed by the de-spread spectrum interleaving module;
the Turbo decoding module is connected with the STBC decoding module and is used for carrying out channel decoding on the signal output after the STBC decoding module processes;
the first CRC check module is connected with the Turbo decoding module and used for judging whether the Turbo decoding result is checked correctly; and when the verification is correct, transmitting the Turbo decoded signal to the MAC module.
Further, the baseband transmission module includes:
the second CRC check module is used for receiving the MAC data transmitted by the MAC module, adding CRC check, serial input and serial output to the MAC data, and performing exclusive OR 0xFFFF on check bits output by a standard CRC check result to avoid generating check bits of all 0 by all 0 input;
turbo encoder: the second CRC check module is connected with the first CRC check module and is used for carrying out Turbo code coding on the bit stream added with the CRC by the first CRC check module and carrying out rate matching on 1/3-efficiency coded output;
the STBC coding module: the Turbo encoder is connected with the encoder and is used for performing STBC coding on the bit stream coded by the Turbo encoder;
a spread spectrum interleaving module: the STBC coding module is connected with the antenna array and used for respectively carrying out spread spectrum interleaving on the two antenna data which are subjected to the STBC coding by the STBC coding module;
a data domain scrambling module: the spread spectrum interleaving module is connected with the base station and is used for scrambling the sequence spread by the spread spectrum interleaving module; scrambling the data of the two antennas by the same scrambling code;
a TFCI encoding module: the system comprises a MAC module, a TFCI control word module and a TFCI control word module, wherein the MAC module is used for transmitting a MAC signaling to the TFCI control word module;
TFCI scrambling module: the TFCI encoding module is connected with the TFCI encoding module and is used for scrambling a TFCI encoding result of the TFCI encoding module;
a pilot frequency generation module: pilot signals for generating two antennas;
a preamble generation module: used for producing the leading signal of two aerials;
physical channel multiplexing module: the device is respectively connected with the data field scrambling module, the TFCI coding module, the pilot frequency generating module and the preamble generating module; the device is used for respectively receiving signals output by the data domain scrambling module, the TFCI encoding module, the pilot frequency generating module and the preamble generating module, and multiplexing the received preamble symbols, the TFCI symbols, the pilot frequency symbols and the data block symbols according to a frame structure to obtain chip signals;
forming a filtering module: and the physical channel multiplexing module is connected with the physical channel multiplexing module and is used for carrying out root raised cosine on the multiplexed chip signal to obtain a baseband output signal with 2 times of sampling rate and finally outputting the baseband output signal through two antennas.
Further, the device also comprises a baseband timing module, wherein the baseband timing module is respectively connected with the baseband capture module, the baseband receiving module and the baseband sending module through the MAC module.
Further, the forming matched filter is a root raised cosine filter matched with the originating forming filter.
The invention has the beneficial effects that: the FPGA-based dual-transmitting and dual-receiving baseband algorithm modulation and demodulation system adopts dual-antenna diversity transmission, and then dual-antenna diversity reception is carried out at a receiving end, namely, signals carrying the same message with small correlation are received on two receiving branches, and then the signals of the two branches are combined and output through a combination technology, so that the probability of deep fading is greatly reduced at the receiving terminal, diversity gain is obtained, and the receiving sensitivity is greatly improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a block diagram of a FPGA-based dual-transmission and dual-reception baseband algorithm modem system according to the present invention;
FIG. 2 is a block diagram of a baseband capture module in the FPGA-based dual-transmission and dual-reception baseband algorithm modem system according to the present invention;
FIG. 3 is a block diagram of a baseband capture module in the FPGA-based dual-transmission and dual-reception baseband algorithm modem system according to the present invention;
fig. 4 is a block diagram of a baseband transmission module in the FPGA-based dual transmission and dual reception baseband algorithm modem system according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.
As shown in fig. 1 to 4, the FPGA-based dual-transmission and dual-reception baseband algorithm modem system according to the embodiment of the present invention includes a MAC module 1, and further includes
The baseband capturing module 2 is connected with the MAC module 1 and an external double antenna and is used for receiving two paths of input I/Q signals carrying the same message in a diversity mode through the double antenna and carrying out filtering and offset frequency correction processing on one path of input I/Q signals;
the baseband receiving module 3 is respectively connected with the baseband capturing module 2 and the MAC module 1, and is configured to receive the signal output by the baseband capturing module 2 and demodulate the signal;
wherein: the MAC module 1 is used for receiving the received data output by the baseband receiving module 3 and the capture indication output by the baseband capture module 2, and analyzing and processing the received data and the capture indication to output MAC data and MAC signaling;
and the baseband sending module 4 is connected with the MAC module 1 and used for receiving the MAC data and the MAC signaling, and performing coding scrambling and composite output on the received data.
In this embodiment, the mobile terminal further includes a baseband timing module 5, and the baseband timing module 5 is connected to the baseband capture module 2, the baseband receiving module 3, and the baseband sending module 4 through the MAC module 1; clocks of the baseband capture module 2, the baseband receiving module 3 and the baseband sending module 4 are derived from the same system master clock, and as shown in fig. 1, the clocks of the three modules can be turned off by respective power down signals to reduce power consumption; with a common timing reference provided by the system master clock.
In this embodiment, the baseband capture module 2 includes:
the data multiplexing module is connected with the two external receiving antennas and is used for carrying out time division multiplexing on the two I/Q signals and multiplexing the two I/Q signals into a path of serial data;
the shaping matched filter is connected with the data multiplexing module and is used for carrying out shaping matched filtering on the signal output by the data multiplexing module; dividing the signal after the forming matching filtering into two paths, and transmitting one path to the baseband receiving module 3;
the digital AGC is connected with the forming matched filter and used for receiving the other path of output signal of the forming matched filter and gaining the signal;
a secondary multiplexing module: the digital AGC is connected and used for receiving the signals after the gain output by the digital AGC and changing the multiplexing sequence of the signals;
a leading matched filter: the secondary multiplexing module is connected with the signal processing module and is used for carrying out differential matched filtering on the leader sequence of each burst in the signal output by the secondary multiplexing module;
a first stage capture module: the device is connected with the preamble matched filter and used for receiving the filtered signal output by the preamble matched filter and carrying out first-stage capture judgment according to the result of the preamble matched filter;
a first frequency offset estimation module: the frequency offset estimation module is connected with the first-stage acquisition module and used for receiving the signal output by the first-stage acquisition module and performing frequency offset estimation according to the maximum path acquired for the first time in the signal;
a second frequency offset estimation module: the second frequency offset estimation module is connected with the first frequency offset estimation module and the second multiplexing module respectively and used for carrying out frequency offset correction on the signal input by the second multiplexing module according to the result of the first frequency offset estimation and carrying out second frequency offset estimation on the preamble symbol;
a second stage capture module: the second frequency offset estimation module and the second multiplexing module are respectively connected and used for carrying out frequency offset correction on the signal input by the second multiplexing module according to the result of the second frequency offset estimation, carrying out second-stage capture on the joint detection of the preamble symbol and the first pilot frequency block, and carrying out third frequency offset estimation when the capture is successful; and according to the result of the third frequency offset estimation, the frequency offset correction is carried out on the signal input by the secondary multiplexing module, and a capture instruction is generated and transmitted to the MAC module 1.
In this embodiment, the baseband receiving module 3 includes:
the data delay module is used for receiving the signal transmitted by the baseband capture module 2, and recombining and outputting the signal pilot frequency block and the data block after different delays according to the signal processing time sequence relation diagram; the aim is to reduce TFCI decoding delay;
the offset frequency correction module is connected with the data delay module and is used for performing pilot frequency offset correction on a pilot frequency block in the recombined signal output by the data delay module and performing data frequency offset correction on a data block in the recombined signal output by the data delay module;
the channel estimation module is connected with the offset frequency correction module and is used for carrying out channel estimation on the pilot signal or the preamble signal corrected by the offset frequency correction module; wherein, the channel estimation of the TFCI block and the channel estimation of the data block are shared;
the RAKE merging module is respectively connected with the offset frequency correction module and the channel estimation module and is used for receiving the data signals corrected by the offset frequency correction module and the channel estimation result output by the channel estimation module; and according to the channel estimation result, carrying out multipath combination and receiving antenna combination on the received signals; wherein, the channel estimation of the TFCI block and the RAKE combination of the data block are shared; the signals merged by the RAKE merging module are divided into two paths, and the TFCI and the data block are respectively processed;
a TFCI descrambling module connected with the RAKE merging module and used for descrambling TFCI receiving signals of the two transmitting antennas respectively and performing transmitting antenna merging on the descrambled signals;
the TFCI decoding module is connected with the TFCI descrambling module and is used for decoding RM codes of output signals of the TFCI descrambling module;
the data descrambling module is connected with the RAKE combination module and is used for descrambling the data block receiving signals of the two transmitting antennas respectively;
and the de-spreading and interleaving module is connected with the data descrambling module and used for obtaining a spreading ratio according to the decoding result of the TFCI and de-spreading and interleaving the data descrambled by the data descrambling module:
the de-STBC module is connected with the de-spread spectrum interleaving module and is used for STBC combination of the signals of the two transmitting antennas processed by the de-spread spectrum interleaving module;
the Turbo decoding module is connected with the STBC decoding module and is used for carrying out channel decoding on the signal output after the STBC decoding module processes;
the first CRC check module is connected with the Turbo decoding module and used for judging whether the Turbo decoding result is checked correctly; and when the verification is correct, transmitting the Turbo decoded signal to the MAC module 1.
In this embodiment, the baseband transmission module 4 includes:
the second CRC check module is used for receiving the MAC data transmitted by the MAC module 1, adding CRC check, serial input and serial output to the MAC data, and performing exclusive OR 0xFFFF on check bits output by a standard CRC check result to avoid generating check bits of all 0 by all 0 input;
turbo encoder: the second CRC check module is connected with the first CRC check module and is used for carrying out Turbo code coding on the bit stream added with the CRC by the first CRC check module and carrying out rate matching on 1/3-efficiency coded output;
the STBC coding module: the Turbo encoder is connected with the encoder and is used for performing STBC coding on the bit stream coded by the Turbo encoder;
a spread spectrum interleaving module: the STBC coding module is connected with the antenna array and used for respectively carrying out spread spectrum interleaving on the two antenna data which are subjected to the STBC coding by the STBC coding module;
a data domain scrambling module: the spread spectrum interleaving module is connected with the base station and is used for scrambling the sequence spread by the spread spectrum interleaving module; scrambling the data of the two antennas by the same scrambling code;
a TFCI encoding module: the system is used for receiving the MAC signaling transmitted by the MAC module 1 and carrying out RM coding on the TFCI control word according to the MAC signaling;
TFCI scrambling module: the TFCI encoding module is connected with the TFCI encoding module and is used for scrambling a TFCI encoding result of the TFCI encoding module;
a pilot frequency generation module: pilot signals for generating two antennas;
a preamble generation module: used for producing the leading signal of two aerials;
physical channel multiplexing module: the device is respectively connected with the data field scrambling module, the TFCI coding module, the pilot frequency generating module and the preamble generating module; the device is used for respectively receiving signals output by the data domain scrambling module, the TFCI encoding module, the pilot frequency generating module and the preamble generating module, and multiplexing the received preamble symbols, the TFCI symbols, the pilot frequency symbols and the data block symbols according to a frame structure to obtain chip signals;
forming a filtering module: and the physical channel multiplexing module is connected with the physical channel multiplexing module and is used for carrying out root raised cosine on the multiplexed chip signal to obtain a baseband output signal with 2 times of sampling rate and finally outputting the baseband output signal through two antennas.
In this embodiment, the forming matched filter is a root-raised cosine filter matched with the originating forming filter.
Therefore, by means of the technical scheme of the invention, the FPGA-based dual-transmission and dual-reception baseband algorithm modulation and demodulation system adopts dual-antenna diversity transmission, then receives dual-antenna diversity reception at a receiving end, namely receives signals carrying the same message with small correlation on two receiving branches, and then combines and outputs two branch signals through a combination technology, thereby greatly reducing the probability of deep fading at a receiving terminal to obtain diversity gain, and greatly improving the receiving sensitivity.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (5)
1. The FPGA-based dual-transmission and dual-reception baseband algorithm modulation and demodulation system comprises an MAC module (1), and is characterized by further comprising:
the baseband capturing module (2) is connected with the MAC module (1) and the external double antennas and is used for receiving two paths of input I/Q signals carrying the same message from the double antennas in a diversity mode and carrying out filtering and offset frequency correction processing on one path of input I/Q signals;
the baseband receiving module (3) is respectively connected with the baseband capturing module (2) and the MAC module (1) and is used for receiving the signal output by the baseband capturing module (2) and demodulating the signal;
wherein: the MAC module (1) is used for receiving the received data output by the baseband receiving module (3) and the capture indication output by the baseband capture module (2), and analyzing and processing the received data and the capture indication to output MAC data and MAC signaling;
the baseband sending module (4) is connected with the MAC module (1) and is used for receiving the MAC data and the MAC signaling, and performing coding scrambling and composite output on the received data;
the baseband acquisition module (2) comprises:
the data multiplexing module is connected with the two external receiving antennas and is used for carrying out time division multiplexing on the two I/Q signals and multiplexing the two I/Q signals into a path of serial data;
the shaping matched filter is connected with the data multiplexing module and is used for carrying out shaping matched filtering on the signal output by the data multiplexing module; dividing the signal after the molding matching filtering into two paths, and transmitting one path to the baseband receiving module (3);
the digital AGC is connected with the forming matched filter and used for receiving the other path of output signal of the forming matched filter and gaining the signal;
a secondary multiplexing module: the digital AGC is connected and used for receiving the signals after the gain output by the digital AGC and changing the multiplexing sequence of the signals;
a leading matched filter: the secondary multiplexing module is connected with the signal processing module and is used for carrying out differential matched filtering on the leader sequence of each burst in the signal output by the secondary multiplexing module;
a first stage capture module: the device is connected with the preamble matched filter and used for receiving the filtered signal output by the preamble matched filter and carrying out first-stage capture judgment according to the result of the preamble matched filter;
a first frequency offset estimation module: the frequency offset estimation module is connected with the first-stage acquisition module and used for receiving the signal output by the first-stage acquisition module and performing frequency offset estimation according to the maximum path acquired for the first time in the signal;
a second frequency offset estimation module: the second frequency offset estimation module is connected with the first frequency offset estimation module and the second multiplexing module respectively and used for carrying out frequency offset correction on the signal input by the second multiplexing module according to the result of the first frequency offset estimation and carrying out second frequency offset estimation on the preamble symbol;
a second stage capture module: the second frequency offset estimation module and the second multiplexing module are respectively connected and used for carrying out frequency offset correction on the signal input by the second multiplexing module according to the result of the second frequency offset estimation, carrying out second-stage capture on the joint detection of the preamble symbol and the first pilot frequency block, and carrying out third frequency offset estimation when the capture is successful; and according to the result of the third frequency offset estimation, the frequency offset correction is carried out on the signal input by the secondary multiplexing module, and a capture instruction is generated and transmitted to the MAC module (1).
2. The FPGA-based dual-transmission and dual-reception baseband algorithm modem system according to claim 1, wherein the baseband receiving module (3) comprises:
the data delay module is used for receiving the signals transmitted by the baseband capture module (2), and recombining and outputting the signal pilot frequency block and the data block after different delays according to the signal processing time sequence relation diagram;
the offset frequency correction module is connected with the data delay module and is used for performing pilot frequency offset correction on a pilot frequency block in the recombined signal output by the data delay module and performing data frequency offset correction on a data block in the recombined signal output by the data delay module;
the channel estimation module is connected with the offset frequency correction module and is used for carrying out channel estimation on the pilot signal or the preamble signal corrected by the offset frequency correction module;
the RAKE merging module is respectively connected with the offset frequency correction module and the channel estimation module and is used for receiving the data signals corrected by the offset frequency correction module and the channel estimation result output by the channel estimation module; and according to the channel estimation result, carrying out multipath combination and receiving antenna combination on the received signals;
a TFCI descrambling module connected with the RAKE merging module and used for descrambling TFCI receiving signals of the two transmitting antennas respectively and performing transmitting antenna merging on the descrambled signals;
the TFCI decoding module is connected with the TFCI descrambling module and is used for decoding RM codes of output signals of the TFCI descrambling module;
the data descrambling module is connected with the RAKE combination module and is used for descrambling the data block receiving signals of the two transmitting antennas respectively;
and the de-spreading and interleaving module is connected with the data descrambling module and used for obtaining a spreading ratio according to the decoding result of the TFCI and de-spreading and interleaving the data descrambled by the data descrambling module:
the de-STBC module is connected with the de-spread spectrum interleaving module and is used for STBC combination of the signals of the two transmitting antennas processed by the de-spread spectrum interleaving module;
the Turbo decoding module is connected with the STBC decoding module and is used for carrying out channel decoding on the signal output after the STBC decoding module processes;
the first CRC check module is connected with the Turbo decoding module and used for judging whether the Turbo decoding result is checked correctly; and when the verification is correct, the Turbo decoded signal is transmitted to the MAC module (1).
3. The FPGA-based dual-transmission and dual-reception baseband algorithm modem system according to claim 1, wherein the baseband transmission module (4) comprises:
the second CRC check module is used for receiving the MAC data transmitted by the MAC module (1), adding CRC check, serial input and serial output to the MAC data, and performing exclusive OR (0 xFFFF) on check bits output by a standard CRC check result to avoid generating check bits of all 0 by all 0 input;
turbo encoder: the second CRC check module is connected with the first CRC check module and is used for carrying out Turbo code coding on the bit stream added with the CRC by the first CRC check module and carrying out rate matching on 1/3-efficiency coded output;
the STBC coding module: the Turbo encoder is connected with the encoder and is used for performing STBC coding on the bit stream coded by the Turbo encoder;
a spread spectrum interleaving module: the STBC coding module is connected with the antenna array and used for respectively carrying out spread spectrum interleaving on the two antenna data which are subjected to the STBC coding by the STBC coding module;
a data domain scrambling module: the spread spectrum interleaving module is connected with the base station and is used for scrambling the sequence spread by the spread spectrum interleaving module; scrambling the data of the two antennas by the same scrambling code;
a TFCI encoding module: the system is used for receiving the MAC signaling transmitted by the MAC module (1) and carrying out RM coding on the TFCI control word according to the MAC signaling;
TFCI scrambling module: the TFCI encoding module is connected with the TFCI encoding module and is used for scrambling a TFCI encoding result of the TFCI encoding module;
a pilot frequency generation module: pilot signals for generating two antennas;
a preamble generation module: used for producing the leading signal of two aerials;
physical channel multiplexing module: the device is respectively connected with the data field scrambling module, the TFCI coding module, the pilot frequency generating module and the preamble generating module; the device is used for respectively receiving signals output by the data domain scrambling module, the TFCI encoding module, the pilot frequency generating module and the preamble generating module, and multiplexing the received preamble symbols, the TFCI symbols, the pilot frequency symbols and the data block symbols according to a frame structure to obtain chip signals;
forming a filtering module: and the physical channel multiplexing module is connected with the physical channel multiplexing module and is used for carrying out root raised cosine on the multiplexed chip signal to obtain a baseband output signal with 2 times of sampling rate and finally outputting the baseband output signal through two antennas.
4. The FPGA-based dual-transmission and dual-reception baseband algorithm modem system according to claim 1, further comprising a baseband timing module (5), wherein the baseband timing module (5) is respectively connected to the baseband capture module (2), the baseband receiving module (3) and the baseband transmitting module (4) through the MAC module (1).
5. The FPGA-based dual-transmission and dual-reception baseband algorithm modem system of claim 1, wherein the shaping matched filter is a root-raised cosine filter matched with the transmit-end shaping filter.
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