CN109658868B - Adder unit and display device - Google Patents
Adder unit and display device Download PDFInfo
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- CN109658868B CN109658868B CN201910070697.2A CN201910070697A CN109658868B CN 109658868 B CN109658868 B CN 109658868B CN 201910070697 A CN201910070697 A CN 201910070697A CN 109658868 B CN109658868 B CN 109658868B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
- G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
Abstract
The application provides a display source electrode driving circuit, which comprises an adder unit addition module, a first sampling module and a second sampling module, wherein the adder unit addition module is configured to sample a plurality of input signals in a first time period under the influence of a clock signal; a hold module configured to provide a hold signal for a first period of time under the influence of the clock signal; and a driving module configured to generate a first output signal based on the hold signal in the first period of time and generate a second output signal based on a superimposed signal of the plurality of input signals in a second period of time; wherein the plurality of input signals include at least a data signal and a compensation signal, and the first period and the second period are adjacent periods in the clock signal. By adopting the source electrode driving circuit of the adder unit, input signals can be superposed on an analog domain, and display precision is effectively improved.
Description
Technical Field
The present application relates to the field of information display, and more particularly to a circuit for display driving of an active matrix organic light emitting diode with compensation.
Background
An Active Matrix Organic Light Emitting Diode (AMOLED) emits Light by current driving generated when a thin film field effect transistor is in a saturated state. In the panel production process, the mobility of the thin film transistor may fluctuate greatly due to process instability. In addition, the organic light emitting device may age after displaying for a period of time due to the material characteristics, and the threshold voltage may drift, so that the output current of the source driving circuit of the display is inconsistent when the same gray scale voltage is input.
The current compensation method is divided into two modes of in-pixel compensation and out-pixel compensation. The time sequence of the in-pixel compensation is complex, and the compensation effect is limited; the off-pixel compensation can better solve the problem by changing the input data voltage, and the panel can use the traditional 2T1C structure to maintain high aperture ratio and improve the display brightness with less thin film transistors.
For the method of off-pixel compensation, it is necessary to store the aging information or threshold voltage shift information of the pixels in the display memory, and when receiving the display data signal, add the data signal and the aging information (since the threshold voltage shift is generally embodied as a threshold voltage increase), and output the result to the pixel array of the display. Therefore, the compensation method requires an adder. For a traditional adder, the output stage operational amplifier often has the situations of voltage mismatch, capacitance mismatch and the like, so that the output precision is influenced. Meanwhile, in time sequence, the output of the capacitor sampling type adder with the traditional structure is in a high-impedance state in a sampling stage, so that no output signal is output at the output end of the source electrode driving circuit in the sampling stage, and the driving time of the pixel is reduced or limited. For a display circuit, reducing or limiting the driving time for a pixel means that the display accuracy is reduced under the same driving capability, or a larger driving circuit is employed to achieve the same accuracy, resulting in an increase in power consumption.
Disclosure of Invention
The present application is directed to the above-mentioned problem, and provides an adder unit, a display source driving circuit comprising: an adder unit comprising an addition module configured to sample a plurality of input signals in a first time period under the influence of a clock signal; a hold module configured to provide a hold signal for a first period of time under the influence of the clock signal; and a driving module configured to generate a first output signal based on the hold signal in the first period of time and generate a second output signal based on a superimposed signal of the plurality of input signals in a second period of time; wherein the plurality of input signals include at least a data signal and a compensation signal, and the first period and the second period are adjacent periods in the clock signal.
In particular, the first output signal corresponds to the output signal of the driving module in a third time period that is earlier than the first time period.
In particular, during the first period of time, the output of the holding module is coupled to the first input of the driving module, the input of the holding module is coupled to the first input or the second input or the output of the driving module to transmit the holding signal to the driving module, and the output of the adding module is disconnected from the first input of the driving module; and during the second time period, the output terminal of the addition module is coupled to the first input terminal of the driving module, the input terminal of the addition module is coupled to the first input terminal or the second input terminal or the output terminal of the driving module, so as to transmit the superposed signal of the plurality of input signals to the driving module, and the output terminal of the holding module is disconnected from the first input terminal of the driving module; and the second input end of the driving module is connected with the output end of the driving module.
In particular, the holding module comprises a first operational amplifier, a first input terminal of which is coupled to the reference low potential via a first capacitor (221, 321), a first switching element (223, 323), respectively, and a second input terminal of which is coupled to the first input terminal or the second input terminal or the output terminal of the driving module via a second capacitor (222, 322); the second input of the first operational amplifier is further coupled to the reference low potential through a second switching element (224, 324), the output of the first operational amplifier being coupled to the first input of the driving module via a third switching element (232, 332).
In particular, the summing module comprises a second op-amp, a first input of which is coupled to the specified potential, a second input of which samples the plurality of input signals via a plurality of sampling branches, a second input of the second op-amp being coupled to an output of the second op-amp via a fourth switching element (217, 317), and an output of the second op-amp being coupled to the first input of the driving module via a fifth switching element (231, 331).
In particular, the plurality of sampling branches comprises at least a first sampling branch comprising a third capacitor (211, 311) and a sixth switching element (213, 313) and a seventh switching element (215, 315), a first end of the third capacitor (211, 311) being coupled to the sixth switching element (213, 313) and being configured to receive a first input signal when the sixth switching element (213, 313) is conductive; the first terminal of the third capacitor (211, 311) is further coupled to the reference low potential through the seventh switching element (215, 315); and a second sampling branch comprising a fourth capacitor (212, 312) and an eighth switching element (214, 314) and a ninth switching element (216, 316), a first end of the fourth capacitor (212, 312) being coupled to the eighth switching element (214, 314) and configured to receive a second input signal when the eighth switching element (214, 314) is conductive; the first terminal of the fourth capacitor (212, 312) is further coupled to the first or second input or output of the driver module through the ninth switching element (216, 316); second terminals of the third capacitor (211, 311) and the fourth capacitor (212, 312) are coupled to a second input terminal of the second op-amp.
In particular, the driving module comprises a third operational amplifier, a second input terminal of which is coupled to an output terminal thereof.
Specifically, one or more of the first to ninth switching elements are transistors that operate based on the clock signal.
In particular, the sampling is a sampling in the analog domain, and the superimposed signal of the plurality of signals is a superimposed signal in the analog domain.
The present application further provides a display apparatus comprising a pixel array comprising pixel devices arranged in rows and/or columns; a gate driving device configured to supply switching signals to the pixel array through a plurality of scan lines; and a source driving device including a plurality of data lines and a plurality of adder units coupled to the plurality of data lines, the source driving device being configured to provide a signal obtained by superimposing a compensation signal and a data voltage signal in an analog domain to the pixel array.
The application also provides a display source voltage compensation method, wherein a source driving circuit of a display comprises an addition module, a holding module and a driving module, and the method comprises the steps of sampling a plurality of input signals through the addition module in a first time period and providing a holding signal to the driving module through the holding module so that the driving module takes the holding signal as a current output signal; in a second time period which is after the first time period and is adjacent to the first time period, the plurality of input signals are superposed on an analog domain through the addition module, and the superposed signals are transmitted to the driving module and the holding module, so that the driving module takes the superposed signals as output signals; wherein the hold signal is an output signal of the driving module in a third time period before the first time period.
By adopting the source electrode driving circuit of the adder unit provided by the application, the input signals can be superposed in a simulation domain, so that the requirement on a post-stage circuit is reduced, the application cost is reduced, the output time of the driving module is prolonged, the display precision is effectively improved, and the threshold voltage drift is reduced.
Drawings
Embodiments are shown and described with reference to the drawings. These drawings are provided to illustrate the basic principles and thus only show the aspects necessary for understanding the basic principles. The figures are not to scale. In the drawings, like reference numerals designate similar features.
FIG. 1 is a diagram of an adder unit architecture according to an embodiment of the present application;
FIG. 2 is a circuit diagram of an adder unit according to a first embodiment of the present application;
FIG. 3a is a circuit diagram of an adder unit according to a second embodiment of the present application;
FIG. 3b is a timing diagram of the input and output of an adder unit according to a second embodiment of the present application;
FIG. 4 is a diagram illustrating a display control method according to an embodiment of the present application;
fig. 5 is a schematic diagram of an architecture of a display device according to an embodiment of the present application.
Detailed Description
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings, which form a part hereof. The accompanying drawings illustrate, by way of example, specific embodiments in which the present application can be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments according to the application. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present application. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present application is defined by the appended claims.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. For the connection between the units in the drawings, for convenience of description only, it means that at least the units at both ends of the connection are in communication with each other, and is not intended to limit the inability of communication between the units that are not connected.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof and in which is shown by way of illustration specific embodiments of the application. In the drawings, like numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized and structural, logical or electrical changes may be made to the embodiments of the present application.
A transistor may refer to a transistor of any structure, such as a Field Effect Transistor (FET) or a Bipolar Junction Transistor (BJT). When the transistor is a field effect transistor, the control electrode of the transistor refers to a grid electrode of the field effect transistor, the first electrode can be a drain electrode or a source electrode of the field effect transistor, and the corresponding second electrode can be a source electrode or a drain electrode of the field effect transistor; when the transistor is a bipolar transistor, the control electrode of the transistor refers to a base electrode of the bipolar transistor, the first electrode may be a collector or an emitter of the bipolar transistor, and the corresponding second electrode may be an emitter or a collector of the bipolar transistor. The light emitting device in the present application may be an Organic Light Emitting Diode (OLED), a quantum dot light emitting diode (QLED), an inorganic Light Emitting Diode (LED), or the like.
Research shows that display uniformity of the active matrix organic light emitting diode can be improved by adding display data and compensation data aiming at material aging or threshold voltage drift in an analog domain within the driving time of a source electrode driving circuit for a pixel. On the contrary, in the process of implementing the above addition in the digital domain, the digital original signal and the digital compensation signal need to be added first and then pass through the digital-to-analog conversion module, so the digital method cannot improve the precision problem in the conversion process, and more bits can only maintain the original conversion precision. However, by always implementing the above-mentioned addition in the analog domain, the gamma curve of the display data and the gamma curve of the compensation signal can be respectively adjusted, and the compensation accuracy can be improved while maintaining the original gamma correction function for gray scale conversion.
Based on the above, the present application proposes a new capacitive analog adder cell, which can have a longer output time. According to the method and the device, the holding module is added in the adder unit, so that the driving module can output the potential of the previous holding time, for example, the data signal of the previous row, at the sampling time. Meanwhile, feedback driving is adopted in the sampling circuit, the offset voltage of the rear stage can be stored when sampling is finished, and mismatch of output of the operational amplifier can be reduced during output.
Fig. 1 is a block diagram of an adder unit according to an embodiment of the present disclosure.
As shown, the adder unit 100 includes an addition module 110, a holding module 120, and a driving module 130. The output of the summing block 110 and the output of the hold block 120 are coupled to the input of the drive block 130.
The adder unit operation is divided into a sample phase and a hold phase, and the operation of the adder unit 100 in the present application is explained in stages below.
A sampling stage:
the output of the summing module 110 is disconnected from the driving module 130 and samples a plurality of input signals (e.g., including the display data signal and the compensation signal for compensating for threshold voltage drift) at its input. The input and output terminals of the holding module 120 are respectively coupled to the driving module 130, so that the driving module 130 maintains outputting the current output first output signal. It will be appreciated that the first output signal corresponds to a signal generated by the summing block 110 after a previous sampling and superposition. In other words, when the addition module 110 samples (i.e., when the addition module is disconnected from the driving module 130), the holding module 120 is electrically connected to the driving module 130, and can continuously maintain the output of the driving module 130.
A maintaining stage:
the input and output of the summing module 110 are both coupled to the driving module 130, such that the driving module 130 outputs a superimposed signal (second output signal) representing the sum of the plurality of input signals in the analog domain; at this stage the output of the holding module 120 is disconnected from the driving module 130 and the output signal of the driving module 130 is stored at the input for use in the next sampling stage.
It is understood that the plurality of input signals herein may include two, three or even more input signals. For ease of understanding, two input signals are illustrated below.
Fig. 2 is a circuit diagram of an adder unit according to a first embodiment of the present application.
The adder unit comprises an adding module 210, a holding module 220 and a driving module 230, wherein an output of the adding module 210 and an output of the holding module 220 are coupled to a positive input of the driving module 230 via different switching elements, respectively, an output of the driving module 230 is coupled to a negative input thereof forming a negative feedback connection, and a negative input of the driving module 230 is further coupled to negative inputs of the adding module 110 and the holding module 120.
According to one embodiment, the summing module 210 includes an OP-amp 1, a capacitor 211, a capacitor 212, and a switch 213-217. The operational amplifier OP1 has a positive input coupled to the fixed potential Vcm and a negative input coupled to the capacitor 211 and the capacitor 212, respectively. The negative input and output of the OP-amp OP1 are coupled through the switch 217. The capacitor 211 and the capacitor 212 receive input voltage signals Vin1 and Vin2 (which may include a display data signal and a compensation signal) through signal receiving switches 213 and 214, respectively. The capacitor 211 is also coupled to ground (or a low reference potential) through a bypass switch 215, and the capacitor 212 is coupled to the output of the driver module 230 through a switch 216 to receive a feedback signal from the driver module 230. The output of the OP-amp OP1 is coupled to the positive input of the driver module 230.
According to one embodiment, the holding module 220 comprises an operational amplifier OP2, a capacitor 221-. The negative input of the OP-amp OP2 is also coupled to ground (or reference low) through a switch 224.
According to one embodiment, the driving module 230 comprises an OP-amp OP3, a switch 231 and 232, wherein the positive input terminal of the OP-amp OP3 is coupled to the output terminal of the OP-amp OP1 via the switch 231 and to the output terminal of the OP-amp OP2 via the switch 232, and the negative input terminal of the OP-amp OP3 is coupled to its own output terminal, forming a unit negative feedback.
The operation of the adder unit in this embodiment is divided into a sampling phase and a holding phase, and the operation of the adder unit is explained in stages below.
A first time period: sampling phase
In this stage, switches 213, 214, 217, and 232 in fig. 2 are closed, and the remaining switches are open. The summing block 210 samples the input signals Vin1, Vin2, i.e., the two signals charge the left plates of the capacitors 211, 212. Because the switches 215, 216, 231 are open and the switch 232 is closed, the holding modules 220 and 230 form a closed loop negative feedback connection, thereby enabling the holding module 220 to maintain the driving module 230 to continue outputting the current output signal (i.e., the signal output by the driving module 230 during the previous time period). During the sampling phase, OP1 forms a closed loop negative feedback connection because switch 217 is closed. Therefore, the right plate potentials of the capacitors 211 and 212 and the potentials of the negative input terminal and the output terminal of the OP1 are the input signal Vcm at the positive input terminal.
A second time period: hold phase
In this stage, switches 213, 214, 217, and 232 in fig. 2 are open, and the remaining switches are closed. At this time, the output terminal of the holding module 220 is disconnected from the positive input terminal of the driving module 230, the output terminal of the adding module 210 is coupled to the positive input terminal of the operational amplifier OP3 via the switch 231, and the negative input terminal of the operational amplifier OP3 is coupled to the negative input terminal of the adding module via the switch 216 and the capacitor 212. During the hold phase, due to the conservation of charge at the right plates of the capacitors 211, 212, while the left plate of the capacitor 211 is coupled to ground potential, a charge transfer effect is generated, the potential of the left plate of the capacitor 212 becomes Vin1+ Vin2, and the potential of the right plate is Vcm. Since the summing module 210 forms negative feedback with the driving module 230 and the negative input terminal and the output terminal of the operational amplifier OP3 are connected to form unit negative feedback, the output signal Vo of the operational amplifier OP3 can be stabilized and output the voltage Vin1+ Vin2 (the output terminal of OP3 is connected to the left plate of the capacitor 212 through the switch 216), and the voltage at the output terminal of the operational amplifier OP1 is also Vin1+ Vin 2.
In addition, the output signal Vo is coupled to the negative input terminal of the OP-amp OP2 via the capacitor 222, so that when the switches 223 and 224 are closed, the left plate of the capacitor 222 lacks a discharge path, and the potential holding can be achieved, i.e., the potential of the left plate of the capacitor 222 is Vin1+ Vin 2. When the adding module 210 enters the next sampling phase, the holding module 220 can make the potential of the output signal Vo of the driving module 230 still equal to Vin1+ Vin 2. The capacitor 221 and the switch 223, which are coupled to ground potential, are arranged to create a symmetrical environment for the capacitor 222 so that the output of OP2 is equal to the input of its negative input.
It will be appreciated that the above described switches may be implemented as switching legs or switching elements comprising transistors.
FIG. 3a is a circuit diagram of an adder unit according to a second embodiment of the present application.
In this embodiment, the positive input of the driving module 330 is coupled to the negative inputs of the OP-amps OP1, OP2 via capacitors 312 and 322, respectively. The operation of the adder unit in this embodiment is still divided into a sample phase and a hold phase, similar to the first embodiment, and the operation of the adder unit is explained in stages below.
A first time period: sampling phase
In this stage, switches 313, 314, 317 and 332 in fig. 3 are closed and the remaining switches are open. The summing module 310 samples the input signals Vin1, Vin 2. When the switches 316 and 331 are turned off, the holding module 320 enables the driving module 330 to maintain the previous state of the output voltage.
A second time period: hold phase
In this stage, switches 313, 314, 317 and 332 in fig. 3 are open and the remaining switches are closed. At this time, the output terminal of the OP-amp OP1 is coupled to the positive input terminal of the OP-amp OP3 via the switch 331. The summing module 310 and the driving module 330 form a path for charge transfer between the capacitors 311 and 312, and the output signal Vo of the driving module 330 is gradually stabilized to two input voltages Vin1 and Vin 2. Specifically, since the left plate of the capacitor 312 is coupled to the positive input terminal of the OP-amp OP3 and the OP-amp OP3 has a connection with unit negative feedback, the potential of the output signal Vo of the OP-amp OP3 is updated to Vin1+ Vin2 at this time.
Compared to the first embodiment, the output terminal (or negative input terminal) of the driving module 330 in this embodiment is not coupled to the input terminals of the adding module 310 and the holding module 320. The positive input of the driving block 330 is coupled to the negative inputs of the adding block 310 and the holding block 320 through capacitors 312 and 322, respectively.
Through the above configuration, in the sampling stage, the output terminal of the holding module 320 is coupled with the negative input terminal to form negative feedback; during the hold phase, the output of the summing module 310 is coupled to its negative input via switch 316, forming negative feedback.
FIG. 3b is a timing diagram of the input and output of an adder unit according to a second embodiment of the present application. The timing sequence in fig. 3b applies equally to the adder unit in fig. 2.
The clock signal CLK in the figure is used to control the switching of the various switches in the adder unit. For example, when the switch is implemented with a transistor, the clock signal CLK may be coupled to a gate of the transistor.
A sampling stage: T1-T2
During this time, the addition module 310 receives the input signal and is disconnected from the driving module 330; the holding module 320 is coupled to the positive input of the driving module 330 to provide the saved signal (i.e., the output signal of the current state of the driving module 330) to the driving module 330. Thus, between T1-T2, the addition module 310 enables sampling of the signals v12 and v22, and the hold module 320 causes the drive module 330 to continue outputting the current output signal, i.e., the sum of the signals v11 and v21 in the analog domain.
A maintaining stage: T2-T3
During this time, the output of the holding module 320 is disconnected from the driving module 330, and the adding module 310 is coupled to the driving module 330 to provide the driving module 330 with the added signals of the signals v12 and v 22.
It will be appreciated that the time periods T3-T4 correspond to the sampling phase, and that the hold module 320 continues to provide the drive module with the summed signals Vo of v12 and v22 in the analog domain (i.e., v12+ v 22). It will be appreciated that the duration of the output signal Vtp of the adder unit shown in fig. 3b, which does not comprise the holding module 320, is reduced by half compared to the solution in the present application.
In addition, although the addition module 310 and the driving module 330 in the above embodiments both use a connection method of unit negative feedback, it can be understood by those skilled in the art that the above modules may also use other negative feedback forms.
It can be seen from the above embodiments that, when the adding modules 210 and 310 perform sampling, the holding modules 220 and 320 can still maintain the outputs of the driving modules 230 and 330, so that when the output terminals of the driving modules 230 and 330 are coupled to the pixel devices, the pixel devices can be charged, and the situation that the driving modules 230 and 330 start charging the pixel devices after the sampling is finished is avoided, so as to achieve the same output level, and the power consumption of the driving modules 230 and 330 is reduced by using the scheme of the present application.
Fig. 4 is a schematic diagram of a display control method according to an embodiment of the present application.
Step S401: the hold module provides a hold signal to the drive module and the summing module samples the first plurality of input signals.
In this step, the summing module samples the received first plurality of input signals in the analog domain under the influence of the clock signal. Meanwhile, the holding module provides a holding signal to the driving module to maintain the driving module to output the current output signal. Wherein the hold signal may be a pixel display data signal of a previous row.
Step S402: the addition module superposes the first plurality of input signals to generate a data signal of the current row and provides the data signal of the current row to the driving module.
In this step, the first plurality of input signals are superimposed in the analog domain by the addition module and the superimposed signals are transmitted to the driving module and the holding module, so that the driving module outputs the updated output signals. In this step the holding module is disconnected from the drive module.
Step S403: the holding module keeps outputting the data signals of the current row to the driving module, and the adding module samples the second plurality of input signals again to obtain the data signals of the next row.
In this step, the holding module maintains the driving module to output the updated output signal based on the superimposed signal, and the adding module re-samples the input.
Fig. 5 is a schematic diagram of an architecture of a display device according to an embodiment of the present application.
The display device 500 includes a pixel array 510, a gate driving circuit 520, and a data driving or source driving circuit 530. In particular, pixel array 510 includes pixel devices arranged in rows and/or columns; the gate driving circuit 520 is used for providing a switching signal O < n > to the pixel array 510 via a plurality of scanning lines; the data driving circuit 530 includes a plurality of data lines and a plurality of adder units, and the data driving circuit 530 compensates the signal D < n > obtained by superimposing the signal (e.g., the signal Vin2) and the data voltage signal (e.g., the signal Vin1) on the analog domain to the source of the pixel array 510 through the plurality of data lines, so as to compensate for the threshold voltage shift or the change of the parameters such as the electron mobility of the pixel devices in the pixel array 510. For example, when the threshold voltage drift of the pixel device is 0.5mV, the data voltage signal received by the pixel device can be increased by 0.5mV by adding Vin1 and Vin2, thereby avoiding the problem of accuracy degradation caused by the threshold voltage drift.
Based on the above configuration, the gate driving circuit 520 may sequentially turn on at least one row/column of the pixel array 510, so that the pixel array 510 can read the data signal output by the data driving circuit 530. In addition, since the adder unit can also output the source compensation signal in the sampling stage, the charging time of the pixel devices in the pixel array 510 can be prolonged, and the accuracy can be further improved.
Thus, while the present application has been described with reference to specific examples, which are intended to be illustrative only and not to be limiting of the application, it will be apparent to those of ordinary skill in the art that changes, additions or deletions may be made to the disclosed embodiments without departing from the spirit and scope of the application.
Claims (10)
1. A display source driving circuit, comprising:
an adder unit comprising
An addition module configured to sample the plurality of input signals in a first time period under the influence of the clock signal;
a hold module configured to provide a hold signal for a first period of time under the influence of the clock signal; and
a driving module configured to generate a first output signal based on the hold signal in the first period of time and generate a second output signal based on a superimposed signal of the plurality of input signals in a second period of time;
wherein the plurality of input signals at least include a data signal and a compensation signal, and the first time period and the second time period are adjacent time periods in the clock signal;
wherein the hold signal and the first output signal correspond to the output signal of the driving module in a third period of time earlier than the first period of time.
2. The circuit of claim 1, wherein,
during the first time period, the output terminal of the holding module is coupled to the first input terminal of the driving module, the input terminal of the holding module is coupled to the first input terminal or the second input terminal or the output terminal of the driving module to transmit the holding signal to the driving module, and the output terminal of the adding module is disconnected from the first input terminal of the driving module; and
during the second time period, the output end of the addition module is coupled to the first input end of the driving module, the input end of the addition module is coupled to the first input end or the second input end or the output end of the driving module so as to transmit the superposed signal of the plurality of input signals to the driving module, and the output end of the holding module is disconnected from the first input end of the driving module;
and the second input end of the driving module is connected with the output end of the driving module.
3. The circuit of claim 2, wherein the holding module comprises:
a first operational amplifier, a first input terminal of which is coupled to a reference low potential via a first capacitor (221, 321) and a first switching element (223, 323), respectively, and a second input terminal of which is coupled to a first input terminal or a second input terminal or an output terminal of the driving module via a second capacitor (222, 322);
the second input of the first operational amplifier is further coupled to the reference low potential through a second switching element (224, 324), the output of the first operational amplifier being coupled to the first input of the driving module via a third switching element (232, 332).
4. The circuit of claim 3, wherein the summing block comprises:
a second op-amp having a first input coupled to a specified potential, a second input sampling the plurality of input signals via a plurality of sampling branches, a second input of the second op-amp being coupled to an output of the second op-amp via a fourth switching element (217, 317), and an output of the second op-amp being coupled to the first input of the driving module via a fifth switching element (231, 331).
5. The circuit of claim 4, wherein the plurality of sampling branches comprise at least
A first sampling branch comprising a third capacitor (211, 311) and a sixth switching element (213, 313) and a seventh switching element (215, 315), a first end of the third capacitor (211, 311) being coupled to the sixth switching element (213, 313) and configured to receive a first input signal when the sixth switching element (213, 313) is conductive; the first terminal of the third capacitor (211, 311) is further coupled to the reference low potential through the seventh switching element (215, 315); and
a second sampling branch comprising a fourth capacitor (212, 312) and an eighth switching element (214, 314) and a ninth switching element (216, 316), a first end of the fourth capacitor (212, 312) being coupled to the eighth switching element (214, 314) and configured to receive a second input signal when the eighth switching element (214, 314) is conductive; the first terminal of the fourth capacitor (212, 312) is further coupled to the first or second input or output of the driver module through the ninth switching element (216, 316);
second terminals of the third capacitor (211, 311) and the fourth capacitor (212, 312) are coupled to a second input terminal of the second op-amp.
6. The circuit of claim 4, wherein the driver module comprises a third op-amp having a second input coupled to an output thereof.
7. The circuit of claim 5, wherein one or more of the first to ninth switching elements are transistors operating based on the clock signal.
8. The circuit of claim 1, wherein the sampling is sampling in the analog domain and the superimposed signal of the plurality of input signals is a superimposed signal in the analog domain.
9. A display device, comprising:
a pixel array comprising pixel devices arranged in rows and/or columns;
a gate driving device configured to supply switching signals to the pixel array through a plurality of scan lines; and
a source driving apparatus comprising a plurality of data lines and a plurality of adder units according to any one of claims 1 to 8 coupled to the plurality of data lines, the source driving apparatus being configured to provide signals obtained by superimposing compensation signals and data voltage signals in an analog domain to the pixel array.
10. A method for compensating a source voltage of a display, wherein a source driving circuit of the display comprises an addition module, a holding module and a driving module, the method comprises the following steps:
sampling a plurality of input signals through the addition module in a first time period, and providing a holding signal to the driving module through the holding module so that the driving module takes the holding signal as a current output signal; and
in a second time period which is after the first time period and is adjacent to the first time period, the plurality of input signals are superposed on an analog domain through the addition module, and the superposed signals are transmitted to the driving module and the holding module, so that the driving module takes the superposed signals as output signals;
wherein the hold signal is an output signal of the driving module in a third time period before the first time period.
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| CN201910070697.2A CN109658868B (en) | 2019-01-25 | 2019-01-25 | Adder unit and display device |
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| CN102157138B (en) * | 2011-04-14 | 2013-01-02 | 深圳市华星光电技术有限公司 | Liquid crystal display and driving method thereof |
| KR101985243B1 (en) * | 2012-09-26 | 2019-06-05 | 엘지디스플레이 주식회사 | Organic Light Emitting Display Device, Driving Method thereof and Manufacturing Method thereof |
| CN103280180B (en) * | 2013-05-28 | 2015-05-27 | 中国科学院上海高等研究院 | Active organic light emitting diode-based display circuit and driving method |
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