CN109656630B - Configuration space access method, device, framework and storage medium - Google Patents
Configuration space access method, device, framework and storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Abstract
The embodiment of the invention provides an access method and device of a configuration space, a processor architecture and a storage medium, wherein the processor architecture with a bridge chip comprises a processor and the bridge chip, the processor is connected with the bridge chip through an HT bus, an address space corresponding to a PCI/PCIe device configuration space is reserved in an address window in an HT interface of the processor, and the method comprises the following steps: loading a first driver by utilizing a uniform extensible firmware interface, wherein the first driver is a driver for accessing a PCI/PCIe device configuration space through an address space reserved on a processor; installing an access protocol for accessing a PCI/PCIe device configuration space according to the first driver; and according to the access protocol, utilizing the first driver to realize the access operation on the PCI/PCIe device configuration space. Therefore, the access of the CPU to the PCI/PCIe device configuration space can be realized through the address space by utilizing the first driver, so that the realization mode of the access to the PCI/PCIe device configuration space is expanded to ensure the use of the bridge chip.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method and an apparatus for accessing a configuration space, a processor architecture, and a storage medium.
Background
At present, the main functions of UEFI (Unified Extensible Firmware Interface, english: Unified Extensible Firmware Interface) Firmware are to initialize a host hardware device and guide an operating system, a PCI (Peripheral Component Interconnect, english: Peripheral Component Interconnect)/PCIe (Peripheral Component Interconnect Express) device is used as an important Peripheral device of a host, and the initialization of the PCI/PCIe device becomes one of important functions of the UEFI Firmware, and the PCI/PCIe device needs to access a PCI/PCIe configuration space for initialization.
The UEFI firmware accesses the PCI/PCIe device configuration space based on X86 and an ARM platform, the configuration space is accessed through two groups of I/O registers provided by a CPU, and currently, the access to the PCI/PCIe device configuration space by using an address space cannot be realized on a Microprocessor with interlocked pipeline (MIPS) platform.
Disclosure of Invention
In view of the above, embodiments of the present invention are proposed to provide a configuration space access method that overcomes or at least partially solves the above mentioned problems to enable access to a PCI/PCIe device configuration space through an address space.
Correspondingly, the embodiment of the invention also provides an access device for configuration space, a processor architecture and a storage medium, which are used for ensuring the implementation and application of the method.
In order to solve the above problem, an embodiment of the present invention discloses an access method for a configuration space, which is applied to a processor architecture with a bridge chip, where the processor architecture with the bridge chip includes a processor and a bridge chip, the processor is connected to the bridge chip through an end-to-end bus technology HT bus, and an address space corresponding to a PCI/PCIe device configuration space is reserved in an address window inside an HT interface of the processor, and the method includes:
loading a first driver by using a unified extensible firmware interface, wherein the first driver accesses the PCI/PCIe device configuration space through the address space reserved on the processor;
installing an access protocol for accessing the PCI/PCIe device configuration space according to the first driver;
and according to the access protocol, utilizing the first driver to realize the access operation on the PCI/PCIe device configuration space.
Optionally, before the step of loading the first driver by using the unified extensible firmware interface, the method further includes:
mapping the PCI/PCIe device configuration space onto the address space.
Optionally, the installing, by using the first driver, an access protocol for accessing the PCI/PCIe device configuration space includes:
starting a preset interface for installing an access protocol according to the first drive;
and installing the access protocol on a preset handle of a driver of the PCI/PCIe device by utilizing the interface.
Optionally, the implementing, according to the access protocol, an access operation to the PCI/PCIe device configuration space by using the first driver includes:
calling a protocol instance provided in the first driver;
and according to the protocol example, utilizing the first driver to perform the access operation on the PCI/PCIe device configuration space.
The embodiment of the present invention further discloses an access device for configuration space, which is applied to a processor architecture with a bridge chip, wherein the processor architecture with the bridge chip comprises a processor and a bridge chip, the processor is connected with the bridge chip through an end-to-end bus technology HT bus, and an address space corresponding to a PCI/PCIe device configuration space is reserved in an address window inside an HT interface of the processor, and the access device comprises:
the driver loading module is used for loading a first driver by utilizing a uniform extensible firmware interface, wherein the first driver accesses the PCI/PCIe device configuration space through the address space reserved on the processor;
the protocol installation module is used for installing an access protocol for accessing the PCI/PCIe equipment configuration space according to the first driver;
and the access operation module is used for realizing the access operation on the PCI/PCIe device configuration space by utilizing the first driver according to the access protocol.
Optionally, the apparatus further comprises:
and the control mapping module is used for mapping the PCI/PCIe device configuration space to the address space before the step of loading the first drive by using the unified extensible firmware interface.
Optionally, the protocol installation module includes:
the interface starting submodule is used for starting a preset interface for installing an access protocol according to the first drive;
and the protocol installation submodule is used for installing the access protocol on a preset handle of the driver of the PCI/PCIe equipment by utilizing the interface.
Optionally, the access operation module includes:
the instance calling submodule is used for calling the protocol instance provided in the first driver;
and the access operation sub-module is used for performing the access operation on the PCI/PCIe device configuration space by utilizing the first driver according to the protocol instance.
The embodiment of the invention also discloses a processor architecture which comprises a processor, a bridge chip, a memory and one or more programs, wherein the processor is connected with the bridge chip through an end-to-end bus technology HT bus, and an address space corresponding to the PCI/PCIe device configuration space is reserved in an address window in the HT interface of the processor; the one or more programs are stored in the memory and configured to be executed by the processor include instructions for:
loading the first driver by using a uniform extensible firmware interface;
installing an access protocol for accessing the PCI/PCIe device configuration space according to the first driver;
and according to the access protocol, utilizing the first driver to realize the access operation on the PCI/PCIe device configuration space through the address space reserved on the bridge chip.
The embodiment of the invention also discloses a readable storage medium, and when instructions in the storage medium are executed by a processor of the electronic equipment, the electronic equipment can execute one or more configuration space access methods in the embodiment of the invention.
The embodiment of the invention has the following advantages:
loading a first driver by using a uniform extensible firmware interface, wherein the first driver accesses the PCI/PCIe device configuration space through the address space reserved on the processor; installing an access protocol for accessing the PCI/PCIe device configuration space according to the first driver; and according to the access protocol, utilizing the first driver to realize the access operation on the PCI/PCIe device configuration space. Therefore, the CPU can realize the access to the PCI/PCIe device configuration space through the reserved address space by using the first driver, thereby expanding the realization mode of the access to the PCI/PCIe device configuration space to ensure the use of the bridge chip.
Drawings
FIG. 1 is a flow chart illustrating the steps of an embodiment of a method for accessing a configuration space according to the present invention;
FIG. 2 is a block diagram of a processor architecture of the present invention;
FIG. 3 is a flow chart of steps in another embodiment of a method for accessing configuration space of the present invention;
FIG. 4 is a diagram illustrating address field meaning for a PCI/PCIe configuration space;
FIG. 5 is a block diagram of an embodiment of an apparatus for accessing configuration space according to the present invention;
fig. 6 is a block diagram of an embodiment of an access device for configuring a space according to the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
The core concept of the embodiment of the invention is that a PCI/PCIe device configuration space is mapped to the address space reserved by the CPU by using a first driver, namely an address space access driver, so that the CPU accesses the PCI/PCIe device configuration space by using UEFI.
Referring to fig. 1, a flowchart illustrating steps of an embodiment of a method for accessing a configuration space according to the present invention is shown, and is applied to a processor architecture with a bridge chip, where the processor architecture with a bridge chip includes a processor and a bridge chip, the processor is connected to the bridge chip through an HT (english: Hyper Transport, chinese: end-to-end bus technology) bus, and an address space corresponding to a PCI/PCIe device configuration space is reserved in an address window inside an HT interface of the processor, and specifically, the method may include the following steps:
The first driver is a driver for accessing the PCI/PCIe device configuration space through the address space reserved on the processor.
Illustratively, the processor can implement the loading operation of the first driver based on UEFI, wherein the UEFI specification is developed from EFI (Extensible Firmware Interface), which is a proposed standard proposed by Intel for architecture, Interface and service of PC Firmware (or called BIOS), since the UEFI is a service-type protocol, the processor loads the first driver on the bridge that enables access to the PCI/PCIe device configuration space through the address space by initiating a service provided in the service-type protocol, the processor may be a CPU of the MIPS architecture, an address space corresponding to a PCI/PCIe device configuration space is reserved in an address window inside an HT interface in a CPU of the MIPS framework, such as a Loongson 3A processor.
The MIPS platform-based CPU may be connected to a bridge chip via an HT bus, the bridge chip is connected to various other devices and/or memory spaces, the bridge chip is connected to PCI/PCIe devices via a PCI bus, and the PCI bus may also be connected to other PCI buses for expanding the number of PCI devices, as shown in the block diagram connection manner shown in fig. 2. The CPU reserves an address space in an address window in the HT interface, wherein the address space corresponds to a PCI/PCIe device configuration space. Since the PCI/PCIe devices have their own independent address spaces, this portion of the space is mapped to the entire system's address space. The mapping address is specified in BIOS/UEFI in two types, one is MMIO (Chinese: Memory mapping I/O) and the other is I/O. I/O access to PCI/PCIe devices is typically performed in a manner that occupies very little space, approximately 64K, compared to MMIO. There are also two parts of space used by PCI/PCIe devices, one part called configuration space (through MMIO); the other part is designated by a BAR (Chinese: Base Address Register) Register of a configuration space, and is an Address space required by the equipment to realize functions. The transaction type in the configuration space is a read-write operation type, the data transmission means that a certain unit of the PCI/PCIe device configuration space or data is read from a certain unit of the PCI/PCIe device configuration space, and the 4kB PCI/PCIe device configuration space is used for discovering the functions of the device through configuration, programming the plug-and-play characteristic and checking the state in the same way in the PCI/PCIe device.
And 102, installing an access protocol for accessing the PCI/PCIe device configuration space according to the first driver.
Illustratively, after the first driver is installed, the Protocol (Protocol) for accessing the PCI/PCIe device configuration space based on the UEFI is installed on the driver of the PCI/PCIe device by using the provided corresponding interface, so as to access the PCI/PCIe device configuration space.
And 103, utilizing the first driver to realize the access operation on the PCI/PCIe device configuration space according to the access protocol.
In a specific application, after the first driver is installed, the PCI/PCIe device configuration space is accessed according to an instance in the Protocol, and data operation is correspondingly performed.
In summary, in the technical solution provided in the present application, a unified extensible firmware interface is used to load a first driver, and the first driver accesses a PCI/PCIe device configuration space through an address space reserved on a processor; installing an access protocol for accessing a PCI/PCIe device configuration space according to the first driver; and according to the access protocol, utilizing the first driver to realize the access operation on the PCI/PCIe device configuration space. Therefore, the access of the CPU to the PCI/PCIe device configuration space can be realized through the address space by utilizing the first driver, so that the realization mode of the access to the PCI/PCIe device configuration space is expanded to ensure the use of the bridge chip.
Optionally, referring to fig. 3, a flowchart of steps of another embodiment of the configuration space access method of the present invention is shown, which may specifically include the following steps:
For example, different from the existing access manner of the I/O register, the present application uses a reserved address space to map the PCI/PCIe device configuration space to the reserved address space, and further can use the first driver to implement access to the PCI/PCIe device configuration space, that is, before step 101, the operation of this step is performed. When the CPU accesses the bridge chip by using the address space (0xFE _0000_0000-0xFE _1FFF _ FFFF) reserved in the address window inside the HT interface, the maximum configuration space size of each device is 4 Kbytes, wherein [39:28] of the address determines the Type of the configuration header (0xFE0 is Type1, and 0xFE1 is Type 1); [23:16] denotes a Bus Number (Bus Number); [15:11] denotes a Device Number (Device Number); [10:8] denotes a Function Number (Function Number); the [27:24] and [7:0] combination represents an offset (offset), as shown in FIG. 4, which shows the meaning of the address field of the CPU accessing the PCI/PCIe device configuration space using the address space reserved by HT, it should be noted that the address space corresponding to the PCI/PCIe device configuration space is included in the reserved address space of HT, so the CPU accesses the bridge through HT, that is, the PCI/PCIe device configuration space is mapped to the address space reserved on HT, and then accesses the PCI/PCIe device configuration space.
This step is identical to step 101 shown in fig. 1 and will not be described herein.
Illustratively, an installprotocol interface (protocol installation interface) provided by UEFI is enabled in a module entry function by a driver of the PCI/PCIe device to enable installation of a preset Handle (Handle) on which an access protocol is installed.
Illustratively, the Protocol is installed on the ImageHandle of the driver of the PCI/PCIe device through the installprotocol interface, so that the driver of the PCI/PCIe device can call the Protocol instance provided by the first driver to perform operations of data access and mapping.
Illustratively, the driver of the PCI/PCIe device invokes an OpenProtocol to obtain a protocol instance provided by the first driver, so as to perform the access operation on the PCI/PCIe device configuration space, that is, perform the next step.
Illustratively, accessing the PCI/PCIe device configuration space is accomplished through a first driver.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.
Referring to fig. 5, a block diagram of an embodiment of an access apparatus for configuration space according to the present invention is shown, and is applied to a processor architecture with a bridge chip, where the processor architecture with a bridge chip includes a processor and a bridge chip, the processor is connected to the bridge chip through an end-to-end bus technology HT bus, and an address space corresponding to a PCI/PCIe device configuration space is reserved in an address window inside an HT interface of the processor, and specifically includes the following modules:
the driver loading module 510 is configured to load a first driver using the unified extensible firmware interface, where the first driver is a driver that accesses the PCI/PCIe device configuration space through an address space reserved on the processor.
A protocol installation module 520, configured to install an access protocol for accessing the PCI/PCIe device configuration space according to the first driver.
And an access operation module 530, configured to implement, according to the access protocol, an access operation on the PCI/PCIe device configuration space by using the first driver.
Optionally, referring to fig. 6, a block diagram of a structure of another embodiment of the access apparatus for configuration space of the present invention is shown, which may specifically include the following modules:
a control mapping module 540, configured to map the PCI/PCIe device configuration space to the address space before the step of loading the first driver using the unified extensible firmware interface.
Optionally, the protocol installation module 520 includes:
and the interface starting submodule 521 is configured to start a preset interface for installing an access protocol according to the first driver.
And a protocol installation sub-module 522 for installing the access protocol on a preset handle of the driver of the PCI/PCIe device using the interface.
Optionally, the access operation module 530 includes:
the instance calling submodule 531 is configured to call a protocol instance provided in the first driver.
And the access operation sub-module 532 is used for performing access operation on the PCI/PCIe device configuration space by using the first driver according to the protocol instance.
For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
The present application further provides a processor architecture, as shown in fig. 2, the processor architecture includes a processor, a bridge chip, a memory, and one or more programs, the processor is connected to the bridge chip through an HT bus, and an address space corresponding to a PCI/PCIe device configuration space is reserved in an address window inside an HT interface of the processor; the one or more programs are stored in the memory and configured to be executed by the processor include instructions for:
loading the first driver by using a uniform extensible firmware interface;
installing an access protocol for accessing a PCI/PCIe device configuration space according to the first driver;
and according to the access protocol, utilizing the first driver to realize the access operation on the PCI/PCIe device configuration space through the address space reserved on the processor.
In an exemplary embodiment, a non-transitory computer readable storage medium is also provided that includes instructions, such as a memory, that are executable by a processor in a processor architecture to perform the above-described method. For example, the non-transitory computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.
A non-transitory computer readable storage medium, instructions in which, when executed by a processor of a terminal, enable the terminal to perform a method of accessing a configuration space, the method comprising:
loading a first driver by using a uniform extensible firmware interface, wherein the first driver accesses a PCI/PCIe device configuration space through an address space reserved on a bridge chip;
installing an access protocol for accessing a PCI/PCIe device configuration space according to the first driver;
and according to the access protocol, utilizing the first driver to realize the access operation on the PCI/PCIe device configuration space.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a predictive manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The present invention provides a method and an apparatus for accessing a configuration space, an electronic device, and a storage medium, which are described in detail above, and the principles and embodiments of the present invention are described herein by using specific examples, and the descriptions of the above examples are only used to help understand the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A method for accessing a configuration space is applied to a processor architecture with a bridge chip, the processor architecture with the bridge chip comprises a processor and the bridge chip, the processor is connected with the bridge chip through an end-to-end bus technology (HT) bus, and an address space corresponding to a PCI/PCIe device configuration space is reserved in an address window inside an HT interface of the processor, and the method comprises the following steps:
loading a first driver by using a unified extensible firmware interface, wherein the first driver accesses the PCI/PCIe device configuration space through the address space reserved on the processor;
installing an access protocol for accessing the PCI/PCIe device configuration space according to the first driver;
and according to the access protocol, utilizing the first driver to realize the access operation on the PCI/PCIe device configuration space.
2. The method of claim 1, further comprising, prior to the step of loading the first driver using the unified extensible firmware interface:
mapping the PCI/PCIe device configuration space onto the address space.
3. The method of claim 1 or 2, wherein installing, according to the first driver, an access protocol for accessing the PCI/PCIe device configuration space comprises:
starting a preset interface for installing an access protocol according to the first drive;
and installing the access protocol on a preset handle of a driver of the PCI/PCIe device by utilizing the interface.
4. The method of claim 1 or 2, wherein the utilizing the first driver to implement the access operation to the PCI/PCIe device configuration space according to the access protocol comprises:
calling a protocol instance provided in the first driver;
and according to the protocol example, utilizing the first driver to perform the access operation on the PCI/PCIe device configuration space.
5. An apparatus for accessing a PCI/PCIe device configuration space, applied to a processor architecture with a bridge, where the processor architecture with the bridge includes a processor and a bridge, the processor is connected to the bridge through an end-to-end bus technology HT bus, and an address space corresponding to the PCI/PCIe device configuration space is reserved in an address window inside an HT interface of the processor, and the apparatus includes:
the driver loading module is used for loading a first driver by utilizing a uniform extensible firmware interface, wherein the first driver is a driver for accessing the PCI/PCIe device configuration space through the address space reserved by the processor;
the protocol installation module is used for installing an access protocol for accessing the PCI/PCIe equipment configuration space according to the first driver;
and the access operation module is used for realizing the access operation on the PCI/PCIe device configuration space by utilizing the first driver according to the access protocol.
6. The apparatus of claim 5, further comprising:
and the control mapping module is used for mapping the PCI/PCIe device configuration space to the address space before the step of loading the first drive by using the unified extensible firmware interface.
7. The apparatus of claim 5 or 6, wherein the protocol installation module comprises:
the interface starting submodule is used for starting a preset interface for installing an access protocol according to the first drive;
and the protocol installation submodule is used for installing the access protocol on a preset handle of the driver of the PCI/PCIe equipment by utilizing the interface.
8. The apparatus of claim 5 or 6, wherein the access operation module comprises:
the instance calling submodule is used for calling the protocol instance provided in the first driver;
and the access operation sub-module is used for performing the access operation on the PCI/PCIe device configuration space by utilizing the first driver according to the protocol instance.
9. A processor architecture is characterized by comprising a processor, a bridge chip, a memory and one or more programs, wherein the processor is connected with the bridge chip through an end-to-end bus technology HT bus, and an address space corresponding to a PCI/PCIe device configuration space is reserved in an address window inside an HT interface of the processor; the one or more programs stored in the memory and configured to be executed by the processor, the one or more programs including instructions for:
loading the first driver by using a uniform extensible firmware interface;
installing an access protocol for accessing the PCI/PCIe device configuration space according to the first driver;
and according to the access protocol, utilizing the first driver to realize the access operation on the PCI/PCIe device configuration space through the address space reserved on the processor.
10. A readable storage medium, characterized in that instructions in the storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the method of accessing a configuration space as claimed in one or more of the method claims 1-4.
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| CN112328198B (en) * | 2020-11-02 | 2022-08-26 | 长沙景嘉微电子股份有限公司 | Control method and device for graphic processor, display method and device for graphic processor, storage medium and electronic device |
| CN113194161B (en) | 2021-04-26 | 2022-07-08 | 山东英信计算机技术有限公司 | Method and device for setting MMIO base address of server system |
| CN114003170B (en) * | 2021-09-17 | 2024-03-19 | 方一信息科技（上海）有限公司 | FPGA-based Raid card driving method |
| CN116909639B (en) * | 2023-09-13 | 2023-12-12 | 珠海星云智联科技有限公司 | Mounting system, method, cluster and storage medium |
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