CN109643973B - Integrated amplifier - Google Patents
Integrated amplifier Download PDFInfo
- Publication number
- CN109643973B CN109643973B CN201680088735.1A CN201680088735A CN109643973B CN 109643973 B CN109643973 B CN 109643973B CN 201680088735 A CN201680088735 A CN 201680088735A CN 109643973 B CN109643973 B CN 109643973B
- Authority
- CN
- China
- Prior art keywords
- cancellation
- signal
- integrated amplifier
- input
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3223—Modifications of amplifiers to reduce non-linear distortion using feed-forward
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2201/00—Indexing scheme relating to details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements covered by H03F1/00
- H03F2201/32—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion
- H03F2201/3218—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion the main amplifier or error amplifier being a feedforward amplifier
Abstract
An integrated amplifier (100) is described, comprising an input (102) for receiving an input signal (Sin); an output (104) for outputting an output signal (Sout); an amplification circuit (106); and a cancellation circuit (114). The amplification circuit (106) is configured to provide an amplified input signal (Samp) based on the input signal (Sin), wherein the amplified input signal (Samp) comprises a fundamental tone and a cross-tone. The cancellation circuit (114) is configured to provide a cancellation signal (Sc) based on the input signal (Sin), wherein the cancellation signal (Sc) comprises a pitch and a cross-tune. The integrated amplifier (100) is configured to provide the output signal (Sout) based on a sum of the amplified input signal (Samp) and the cancellation signal (Sc) such that a cross-tuning of the amplified input signal (Samp) is attenuated by a cross-tuning of the cancellation signal (Sc).
Description
Technical Field
The present invention relates to an integrated amplifier comprising an amplifying circuit.
Background
High linearity Radio Frequency (RF) amplifiers are an important component of telecommunication systems. There are several different high linearity RF amplifiers on the market. There are high linearity amplifiers on the market that comprise a single transistor fabricated on a gallium arsenide (GaAs) substrate. Transistors on GaAs substrates have very good performance, one of which is their high linearity. However, the process of manufacturing RF amplifiers using GaAs is expensive and not suitable for system integration.
Transistors on silicon germanium (SiGe) substrates typically have low linearity. By using different techniques in order to achieve the same high linearity in transistors using SiGe as in transistors using GaAs. In some techniques, signals are cross-fed by using differential pairs in the amplifier to cancel intermodulation. Another technique is to use a bias circuit to feed back or feed forward the signal in order to linearize the amplifier.
As telecommunications systems become more integrated, there is a need for a structure that can meet the performance requirements of these individual amplifiers and that can be manufactured using inexpensive standard processes.
Disclosure of Invention
It is an object of embodiments of the present invention to provide an integrated amplifier to reduce the problems of the conventional solutions.
It is a further object of the invention to provide an integrated amplifier enabling amplification of an input signal containing a fundamental tone, wherein the amplitude of the intermodulation tones is substantially lower than in the case of the integrated amplifier used in the conventional scheme. Intermodulation refers to amplitude modulation of signals containing two or more different frequencies caused by the non-linearity of the integrated amplifier.
The above object is achieved by the subject matter of the independent claims. Further advantageous implementations of the invention can be found in the dependent claims.
According to a first aspect of the present invention, there is provided an integrated amplifier comprising: an input for receiving an input signal; an output terminal for outputting an output signal; an amplifying circuit; and a cancellation circuit. Wherein the amplification circuit is configured to provide an amplified input signal based on the input signal, wherein the amplified input signal comprises a fundamental tone and a intermodulation tone; the cancellation circuit is configured to provide a cancellation signal based on the input signal, wherein the cancellation signal includes a fundamental tone and a cross-tone; the integrated amplifier is configured to provide the output signal based on a sum of the amplified input signal and the cancellation signal such that a cross-tuning of the amplified input signal is attenuated by a cross-tuning of the cancellation signal.
The amplifying circuit and the cancelling circuit are connected between the input terminal and the output terminal.
With the integrated amplifier of the first aspect, the input signal containing the fundamental tone and the intermodulation caused by the nonlinearity in the amplifying circuit can be attenuated. The degree of attenuation of the intermodulation products of the amplified input signal is dependent on the magnitude of the intermodulation products of the cancellation signal. The described integrated amplifier thus reduces the effect of non-linearities in the amplification circuit, whereas the requirements on the manufacturing process of the amplification circuit can be relaxed compared to conventional solutions.
In a first possible implementation form of the integrated amplifier of the first aspect, the phase of the cancellation signal is opposite to the phase of the amplified input signal. This way the attenuation of the intermodulation of the amplified input signal is optimized.
According to a first possible implementation form, in a second possible implementation form of the integrated amplifier, a first ratio is the amplitude of the fundamental tone of the cancellation signal divided by the amplitude of the cross-tuning of the cancellation signal, and a second ratio is the amplitude of the fundamental tone of the amplified input signal divided by the amplitude of the cross-tuning of the amplified input signal, wherein the second ratio is greater than the first ratio. By selecting such a ratio, the pitch of the amplified input signal is not unnecessarily attenuated.
According to a second possible implementation manner, in a third possible implementation manner of the integrated amplifier, the amplitude of the intermodulation product of the cancellation signal is the same as the amplitude of the intermodulation product of the amplified input signal. Ideally, the amplitude of the intermodulation of the cancellation signal is equal to the amplitude of the intermodulation of the amplified input signal, so that the intermodulation of the amplified input signal is completely cancelled.
In a fourth possible implementation form of the integrated amplifier according to the first aspect as such or any one of the first to third implementation forms of the first aspect, the cancellation circuit comprises a cancellation transistor and a cancellation output terminal, wherein the cancellation circuit is configured to output the cancellation signal at the cancellation output terminal. Since the cancellation circuit can be set to have a non-linear characteristic similar to that of the amplification circuit, a transistor is a preferred device for generating the cancellation signal.
According to a fourth implementation form, in a fifth possible implementation form of the integrated amplifier, the cancellation circuit comprises a cancellation input, a cancellation impedance and a current source, wherein the cancellation transistor comprises an input terminal and an output terminal, the output terminal is connected to the cancellation output, the input terminal is connected to the current source, and the input terminal is connected to the cancellation input via the cancellation impedance.
In a fifth possible implementation, the cancellation signal will be provided as a current. Preferably, the amplified input signal is also provided as a current, which will therefore enable a simple addition of the cancellation signal to the amplified input signal. Of course, the cancellation signal and the amplified input signal may also be converted to voltages before being added to the cancellation signal.
In a fifth possible implementation, the cancellation circuit receives the input signal at the cancellation input. The current through the current source is substantially constant. The current through the current source is the sum of the current through the cancellation transistor and the current through the cancellation impedance. As the input signal increases, the current through the cancelling impedance also increases. As the current through the cancellation impedance increases, the current through the cancellation transistor and the current to the cancellation output both decrease. Thus, the phase of the current to the cancellation output will be opposite to the phase of the input signal. When the input signal increases, the amplified input signal, i.e. the current to the amplified output, increases. The current in the form of the cancellation signal will add to the current in the form of the amplified input signal to produce the output signal. Thus, the phase of the amplified input signal will be substantially the same as the phase of the input signal, but opposite to the phase of the cancellation signal. Due to the non-linear characteristics of the cancellation transistor, the cancellation signal will have a similar intermodulation to the amplified input signal. By properly evaluating the magnitude of the current source and the cancellation impedance, the cancellation signal will have a large intermodulation and a small pitch. This is in contrast to the design of the amplifier circuit with as little intermodulation as possible. By making the estimate to the cancellation circuit, the cancellation signal will essentially attenuate the intermodulation tones.
According to a fifth possible implementation form, in a sixth possible implementation form of the integrated amplifier, the current source is programmable. By making the current source programmable, the integrated amplifier can be tuned to maximally attenuate the intermodulation tones.
In a seventh possible implementation form of the integrated amplifier according to the fifth or sixth possible implementation form, the integrated amplifier comprises an impedance buffer (e.g. a buffer amplifier) connected between the input terminal and the cancellation input terminal. The impedance buffer minimizes the effect of the cancellation circuit on the input signal.
In an eighth possible implementation form of the integrated amplifier according to any one of the fifth to seventh possible implementation forms, the current source comprises a cancellation power supply and a supply resistor, wherein the supply resistor is connected between the cancellation power supply and the cancellation input terminal. This is the simplest implementation of the current source. Of course, the current source may also be implemented in many other ways.
In a ninth possible implementation form of the integrated amplifier according to any of the fifth to eighth possible implementation forms, the cancelling impedance comprises a resistor in series with a capacitor. The capacitor will pass Alternating Current (AC) signals between different DC levels.
In a tenth possible implementation form of the integrated amplifier according to the ninth possible implementation form, at least one of the resistor and the capacitor is programmable. By making one or both of the resistor and the capacitor programmable, the integrated amplifier can be tuned to optimize the attenuation of the intermodulation tones.
In an eleventh possible implementation form of the integrated amplifier according to any one of the fourth to tenth possible implementation forms, the amplifying circuit comprises an amplifying transistor, wherein the cancelling transistor is of the same type as the amplifying transistor. In order to effectively cancel the intermodulation of the amplified input signal, it is critical to make the nonlinear characteristic of the cancellation transistor as similar as possible to that of the amplification transistor. This may be achieved at least in part by the cancellation transistor being of the same type as the amplification transistor.
In a twelfth possible implementation form of the integrated amplifier according to the eleventh possible implementation form, the cancellation transistor is matched with the amplification transistor in at least one of the following respects: the temperature during operation, the current density during operation and the manufacturing process, i.e. the manufacturing process of the cancellation transistor is matched to the manufacturing process of the amplification transistor. By matching the amplifying transistor and the canceling transistor, their non-linear characteristics are made similar. This is advantageous to counteract the intermodulation as much as possible.
In a thirteenth possible implementation form of the integrated amplifier according to any one of the fifth to twelfth possible implementation forms, the integrated amplifier comprises an input impedance and a first power supply, wherein the amplifying circuit comprises an amplifying input terminal, and the input impedance is connected between the amplifying input terminal and the first power supply. The input impedance determines the characteristics of the amplification circuit. The power supply may be a voltage supply.
In a fourteenth possible implementation form of the integrated amplifier according to the thirteenth possible implementation form, the input impedance is matched to the cancellation impedance. The input impedance is matched to the cancellation impedance to ensure that the phase difference between the amplified input signal and the cancellation signal is as close to 180 degrees as possible. Furthermore, matching the input impedance to the cancelling impedance also ensures that the current through the input impedance matches the current through the cancelling impedance.
In a fifteenth possible implementation form of the integrated amplifier according to any of the fifth to fourteenth possible implementation forms, the integrated amplifier comprises a bias, wherein the cancellation transistor comprises a cancellation control terminal connected to the bias. This is the power supply for the base/gate of the transistor. The cancellation circuit is controlled using a collector and an emitter, and a predetermined bias signal is supplied to the cancellation control terminal.
In a sixteenth possible implementation form of the integrated amplifier according to the first aspect as such or any one of the first to fifteenth possible implementation forms of the first aspect, the integrated amplifier comprises a second power supply and a load connected between the second power supply and the output. The load ensures a possible voltage swing on the output.
According to a second aspect of the present invention, there is provided a communication device for a wireless communication system, the communication device comprising an integrated amplifier according to the first aspect or any one of the first to sixteenth possible implementations of the first aspect.
Drawings
FIG. 1 illustrates an integrated amplifier provided by an embodiment of the present invention;
fig. 2 shows an integrated amplifier provided by an embodiment of the present invention, providing one possible implementation of the integrated amplifier schematically shown in fig. 1;
FIG. 3a shows one possible implementation of the cancellation circuit in the integrated amplifier shown in FIG. 2 in more detail;
FIG. 3b shows one possible implementation of the cancellation circuit in the integrated amplifier shown in FIG. 2 in more detail;
fig. 4 shows a simplified diagram of the cancellation of the cross-tuning of the amplified input signal Samp;
fig. 5 schematically shows a communication device in a wireless communication system.
Detailed Description
The embodiment will be described below. In the following description of the embodiments, similar features in different embodiments will be denoted by the same reference numerals.
Fig. 1 illustrates an integrated amplifier 100 provided by an embodiment of the present invention. The integrated amplifier 100 includes: an input 102 for receiving an input signal Sin; an output terminal 104 for outputting an output signal Sout; an amplification circuit 106 including an amplification output 112 and an amplification control input 168; and a cancellation circuit 114 including a cancellation output 124 and a cancellation input 116. The signals at the amplification output 112 and the cancellation output 124 are added to generate the signal Sout on the output 104. Both the amplification control input 168 and the cancellation input 116 are connected to the input 102. The amplifying circuit 106 is configured to provide an amplified input signal Samp at the amplifying output 112 based on the input signal Sin. The amplified input signal Samp includes a fundamental tone and a intermodulation tone. The cancellation circuit 114 is configured to provide a cancellation signal Sc based on the input signal Sin, wherein the cancellation signal Sc includes a fundamental tone and a cross-tone. The integrated amplifier 100 is configured to provide the output signal Sout as a sum of the amplified input signal Samp and the cancellation signal Sc. Therefore, the cross-tuning of the amplified input signal Samp is attenuated by the cross-tuning of the cancellation signal Sc.
Fig. 2 shows an integrated amplifier 100 provided by an embodiment of the present invention. The integrated amplifier 100 shown in fig. 2 provides one possible implementation of the integrated amplifier 100 shown in fig. 1. The integrated amplifier 100 includes: an input 102 for receiving an input signal Sin; an output terminal 104 for outputting an output signal current Sou; an amplification circuit 106 comprising an amplification output 112 and an amplification input 110; and a cancellation circuit 114 including a cancellation output 124 and a cancellation input 116. The amplification output 112 and the cancellation output 124 are both connected to the output 104, and the amplification control input 168 and the cancellation input 116 are both connected to the input 102. The amplifying circuit 106 is configured to provide an amplified input signal current Samp at the amplifying output 112 based on the input signal Sin. The current in the form of the amplified input signal Samp comprises a fundamental tone and a cross-tone. The amplification circuit 106 includes a single amplification transistor 128 as shown in fig. 2. The amplifying transistor 128, which in the example is realized as a field effect NPN transistor 128, comprises an amplifying input terminal 120 (emitter) connected to the amplifying input terminal 110 and an amplifying output terminal 122 (collector) connected to the amplifying output terminal 112 (base). The amplifying transistor further comprises an amplification control terminal 108 connected to the input terminal 102 via the amplification control terminal 168. Fig. 2 is simplified to show only the most critical components. Other components may be added to the main amplifier. There may also be other components between the input 102 and the amplification control terminal 108. Of course, instead of using only a single amplifying transistor 128, a plurality of cascade-coupled transistors may also be used in the amplifying circuit 106. Alternatively, a transistor of another technology may be used instead of the field effect transistor 128.
The cancellation circuit 114 is configured to provide a current in the form of a cancellation signal Sc based on the input signal Sin, wherein the current in the form of the cancellation signal Sc comprises a fundamental tone and a cross-tone. The integrated amplifier 100 is used to provide a current in the form of the output signal Sout at the output 104. The output signal Sout is the sum of the current in the form of the amplified input signal Samp and the current in the form of the cancellation signal Sc. Thus, the cross-tuning of the amplified input signal Samp is attenuated by the cross-tuning of the cancellation signal Sc, and the output signal Sout (assuming complete cancellation) will contain only pitch. The integrated amplifier 100 includes an input impedance 148 and a first power supply 156, which may be a ground plane or ground connection. The input impedance 148 is connected between the amplification input 110 and the first power supply 156. The integrated amplifier 100 further comprises a second power supply 162 and a load 164 connected between the second power supply 162 and the output 104, wherein the load 164 primarily functions to swing the voltage at the output 104, the second power supply 162 is a voltage supply, and the load 164 may be a resistive load, an inductive load, or a combination of resistive and inductive loads. The output signal Sout will flow through the load 164 and will generate a voltage on the output 104.
Fig. 3a shows in more detail one possible implementation of the cancellation circuit 114 in the embodiment shown in fig. 2. Fig. 3b shows another possible implementation of the cancellation circuit 114 in the integrated amplifier shown in fig. 2 in more detail.
As shown in fig. 3a and 3b, the cancellation circuit 114 comprises a cancellation transistor 130 and a cancellation output terminal 124, wherein the cancellation circuit 114 is configured to output a current in the form of the cancellation signal Sc at the cancellation output terminal 124. The cancellation circuit 114 also includes a cancellation input 116, a cancellation impedance 132, and a current source 136. Preferably, the current source 136 is programmable so that the amplification circuit 106 can be tuned during operation. The cancellation transistor 130 comprises a cancellation input terminal 140 and a cancellation output terminal 142, wherein the cancellation output terminal 142 is connected to the cancellation output 124, the cancellation input terminal 140 is connected to the current source 136, and the cancellation input terminal 140 is connected to the cancellation input 116 via the cancellation impedance 132. The cancelling impedance 132 comprises a resistor 150 in series with a capacitor 152. Preferably, at least one of the resistor 150 and the capacitor 152 is programmable to tune the amplification circuit 106 during operation of the integrated amplifier. The integrated amplifier 100 further comprises a bias 166, wherein the cancellation transistor 130 comprises a cancellation control terminal 146 connected to the bias 166. Thus, the cancellation control terminal 146 is not actively used to control the cancellation transistor 130, but is merely used to properly bias the cancellation transistor 130.
The integrated amplifier 100 may comprise an impedance buffer 160 (fig. 3b) connected between the input 102 and the cancellation input 116. The impedance buffer 160, for example in the form of a buffer amplifier, ensures that the impedance seen from the input 102 towards the cancellation circuit 114 is very high. Therefore, the influence of the cancellation circuit 114 introduced via the impedance buffer 160 on the integrated amplifier 100 is minimal compared to the case where the cancellation circuit 114 is not present.
The current source 136 may include a cancellation power supply 158 and a power supply resistor 154 as shown in fig. 3b, wherein the power supply resistor 154 is connected between the cancellation power supply 158 and the cancellation input terminal 140. The cancellation power supply 158 is a voltage power supply, and the cancellation power supply 158 and the power supply resistor 154 provide a simple implementation of the current source 136.
In order to ensure that the cancellation circuit 114 provides a cancellation signal Sc that effectively attenuates the intermodulation of the amplified input signal Samp, it is highly advantageous if the frequency characteristics of the cancellation transistor 130 and the frequency characteristics of the amplification transistor 128 are matched as closely as possible in terms of intermodulation. In order to achieve such matching in the frequency characteristics, it is preferable that the cancel transistor 130 is of the same type as the amplification transistor 128. Further, preferably, the cancellation transistor 130 is matched with the amplification transistor 128 in at least one of: the temperature during operation, the current density during operation, and the manufacturing process, i.e., the manufacturing process of the cancellation transistor 130 are preferably the same as the manufacturing process of the amplification transistor 128.
In order to attenuate the intermodulation of the amplified input signal current Samp as effectively as possible, not only should the frequency characteristics of the cancellation transistor 130 match the frequency characteristics of the amplification transistor 128 in terms of intermodulation, but also the phase of the cancellation signal current Sc should be opposite to the phase of the amplified input signal current Samp.
For best performance, the attenuation of the intermodulation of the amplified input signal Samp should be equal to the total cancellation, while the attenuation of the fundamental tone of the amplified input signal Samp should be as small as possible. To achieve this goal, the following design rules may be defined: a first ratio being a magnitude of a pitch of the cancellation signal Sc divided by a magnitude of a cross-tuning of the cancellation signal Sc, a second ratio being a magnitude of a pitch of the amplified input signal Samp divided by a magnitude of a cross-tuning of the amplified input signal Samp, wherein the second ratio is greater than the first ratio; preferably, the amplitude of the cross-tuning of the cancellation signal Sc should be substantially equal to the amplitude of the cross-tuning of the amplified signal Samp.
The desired relationship between the amplitude of the mutually tuned fundamental tones of the amplified input signal Samp and the cancellation signal Sc and the amplitude of the fundamental tones is achieved by appropriate evaluation of the magnitudes of the impedances of the integrated amplifier 100, i.e. of the cancellation impedance 132 and the input impedance 148 and of the current densities in the amplifying transistor 128 and the cancellation transistor 130.
Fig. 4 shows a simplified diagram of a typical test case illustrating the cross-tuning cancellation of the current in the form of an amplified input signal Samp.
The operation of the integrated amplifier 100 will now be described with reference to fig. 2, 3 and 4.
When an input signal Sin is applied at the input 102 of the integrated amplifier 100, a current will be generated through the input impedance 148. The current Sin/Z148 will flow through the amplified input 110 to the amplified output 112, where Z148 is the impedance of the input impedance 148. When the current Sin/Z148 flows through the transistor 128 to the amplified output 112, a cross-tuning will result. The sum of the current from the amplifying output 112 and the current from the cancelling output 124 will flow through the impedance Z164 and produce a voltage at the output 104, where Z164 is the impedance of the load 164.
The input signal Sin will also generate a voltage across the cancelling impedance 132. At the input of the cancellation circuit 114, the voltage across the cancellation impedance 132 will generate an AC current iinSin/Z132, where Z132 is the value of the cancellation impedance 132. The AC current iinAnd a constant DC current I1 from the current source 136 will be summed at the cancellation input terminal 140, which will serve as a virtual ground and current summing point, with the sum equation I1Iin+i2. According to said equation, the current i2Can be described as i2＝I1–iinAnd since I1 is a constant current, the AC current I2Will be equal to i2＝–iin＝–Sin/Z132。i2The opposite sign of (c) ensures that the current originating from the cancellation output 124 has the opposite phase to the input signal Sin. When the current i2The nonlinearity of the cancellation transistor 130 will mutually tune the cancellation signal current Sc when it flows through the cancellation transistor 130 to the cancellation output 124.
The nonlinearity of the cancellation transistor 130 may be varied by the size of the cancellation transistor 130, the size of the cancellation impedance 132, and the current of the current source 136. In general, the linearity of a (field effect) transistor depends on the voltage VCE across the collector and emitter and the bias current under bias conditions. The linearity is generally optimal if the AC current is small compared to the DC bias current. The real part of the cancellation impedance 132, i.e. the size of the cancellation resistor 150, is changed by iinAC size of (d). Since the linearity of the cancellation transistor 130 depends on the DC bias currents I1 and IinThe AC magnitude of the cancellation impedance 132, i.e., the magnitude of the cancellation resistor 150 and I1 may all be used to set the desired linearity of the cancellation transistor 130. If the real part of the cancellation impedance 132, i.e., the magnitude of the cancellation resistor 150, is changed while keeping I1 unchanged, the fundamental, second order, and third order cross-tuning of the cancellation signal Sc will change accordingly. However, if I1 is changed, but the real part of the cancellation impedance 132, i.e., the size of the cancellation resistor 150, remains the same, most of the second and third order cross-tones in the cancellation signal Sc will change, while the fundamental tone of the cancellation signal Sc remains more or less stable. If the VCE of the transistor is changed, the effect will be more or less the same. The imaginary value of the cancelling impedance 132, i.e. the size of the cancelling capacitor 152, will vary i with respect to the input signal Sin2The phase of the spectrum of (a).
At the output 104 of the integrated amplifier 100, a current in the form of the amplified input signal Samp is added to a current in the form of the cancellation signal SC. Since the phase of the cancellation signal Sc is opposite to the phase of the amplified input signal Samp, as described above, the addition of signals corresponds to the subtraction of the cancellation signal Sc from the amplified input signal Samp.
As described above, fig. 4 shows a simplified diagram of the cancellation of the intermodulation of the amplified input signal Samp. Fig. 4a shows the frequency spectrum of the current of the amplified input signal Samp with two test tones as input signal Sin. The cross-tuning of the current in the form of the amplified input signal Samp is denoted Im in fig. 4a and the fundamental tone of the current of the amplified input signal Samp is denoted F. Fig. 4b shows a frequency spectrum of the current in the form of the cancellation signal Sc. As described above, the sign of the spectrum of the cancelled signal Sc is opposite to the sign of the spectrum of the amplified input signal Samp. The cross-tuning of the current in the form of the cancellation signal Sc is denoted Im 'in fig. 4b and the pitch of the current in the form of the cancellation signal Sc is denoted F'. It is noted that the fundamental tone F 'of the current in the form of the cancellation signal Sc is very low, while the cross-tone IM' of the current in the form of the cancellation signal Sc matches the cross-tone in the amplified input signal Samp. The linearity of the cancellation circuit 114 is chosen to be low to avoid excessively reducing the pitch F of the amplified input signal. The sum of the current of the amplified input signal Samp and the current of the cancellation signal Sc is actually the subtraction of the cancellation signal Sc from the amplified input signal Samp as described above. This will result in the output signal Sout shown in fig. 4c having only two pitches F ". It should be noted that fig. 4 shows the sum of the currents, and Sout in fig. 4c corresponds to the current that generates the output voltage when the current flows through the load 164.
It should be noted that since both the amplifying transistor 128 and the cancelling transistor 130 have current outputs, the addition of the amplified input signal Samp and the cancelling signal Sc does not necessarily have to be performed directly on the outputs as shown in the figure. The summing point can be varied in a number of different ways by different configurations of the cascode.
Fig. 5 schematically shows a communication device 300 in a wireless communication system 200. The communication device 300 includes the integrated amplifier 100 provided by the embodiment of the present invention. The wireless communication system 200 further comprises a network node 400 comprising a node wireless transceiver 402. The dashed arrow a1 represents a transmission from the communication device 300 to the network node 400, which is commonly referred to as an upstream transmission. The solid arrow a2 represents a transmission from the network node 400 to the communication device 300, which is commonly referred to as a downlink transmission.
The communication device 300 may be any one of a User Equipment (UE), a Mobile Station (MS), a wireless terminal, or a mobile terminal in Long Term Evolution (LTE) capable of performing wireless communication in a wireless communication system, which is sometimes referred to as a wireless cellular system. The UE may also be referred to as a mobile phone, a cellular phone, a tablet, or a laptop computer with wireless capabilities. A UE herein may be, for example, a portable, pocket, hand-held, computer-included, or vehicle-mounted mobile device capable of communicating voice or data with another entity, such as another receiver or server, via a radio access network. The UE may be a Station (STA), which is any device including an interface connected to a Wireless Medium (WM) and meeting the requirements of Media Access Control (MAC) and physical layer (PHY) of IEEE 802.11.
The radio network nodes may be classified into different categories, such as macro eNodeB, home eNodeB or pico base station, based on transmit power and cell size. The wireless network node may be a Station (STA), which is any device including an interface connected to a Wireless Medium (WM) and meeting the requirements of Media Access Control (MAC) and physical layer (PHY) of IEEE 802.11.
Claims (17)
1. An integrated amplifier (100), comprising:
an input (102) for receiving an input signal (Sin);
an impedance buffer (160);
an output (104) for outputting an output signal (Sout);
an amplification circuit (106); and
a cancellation circuit (114); wherein the amplification circuit (106) is configured to provide an amplified input signal (Samp) based on the input signal (Sin), wherein the amplified input signal (Samp) comprises a fundamental tone and a cross-tone;
-the cancellation circuit (114) is configured to provide a cancellation signal (Sc) based on the input signal (Sin), wherein the cancellation signal (Sc) comprises a pitch and a cross-tune; -the integrated amplifier (100) is configured to provide the output signal (Sout) based on a sum of the amplified input signal (Samp) and the cancellation signal (Sc) such that a cross-tuning of the amplified input signal (Samp) is attenuated by a cross-tuning of the cancellation signal (Sc);
the impedance buffer (160) is connected between the input terminal (102) and an input terminal of the cancellation circuit (114), the impedance buffer (160) being configured to increase an impedance of the input terminal (102) to the cancellation circuit (114).
2. The integrated amplifier (100) of claim 1, wherein the phase of the cancellation signal (Sc) is opposite to the phase of the amplified input signal (Samp).
3. The integrated amplifier (100) of claim 2,
-a first ratio is the amplitude of the pitch of the cancellation signal (Sc) divided by the amplitude of the intermodulation tone of the cancellation signal (Sc);
-a second ratio is the amplitude of the fundamental tone of the amplified input signal (Samp) divided by the amplitude of the intermodulation tone of the amplified input signal (Samp);
wherein the second ratio is greater than the first ratio.
4. An integrated amplifier (100) as claimed in claim 3, characterized in that the amplitude of the cross-tuning of the cancellation signal (Sc) is of the same magnitude as the amplitude of the cross-tuning of the amplified input signal (Samp).
5. The integrated amplifier (100) of any of the preceding claims, wherein the cancellation circuit (114) comprises a cancellation transistor (130) and a cancellation output (124);
wherein the cancellation circuit (114) is configured to output the cancellation signal (Sc) on the cancellation output (124).
6. The integrated amplifier (100) of claim 5,
the cancellation circuit (114) comprises a cancellation input (116), a cancellation impedance (132), and a current source (136);
the cancellation transistor (130) comprises a cancellation input terminal (140) and a cancellation output terminal (142);
wherein the cancellation output terminal (142) is connected to the cancellation output (124);
the cancellation input terminal (140) is connected to the current source (136);
the cancellation input terminal (140) is connected to the cancellation input (116) via the cancellation impedance (132).
7. The integrated amplifier (100) of claim 6, wherein the current source (136) is programmable.
8. The integrated amplifier (100) of claim 6 or 7, wherein the current source (136) comprises a cancellation supply (158) and a supply resistor (154);
wherein the power supply resistor (154) is connected between the cancellation power supply (158) and the cancellation input terminal (140).
9. The integrated amplifier (100) of claim 6 or 7, wherein the cancelling impedance (132) comprises a resistor (150) in series with a capacitor (152).
10. The integrated amplifier (100) of claim 9, wherein at least one of the resistor (150) and the capacitor (152) is programmable.
11. The integrated amplifier (100) of claim 5, wherein the amplification circuit (106) comprises an amplification transistor (128);
wherein the cancellation transistor (130) is of the same type as the amplification transistor (128).
12. The integrated amplifier (100) of claim 11, wherein the cancellation transistor (130) is matched to the amplification transistor (128) in at least one of: temperature during operation, current density during operation, and manufacturing process.
13. The integrated amplifier (100) of any of claims 6-7, comprising an input impedance (148) and a first power supply (156);
wherein the amplification circuit (106) comprises an amplification input (110);
the input impedance (148) is connected between the amplification input (110) and the first power supply (156).
14. The integrated amplifier (100) of claim 13, wherein the input impedance (148) is matched to the cancellation impedance (132).
15. The integrated amplifier (100) of claim 5, comprising a bias (166), wherein the cancellation transistor (130) comprises a cancellation control terminal (146) connected to the bias (166).
16. The integrated amplifier (100) of claim 5, further comprising a second power supply (162) and a load (164) connected between the second power supply (162) and the output (104).
17. A communication device (300) for a wireless communication system (200), the communication device (300) comprising an integrated amplifier (100) according to any of the preceding claims.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/EP2016/070034 WO2018036627A1 (en) | 2016-08-25 | 2016-08-25 | Integrated amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109643973A CN109643973A (en) | 2019-04-16 |
| CN109643973B true CN109643973B (en) | 2022-05-13 |
Family
ID=56799473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680088735.1A Active CN109643973B (en) | 2016-08-25 | 2016-08-25 | Integrated amplifier |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109643973B (en) |
| WO (1) | WO2018036627A1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1201293A (en) * | 1997-01-31 | 1998-12-09 | 三星电子株式会社 | Linear power amplifier and method for eliminating intermodulation distortion signals |
| US6172564B1 (en) * | 1999-07-30 | 2001-01-09 | Eugene Rzyski | Intermodulation product cancellation circuit |
| KR20020009678A (en) * | 2000-07-26 | 2002-02-02 | 윤종용 | Receive circuit using intermodulation filter in mobile communication set |
| CN1531776A (en) * | 2000-11-03 | 2004-09-22 | �����ɷ� | Circuit for linearizing electronic devices |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6781467B2 (en) * | 2003-01-24 | 2004-08-24 | Qualcomm Incorporated | High linearity low noise amplifier |
| ATE447257T1 (en) * | 2004-02-17 | 2009-11-15 | Ericsson Telefon Ab L M | DYNAMIC BIASED AMPLIFIER |
| KR100631973B1 (en) * | 2005-03-02 | 2006-10-11 | 삼성전기주식회사 | Variable gain broadband amplifier |
| FI20055401A0 (en) * | 2005-07-11 | 2005-07-11 | Nokia Corp | Improvements in integrated RF circuits |
| KR100829780B1 (en) * | 2007-02-27 | 2008-05-16 | 삼성전자주식회사 | Low noise amplifier with improved iip3 and methods thereof |
| KR101400862B1 (en) * | 2007-09-19 | 2014-05-28 | 삼성전자주식회사 | Apparatus and method for low noise amplify in wireless communication system |
| US7936220B2 (en) * | 2008-12-12 | 2011-05-03 | Qualcomm, Incorporated | Techniques for improving amplifier linearity |
| US8373503B1 (en) * | 2011-12-12 | 2013-02-12 | Linear Technology Corporation | Third order intermodulation cancellation for RF transconductors |
-
2016
- 2016-08-25 CN CN201680088735.1A patent/CN109643973B/en active Active
- 2016-08-25 WO PCT/EP2016/070034 patent/WO2018036627A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1201293A (en) * | 1997-01-31 | 1998-12-09 | 三星电子株式会社 | Linear power amplifier and method for eliminating intermodulation distortion signals |
| US6172564B1 (en) * | 1999-07-30 | 2001-01-09 | Eugene Rzyski | Intermodulation product cancellation circuit |
| KR20020009678A (en) * | 2000-07-26 | 2002-02-02 | 윤종용 | Receive circuit using intermodulation filter in mobile communication set |
| CN1531776A (en) * | 2000-11-03 | 2004-09-22 | �����ɷ� | Circuit for linearizing electronic devices |
Non-Patent Citations (2)
| Title |
|---|
| "A 20 GHz power amplifier with IM3 distortion cancellation by load-split derivative superposition";Kun-Yao Kao等;《2016 IEEE MTT-S International Microwave Symposium (IMS)》;20160811;1-4 * |
| "一种基于五类线的远端微功率模块的研究与设计";汪锋;《中国优秀博硕士学位论文全文数据库(硕士) 信息科技辑》;20150515;I136-623 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2018036627A1 (en) | 2018-03-01 |
| CN109643973A (en) | 2019-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8548390B2 (en) | Method and system for transmitter output power compensation | |
| US9203347B2 (en) | Envelope tracking apparatus and method | |
| US6943628B2 (en) | Methods and apparatus for substantially reducing nonlinear distortion | |
| JP6117421B2 (en) | Techniques to reduce harmonic distortion of impedance attenuators for low power broadband high resolution DACs | |
| TW201008110A (en) | Method of achieving high selectivity in receiver RF front-ends | |
| EP2106021B1 (en) | Converting circuit for converting differential signal to single-ended signal | |
| US10715203B2 (en) | Wireless transceiver capable of offsetting internal signal leakage | |
| CN109643973B (en) | Integrated amplifier | |
| JP5983968B2 (en) | Power amplification circuit and power amplification module | |
| US11228285B2 (en) | Power amplifier | |
| Dardaillon et al. | Adaptive digital pre-distortion for future wireless transmitters | |
| US10205473B2 (en) | Cartesian error-feedback transmitter architecture with a feedforward path | |
| KR20000005688A (en) | Amplifier and method of canceling distortion by combining hyperbolic tangent and hyperbolic sine transfer functions | |
| WO2020103450A1 (en) | Programmable on-chip self-calibrating balanced attenuator | |
| Al-Shaikhli et al. | Integrated of low noise amplifier and notch filter for wireless communications | |
| Janssen | Methodologies for multi-radio coexistence: Self-interference suppression techniques | |
| Logvinov et al. | Technical Indicators of Devices for Signal Reception and Processing | |
| Syed Ameer Abbas et al. | Design and Analysis of 1–3 GHz Wideband LNA Using ADS | |
| Watkins et al. | Flexible linearity profile low noise feedforward amplifiers for improving channel capacity | |
| JP2015231056A (en) | Power amplification apparatus | |
| KR20210101852A (en) | Power Amplifier | |
| van Bezooijen et al. | Adaptive RF Front-Ends | |
| Debaillie et al. | DUPLO Deliverable D2. 3.2 | |
| Kulkarni et al. | Intermodulation Distortion |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |