CN109638956B

CN109638956B - Power supply switching circuit

Info

Publication number: CN109638956B
Application number: CN201811623299.0A
Authority: CN
Inventors: 李雷波; 刘强
Original assignee: Swit Electronics Co Ltd
Current assignee: Swit Electronics Co Ltd
Priority date: 2018-12-28
Filing date: 2018-12-28
Publication date: 2024-02-23
Anticipated expiration: 2038-12-28
Also published as: CN109638956A

Abstract

The invention discloses a power supply switching circuit which comprises a first switch, a third switch, a fourth switch, a first self-locking anti-backflow circuit, a first interlocking circuit and a first interlocking anti-backflow circuit, wherein the first self-locking anti-backflow circuit is connected with the first interlocking circuit; the input ends of the first switch, the first interlocking circuit and the first interlocking backflow preventing circuit are respectively used for being connected with a power supply A; the input ends of the third switch and the first interlocking circuit are respectively connected with a power supply B, the output end of the third switch is respectively connected with the first self-locking backflow-preventing circuit and the fourth switch, and the output end of the fourth switch and the output end of the first switch are connected with the power supply output; the output end of the first self-locking backflow preventing circuit is connected with the first switch, the output end of the first interlocking circuit is connected with the third switch, and the output end of the first interlocking backflow preventing circuit is connected with the fourth switch. The invention can solve the problem of power conflict of the monitor when the multi-path power supply is in power supply, has reverse protection function, simple circuit structure and good application prospect.

Description

Power supply switching circuit

Technical Field

The invention relates to the field of video shooting equipment, in particular to a power supply switching circuit capable of automatically switching according to priority.

Background

Currently, in use, monitors in the field of film and television shooting generally adopt two power supply modes: the external DC power supply and the battery buckle power supply only need to consider the switching and protection of the two paths of power supplies in actual use.

Along with market demands, the 4K monitor starts to enter the market, and accordingly power of the monitor is increased, in order to ensure reliable operation of the monitor, a power supply mode of the monitor is changed into a built-in AC-DC module for supplying power by default, but an external DC power input interface and a battery buckle interface are also required to be provided for adapting to use environments of various users, so that three paths of power supplies of the monitor are switched and protected, and therefore, the previous design cannot meet requirements, and therefore, a new circuit design is required to meet use requirements.

Therefore, the application number is 2015108723569, and the Chinese patent with the patent name of "three-power supply automatic switching circuit" provides a technical scheme, and the technical scheme is that three paths of power supplies A/B/C judge the existence state of three paths of power supplies in a detection circuit 1, output detection signals 1 to a logic selection circuit, then power supplies B/C judge in a detection circuit 2, output detection signals 1 to a logic circuit, power supplies A/C judge in a detection circuit 3, output detection signals 3 to a logic circuit, the logic circuit analyzes the three detection signals and controls three independent switching circuits to output, so that the whole circuit system is complex, devices are numerous, and the design and understanding are not facilitated. In addition, the undervoltage/overvoltage protection circuit in the existing design is mostly completed by an operational amplifier circuit and a singlechip, and the operational amplifier circuit is often unstable in undervoltage/overvoltage value and has deviation. In the technical scheme of the singlechip, the singlechip is also required to be provided with a proper power supply, and an accurate and stable voltage value is required for reference, so that the singlechip is inconvenient to implement.

Disclosure of Invention

The invention aims to provide a power supply switching circuit with a simple structure, which realizes automatic switching of multiple paths of power supplies.

The technical scheme adopted by the invention is as follows: the power supply switching circuit comprises a first switch, a third switch, a fourth switch, a first self-locking anti-backflow circuit, a first interlocking circuit and a first interlocking anti-backflow circuit;

the input ends of the first switch, the first interlocking circuit and the first interlocking backflow preventing circuit are respectively used for being connected with a power supply A;

the input ends of the third switch and the first interlocking circuit are respectively connected with a power supply B, the output end of the third switch is respectively connected with the first self-locking backflow-preventing circuit and the fourth switch, and the output end of the fourth switch and the output end of the first switch are connected with the power supply output;

the output end of the first self-locking backflow preventing circuit is connected with the first switch, the output end of the first interlocking circuit is connected with the third switch, and the output end of the first interlocking backflow preventing circuit is connected with the fourth switch.

Preferably, the invention further comprises a second switch, a second self-locking anti-backflow circuit, a fifth switch, a sixth switch, a second interlocking circuit and a second interlocking anti-backflow circuit; the output end of the first switch is respectively connected with the second switch, the second interlocking circuit and the second interlocking backflow preventing circuit; the output end of the fourth switch is respectively connected with the second switch, the second interlocking circuit and the second interlocking backflow preventing circuit; the input ends of the fifth switch and the second interlocking circuit are respectively used for being connected with a power supply C, and the output end of the fifth switch is respectively connected with the sixth switch and the second self-locking backflow preventing circuit; the output end of the sixth switch and the output end of the second switch are connected with the power supply for output, and the output end of the fourth switch and the output end of the first switch are not directly connected with the power supply for output; the output end of the second self-locking backflow preventing circuit is connected with a second switch, the output end of the second interlocking circuit is connected with a fifth switch, and the output end of the second interlocking backflow preventing circuit is connected with a sixth switch.

Preferably, the first switch, the third switch, the fourth switch, the second switch, the fifth switch and the sixth switch are PMOS transistors.

Preferably, the first interlocking circuit comprises resistors R1, R2, R3, R4, and transistors Q1, Q2; one end of the resistor R1 is used for being connected with the power supply A, the other end of the resistor R1 is respectively connected with the resistor R2 and the base electrode of the triode Q1, and the other end of the resistor R2 and the emitter electrode of the triode Q1 are grounded; the collector of triode Q1 connects one end of resistance R3 and the base of triode Q2 respectively, and the other end of resistance R3, the one end of resistance R4 are used for connecting power B respectively, and the other end of resistance R4, third switch are connected with triode Q2's collector, and triode Q2's projecting pole ground.

Preferably, the first self-locking anti-backflow circuit comprises a resistor R5 and diodes D1 and D2, one end of the resistor R5 is connected with the first switch, the other end of the resistor R5 is connected with the positive electrode of the diode D1, the negative electrode of the diode D1 is connected with the negative electrode of the diode D2, the positive electrode of the diode D2 is grounded, and the output of the third switch is connected between the resistor R5 and the positive electrode of the diode D1.

Preferably, the first interlocking anti-backflow circuit comprises resistors R6, R7 and a diode D3; the positive electrode of the diode D3 is used for being connected with the power supply A, and the negative electrode of the diode D3 is divided

One end of the resistor R6 and one end of the resistor R7 are connected respectively, the other end of the resistor R6 is connected with the fourth switch, and the other end of the resistor R7 is grounded.

Preferably, the second interlocking circuit comprises resistors R15, R16, R17, R18, and transistors Q3, Q4; one end of the resistor R15 is connected with the output end of the first switch and the output end of the fourth switch, the other end of the resistor R15 is respectively connected with the resistor R16 and the base electrode of the triode Q3, and the other end of the resistor R16 and the emitter electrode of the triode Q3 are grounded; the collector of the triode Q3 is respectively connected with one end of a resistor R17 and the base of the triode Q4, the other end of the resistor R17 and one end of a resistor R18 are respectively connected with a power supply C, the other end of the resistor R18 and a fifth switch are connected with the collector of the triode Q4, and the emitter of the triode Q4 is grounded.

Preferably, the second self-locking anti-backflow circuit comprises a resistor R19, diodes D4 and D5, one end of the resistor R19 is connected with the second switch, the other end of the resistor R19 is connected with the positive electrode of the diode D4, the negative electrode of the diode D4 is connected with the negative electrode of the diode D5, the positive electrode of the diode D5 is grounded, and the output of the fifth switch is connected between the resistor R19 and the positive electrode of the diode D4.

Preferably, the second interlocking anti-backflow circuit comprises resistors R20, R21 and a diode D6; the output end of the first switch and the output end of the fourth switch are connected with the positive electrode of a diode D6, the negative electrode of the diode D6 is respectively connected with one end of a resistor R20 and one end of a resistor R21, the other end of the resistor R20 is connected with a sixth switch, and the other end of the resistor R21 is grounded.

Preferably, the system further comprises a seventh switch, a sampling circuit and an undervoltage and overvoltage protection circuit; the output end of the first switch and the output end of the fourth switch are connected with the seventh switch and the input end of the sampling circuit, the undervoltage and overvoltage protection is respectively connected with the output end of the sampling circuit and the seventh switch, the seventh switch is connected with the power supply output, or the output end of the second switch and the output end of the sixth switch are connected with the seventh switch and the input end of the sampling circuit, the undervoltage and overvoltage protection is respectively connected with the output end of the sampling circuit and the seventh switch, and the seventh switch is connected with the power supply output.

Preferably, the seventh switch is a double NMOS transistor.

Compared with the prior art, the invention has the beneficial effects that: (1) The circuit is completely compatible with two-path power supply switching, can be directly used in circuit design, does not need to replace devices, and improves the universality of the circuit. (2) Each power supply has the function of reverse connection prevention, so that a post-stage circuit is better protected. (3) The circuit has the undervoltage/overvoltage protection function and prevents the abnormal operation of the subsequent circuit caused by voltage problems.

Drawings

FIG. 1 is a circuit block diagram of the present invention;

FIG. 2 is a schematic diagram of the simultaneous power A/B/C operation of the present invention;

FIG. 3 is a schematic diagram showing the simultaneous operation of the power supplies A/B of the present invention;

FIG. 4 is a schematic diagram of the simultaneous power A/C operation of the present invention;

FIG. 5 is a schematic diagram showing the operation of the power supply A of the present invention;

FIG. 6 is a schematic diagram of the simultaneous power B/C operation of the present invention;

FIG. 7 is a schematic diagram showing the operation of the power supply B of the present invention;

FIG. 8 is a schematic diagram showing the operation of the power supply C of the present invention;

FIG. 9 is a schematic diagram of the operation of the present invention in which the power supplies A/B/C are present at the same time, but the voltages are unsafe voltages;

FIG. 10 is a schematic diagram of the reverse operation of the power supply B of the present invention;

FIG. 11 is a schematic diagram of a two-stage circuit with only power source A, B;

fig. 12 is a circuit diagram of the interlock circuit 1 of the present invention;

fig. 13 is a circuit diagram of the self-locking anti-backflow circuit 1 of the present invention;

fig. 14 is a circuit diagram of the interlocking anti-backflow circuit 1 of the present invention;

fig. 15 is a circuit diagram of the interlock circuit 2 of the present invention;

FIG. 16 is a circuit diagram of the self-locking anti-backflow circuit 2 of the present invention;

fig. 17 is a circuit diagram of the interlock anti-backflow circuit 2 of the present invention;

FIG. 18 is a circuit diagram of a sampling circuit of the present invention;

fig. 19 is a circuit diagram of an under/over voltage protection circuit of the present invention.

Detailed Description

The invention is further described below in connection with specific embodiments.

The priority of the power supply is shown in table 1:

TABLE 1

When the power supply a exists, the power supply B, C is turned off and only the power supply a is output, irrespective of the presence or absence of the power supply B, C.

When the power supply A does not exist, the user checks whether the power supply B exists at the moment, and if the power supply B exists, the power supply C is turned off no matter whether the power supply C exists or not, and only the power supply B is output.

When none of the power sources A, B exists, the power source C is directly output if the power source C exists.

I.e. the priority of the power supply is: power supply a > power supply B > power supply C. In actual use, the power supply with the highest priority is connected to the power supply A of the drawing, the power supply with the next priority is connected to the power supply B, and the power supply with the lowest priority is connected to the power supply C.

The invention is especially suitable for power supply management of the monitor, and has the condition of three power supply inputs in the use of the monitor, at the moment, the built-in AC-DC power supply is the power supply A, the priority is highest, the external DC is the power supply B, the priority is inferior, the battery buckle plate input is the power supply C, and the priority is lowest, so that when the power supply A exists, the power supply of the power supply B/C is effectively reserved, and the trouble of no power supply of the direct current power supply caused by using the power supply B/C is avoided. The invention is also applicable to switching among other multipath power supplies.

As shown in FIG. 1, the power supply switching circuit provided by the invention comprises a plurality of switches, wherein the switches in FIG. 1 have two specific forms, one of the switches adopts a PMOS tube as a switch, and the other switch adopts a double NMOS tube as a switch. Specifically, the invention comprises a first PMOS tube (PMOS 1), a second PMOS tube (PMOS 2), a third PMOS tube (PMOS 3), a fourth PMOS tube (PMOS 4), a fifth PMOS tube (PMOS 5) and a sixth PMOS tube (PMOS 6), wherein the first self-locking backflow preventing circuit (self-locking backflow preventing circuit 1), the second self-locking backflow preventing circuit (self-locking backflow preventing circuit 2), the first interlocking circuit (interlocking circuit 1), the second interlocking circuit (interlocking circuit 2), the first interlocking backflow preventing circuit (interlocking backflow preventing circuit 1) and the second interlocking backflow preventing circuit (interlocking backflow preventing circuit 2);

the power supply A is respectively connected with a first PMOS tube, a first interlocking circuit and a first interlocking backflow preventing circuit, the output end of the first interlocking circuit is connected with a third PMOS tube, the output end of the first interlocking backflow preventing circuit is connected with a fourth PMOS tube, the output end of the first PMOS tube is respectively connected with a second PMOS tube, a second interlocking circuit and a second interlocking backflow preventing circuit, the output end of the second interlocking circuit is connected with a fifth PMOS tube, and the output end of the second interlocking backflow preventing circuit is connected with a sixth PMOS tube; the power supply B is connected with a third PMOS tube and a first interlocking circuit, the output end of the third PMOS tube is respectively connected with a first self-locking backflow-preventing circuit and a fourth PMOS tube, the output end of the first self-locking backflow-preventing circuit is connected with the first PMOS tube, and the output end of the fourth PMOS tube is respectively connected with a second PMOS tube, a second interlocking circuit and a second interlocking backflow-preventing circuit; the power supply C is connected with the fifth PMOS tube and the second interlocking circuit, the output end of the fifth PMOS tube is respectively connected with the sixth PMOS tube and the second self-locking backflow-preventing circuit, and the output end of the second self-locking backflow-preventing circuit is connected with the second PMOS tube. The output end of the second PMOS transistor is connected to a load (not shown in the figure) after being connected to the output end of the sixth PMOS transistor.

In order to enhance the safety of the circuit, the invention also provides a double NMOS tube (as a switch, other devices can be replaced), a sampling circuit and an undervoltage and overvoltage protection circuit, wherein the output end of the second PMOS tube and the output end of the sixth PMOS tube are connected with the double NMOS tube, the output end of the double NMOS tube is connected with a load, one end of the sampling circuit is connected with the outputs of the PMOS2 and the PMOS6 to sample the voltage entering the double NMOS tube, the other end of the sampling circuit is connected with the undervoltage and overvoltage protection circuit, and the undervoltage and overvoltage protection circuit is also connected with the double NMOS tube.

As shown in fig. 2-5, when power supply a is present, whether power supply B and C are present or neither is present, power supply a is preferentially selected for power supply, and if power supply B or C is present, power supply B or C needs to be turned off, and PMOS transistors are turned off by interlocking anti-backflow circuits, preventing voltage backflow.

As shown in fig. 2, when the power source A, B, C exists simultaneously, the power source a respectively signals the first interlocking circuit and the first interlocking backflow preventing circuit to turn off the third PMOS transistor and the fourth PMOS transistor, and simultaneously respectively signals the second interlocking circuit and the second interlocking backflow preventing circuit through the first PMOS transistor to turn off the fifth PMOS transistor and the sixth PMOS transistor, so as to turn off the output of the power source B and the power source C, and simultaneously prevent the voltage from flowing backward.

As shown in fig. 3, when only the power supplies a and B are present, the power supply a signals the first interlock circuit and the first interlock backflow preventing circuit to turn off the third PMOS transistor and the fourth PMOS transistor, respectively, while a signal is given to the second interlock backflow preventing circuit through the first PMOS transistor to turn off the sixth PMOS transistor to turn off the output of the power supply B and simultaneously prevent the voltage backflow to the power supplies B and C.

As shown in fig. 4, when the power supplies a and C exist, the power supply a gives a signal to the first interlocking anti-backflow circuit to turn off the fourth PMOS transistor, and simultaneously gives signals to the second interlocking circuit and the second interlocking anti-backflow circuit through the first PMOS transistor to turn off the fifth PMOS transistor and the sixth PMOS transistor, respectively, to turn off the output of the power supply C, and simultaneously prevent the voltage backflow to the power supplies B and C.

As shown in fig. 5, when only the power supply a exists, the power supply a gives a signal to the first interlocking anti-backflow circuit to turn off the fourth PMOS transistor, and simultaneously gives a signal to the second interlocking anti-backflow circuit to turn off the sixth PMOS transistor through the first PMOS transistor, so that the voltage backflow to the power supplies B and C is prevented.

As shown in fig. 6, when the power supply a does not exist and the power supplies B and C exist at the same time, the power supply B is preferentially selected to supply power, the power supply B supplies a signal to the first self-locking anti-backflow circuit through the third PMOS tube, and the first self-locking anti-backflow circuit turns off the first PMOS tube to prevent the voltage of the power supply a from flowing backwards; meanwhile, the fourth PMOS tube respectively gives signals to the second interlocking circuit and the second interlocking backflow preventing circuit to respectively turn off the fifth PMOS tube and the sixth PMOS tube, turns off the output of the power supply C, and simultaneously prevents the backflow of the voltage of the power supply C.

As shown in fig. 7, when only the condition of the power supply B exists, the power supply B signals the first self-locking anti-backflow circuit through the third PMOS transistor, and the first self-locking anti-backflow circuit turns off the first PMOS transistor to prevent the voltage of the power supply a from flowing backwards; meanwhile, the fourth PMOS tube gives a signal to the second interlocking backflow preventing circuit to turn off the sixth PMOS tube, so that backflow of the voltage of the power supply C is prevented.

As shown in fig. 8, when only the power supply C exists, the power supply C provides a signal to the second self-locking anti-backflow circuit through the fifth PMOS transistor to turn off the second PMOS transistor, so as to prevent the voltage backflow of the power supplies a and B.

Meanwhile, as the demand of the 4K monitor is increasing, the display panel mostly adopts the V-BY-ONE signal, and the standard voltage of the V-BY-ONE is 12V, so when the power supply is lower than 12V, the problem of abnormal operation of the display panel exists, and the 4K display panel is expensive, so that the occurrence of the phenomenon needs to be avoided. As shown in FIG. 9, the undervoltage and overvoltage protection in the design of the invention plays a role in protection, the configuration resistor in the sampling circuit is configured to be lower than 12V to be turned off, and when the sampling voltage of the sampling circuit is abnormal, the undervoltage and overvoltage protection circuit turns off the double NMOS tubes, so that the problem of too low voltage can not occur during power supply, and the display screen panel is protected.

The invention adds reverse connection protection in the design, thus ensuring the safety of the equipment and reducing unnecessary loss. As shown in fig. 10, after the power supply B is reversely connected, the positive electrode cannot reach the negative electrode of the power supply through the first interlocking circuit and the first interlocking backflow preventing circuit, the first interlocking circuit and the first interlocking backflow preventing circuit do not work, the third PMOS tube and the fourth PMOS tube cannot be opened, the main circuit cannot form a loop, and the power supply and the rear-stage circuit can normally work in the reverse connection state. The same reverse connection prevention function is also applicable to the power supplies a and C.

As shown in fig. 11, the invention is also applicable to the switching between two power supplies, the power supply a is respectively connected with the PMOS1, the interlocking circuit 1 and the interlocking backflow preventing circuit 1, the output end of the interlocking circuit 1 is connected with the PMOS3, the output end of the interlocking backflow preventing circuit 1 is connected with the PMOS4, the power supply B is respectively connected with the PMOS3 and the interlocking circuit 1, the output end of the PMOS3 is respectively connected with the PMOS4 and the self-locking backflow preventing circuit 1, the output end of the self-locking backflow preventing circuit 1 is connected with the PMOS1, the output end of the PMOS1 and the output end of the PMOS4 are respectively connected with the double NMOS, the sampling circuit is respectively connected with the input end of the double NMOS and the undervoltage and overvoltage protecting circuits, and the undervoltage and overvoltage protecting circuits are connected with the double NMOS. When the power source A, B is simultaneously present or only the power source A is provided, the priority of the power source A is high, the power source A turns off the PMOS3 and the PMOS4 through the interlocking circuit 1 and the interlocking anti-backflow circuit 1, and the PMOS1 is turned on. When only the power supply B is provided, the PMOS3 and the PMOS4 are conducted, and the self-locking anti-backflow circuit 1 enables the PMOS1 to be closed.

The structure of the interlock circuit 1 and the interlock circuit 2, and the structure of the interlock backflow preventing circuit 1 and the interlock backflow preventing circuit 2 are the same, and for the sake of clarity of description of the present invention, the following description will be given respectively.

As shown in fig. 12, the first interlocking circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a triode Q1 and a triode Q2, wherein one end of the resistor R1 is connected with a power supply a, the other end is respectively connected with the resistor R2 and the base electrode of the triode Q1, and the other end of the resistor R2 and the emitter electrode of the triode Q1 are grounded; the collector of the triode Q1 is respectively connected with one end of a resistor R3 and the base of the triode Q2, the other end of the resistor R3 and one end of a resistor R4 are respectively connected with a power supply B, and the collector of the triode Q2 is respectively connected with the other end of the resistor R4 and the grid G3 of the PMOS 3.

As shown in fig. 13, the first self-locking anti-backflow circuit includes a resistor R5, a diode D1, and a diode D2, wherein one end of the resistor R5 is connected to the gate G1 of the PMOS1, the other end is connected to the anode of the diode D1, the cathode of the diode D1 is connected to the cathode of the diode D2, the anode of the diode D2 is grounded, and the output PM3 of the PMOS3 is connected between the resistor R5 and the anode of the diode D1.

As shown in fig. 14, the first interlocking backflow preventing circuit includes a resistor R6, a resistor R7 and a diode D3, the power supply a is connected to the positive electrode of the diode D3, the negative electrode of the diode D3 is respectively connected to one end of the resistor R6 and one end of the resistor R7, the other end of the resistor R6 is connected to the gate G4 of the PMOS4, and the other end of the resistor R7 is grounded.

As shown in fig. 15, the second interlocking circuit includes a resistor R15, a resistor R16, a resistor R17, a resistor R18, a triode Q3 and a triode Q4, one end of the resistor R15 is connected with the output PM1 of the PMOS1, the other end is respectively connected with the resistor R16 and the base electrode of the triode Q3, and the other end of the resistor R16 and the emitter electrode of the triode Q3 are grounded; the collector of the triode Q3 is respectively connected with one end of a resistor R17 and the base of a triode Q4, the other end of a resistor R173 and one end of a resistor R18 are respectively connected with a power supply C, and the collector of the triode Q4 is respectively connected with the other end of the resistor R18 and the grid G5 of a PMOS 5.

As shown in fig. 16, the second self-locking anti-backflow circuit includes a resistor R19, a diode D4, and a diode D5, wherein one end of the resistor R19 is connected to the gate G2 of the PMOS2, the other end is connected to the anode of the diode D4, the cathode of the diode D4 is connected to the cathode of the diode D5, the anode of the diode D5 is grounded, and the output PM5 of the PMOS5 is connected between the resistor R19 and the anode of the diode D4.

As shown in fig. 17, the second interlocking anti-backflow circuit includes a resistor R29, a resistor R21 and a diode D6, the output PM1 of the PMOS1 is connected to the positive electrode of the diode D6, the negative electrode of the diode D6 is respectively connected to one end of a resistor R20 and one end of the resistor R21, the other end of the resistor R20 is connected to the gate G6 of the PMOS6, and the other end of the resistor R21 is grounded.

As shown in fig. 18, the sampling circuit includes a resistor R8, a resistor R9, and a resistor R10, where the resistor R8, the resistor R9, and the resistor R10 are sequentially connected in sequence, one end of the resistor R8 is connected to the output end of the second PMOS tube and the output end of the sixth PMOS tube, the under/over-voltage protection chip IC is connected between the resistor R8 and the resistor R9, and collects an under-voltage sampling value, the under/over-voltage protection chip IC is further connected between the resistor R9 and the resistor 10, and collects an over-voltage sampling value, and the other end of the resistor R10 is grounded.

As shown in fig. 19, the undervoltage/overvoltage protection circuit includes an undervoltage/overvoltage protection chip IC, a capacitor C1, a capacitor C2, a resistor R11, a resistor R12, a resistor R13, and a resistor R14, wherein one end of the capacitor C1 is grounded, the other end is respectively connected to the output end of the second PMOS tube, the output end of the sixth PMOS tube, the undervoltage/overvoltage protection chip IC, the resistor R11, and the resistor R12, the other end of the resistor R11 is connected to the positive electrode of the light emitting diode, the negative electrode of the light emitting diode and the other end of the resistor R12 are respectively connected to the undervoltage/overvoltage protection chip IC, one end of the capacitor C2 is grounded, the other end is connected to the undervoltage/overvoltage protection chip IC through the resistor R13, and the double NMOS tubes are connected to the undervoltage/overvoltage protection chip IC through the resistor R14.

The operation of the present invention is described in detail below in conjunction with fig. 1-19.

(1) As shown in fig. 2, 12-17, when both power supplies A, B, C are present, power supply a gives a signal to interlock circuit 1 and interlock anti-backflow circuit 1, such that Q1 in interlock circuit 1 is turned on, Q2 is turned off, the potential of gate G3 of PMOS3 is equal to power supply B, PMOS3 is turned off, D3 and R6 in interlock anti-backflow circuit 1 make the potential of gate G4 of PMOS4 equal to power supply a, and PMOS4 is turned off to prevent power supply a from backflow to output to power supply B; d1, D2 and R5 in the self-locking anti-backflow circuit 1 pull the potential of the grid G1 of the PMOS1 to 0V, so that the PMOS1 is turned on, and the power supply A outputs PM1; PM1 turns Q3 in the interlocking circuit 2 on and Q4 off, the potential of the grid G5 of the PMOS5 is equal to the potential of the power supply C, the PMOS5 is turned off, D4, D5 and R19 in the self-locking anti-backflow circuit 2 pull the potential of the grid G2 of the PMOS2 to 0V, so that the PMOS2 is turned on, and PM1 is output as PM2; PM1 pulls the gate G6 potential of PMOS6 in the interlocking anti-backflow circuit 2 through D6 and R20 to coincide with the output PM1 of PMOS1, and PMOS6 is turned off, preventing the backflow output of power supply A to power supply C. At this time, the power supply B/C is turned off by the PMOS3 and the PMOS5 and cannot be output, and the power supply A is normally output through the PMOS1 and the PMOS 2.

(2) As shown in fig. 3, 12-17, when the power source A, B is present and the power source C is not present, the power source a gives a signal to the interlock circuit 1 and the interlock anti-backflow circuit 1, so that the Q1 in the interlock circuit 1 is turned on, the Q2 is turned off, the potential of the gate G3 of the PMOS3 is equal to the power source B, the PMOS3 is turned off, the potentials of the gates G4 of the PMOS4 are equal to the power source a by the D3 and R6 in the interlock anti-backflow circuit 1, and the PMOS4 is turned off to prevent the power source a from backflow to be outputted to the power source B; d1, D2 and R5 in the self-locking anti-backflow circuit 1 pull the potential of the grid G1 of the PMOS1 to 0V, so that the PMOS1 is turned on, and the power supply A outputs PM1; d4, D5 and R19 in the self-locking anti-backflow circuit 2 pull the potential of the grid electrode G2 of the PMOS2 to 0V, so that the PMOS2 is turned on, and PM1 is output as PM2; PM1 pulls the gate G6 potential of PMOS6 in the interlocking anti-backflow circuit 2 through D6 and R20 to coincide with the output PM1 of PMOS1, and PMOS6 is turned off, preventing the backflow output of power supply A to power supply C. At this time, the power supply B is turned off by the PMOS3 and cannot be outputted, and the power supply A is normally outputted through the PMOS1 and the PMOS 2.

(3) As shown in fig. 4, 12-17, when power source A, C is present and power source B is not present, power source a gives a signal to the interlocking anti-backflow circuit 1, and in the interlocking anti-backflow circuit 1, D3 and R6 make the potential of gate G4 of PMOS4 equal to power source a, PMOS4 turns off to prevent power source a from backflow out to power source B; d1, D2 and R5 in the self-locking anti-backflow circuit 1 pull the potential of the grid G1 of the PMOS1 to 0V, so that the PMOS1 is turned on, and the power supply A outputs PM1; PM1 turns Q3 in the interlocking circuit 2 on and Q4 off, the potential of the grid G5 of the PMOS5 is equal to the potential of the power supply C, the PMOS5 is turned off, D4, D5 and R19 in the self-locking anti-backflow circuit 2 pull the potential of the grid G2 of the PMOS2 to 0V, so that the PMOS2 is turned on, and PM1 is output as PM2; PM1 pulls the gate G6 potential of PMOS6 in the interlocking anti-backflow circuit 2 through D6 and R20 to coincide with the output PM1 of PMOS1, and PMOS6 is turned off, preventing the backflow output of power supply A to power supply C. At this time, the power supply C is turned off by the PMOS5 and cannot be outputted, and the power supply A is normally outputted through the PMOS1 and the PMOS 2.

In the application scene of the monitor, the monitor can be used outdoors, and the most convenient use outdoors is to use a battery buckle to supply power for the monitor, so that the battery becomes a very easy-to-consume device, and if the battery is used for supplying power for the monitor and an AC power supply is also connected, the output of the battery needs to be cut off, and the AC-DC power supply is selected.

(4) As shown in fig. 5, 12-17, when only the power supply a exists, the power supply a gives a signal to the interlocking anti-backflow circuit 1, and the electric potential of the grid electrode G4 of the PMOS4 is equal to the power supply a by the D3 and the R6 in the interlocking anti-backflow circuit 1, so that the PMOS4 turns off to prevent the power supply a from backflow and outputting to the power supply B; d1, D2 and R5 in the self-locking anti-backflow circuit 1 pull the potential of the grid G1 of the PMOS1 to 0V, so that the PMOS1 is turned on, and the power supply A outputs PM1; d4, D5 and R19 in the self-locking anti-backflow circuit 2 pull the potential of the grid electrode G2 of the PMOS2 to 0V, so that the PMOS2 is turned on, and PM1 is output as PM2; PM1 pulls the gate G6 potential of PMOS6 in the interlocking anti-backflow circuit 2 through D6 and R20 to coincide with the output PM2 of PMOS2, and PMOS6 is turned off, preventing the backflow output of power supply A to power supply C. At this time, the power supply a normally outputs through PMOS1 and PMOS 2.

(5) As shown in fig. 6, 12-17, when the power source B, C is present and the power source a is not present, the power source B gives a signal to the interlock circuit 1 to turn off Q2 in the interlock circuit 1 and turn on the PMOS3 when the potential of the gate G3 of the PMOS3 is equal to 0V, the PMOS3 is turned on, the power source B outputs PM3, the potentials of the gates G4 of the PMOS4 are pulled to 0V by the R6 and R7 in the interlock anti-backflow circuit 1, the PMOS4 is turned on, the PM3 outputs PM4, the potentials of the gates G2 of the PMOS2 are pulled to 0V by the D4, D5 and R19 in the self-locking anti-backflow circuit 2, the PMOS2 is turned on, and the PM4 outputs PM2; PM3 pulls the potential of the grid G1 of the PMOS1 to PM1 through R5 in the self-locking anti-backflow circuit 1, so that the PMOS1 is closed, and the power supply is prevented from backflow and output to the power supply A; PM1 turns Q3 in interlock circuit 2 on Q4 off, the potential of grid G5 of PMOS5 equals power C, then PMOS5 turns off, PM1 pulls the potential of grid G6 of PMOS6 through D6 and R20 in interlock anti-backflow circuit 2 to be consistent with PM2, then PMOS6 turns off, prevents power supply from flowing backward and outputting to power C, and power C is turned off by PMOS5 and can not output at this moment, and power B normally outputs through PMOS3, PMOS4 and PMOS 2.

When a user uses the camera outdoor, under the condition that no AC exists, the camera can only output power which is connected to the power B, or other DC power is connected to the power B, and the battery buckle is connected to the power C for power supply, although two paths of power supplies are used for power supply, the circuit can preferably select the power B for power supply, the power of the battery buckle is cut off, and the electric quantity of a battery is reserved for standby.

(6) As shown in fig. 7, 12-17, when the power supply B is present and the power supply A, C is not present, the power supply B gives a signal to the interlock circuit 1 to turn off Q2 in the interlock circuit 1 and turn on the PMOS3 when the potential of the gate G3 of the PMOS3 is equal to 0V, the PMOS3 is turned on, the power supply B outputs PM3, the potentials of the gates G4 of the PMOS4 are pulled to 0V by the R6 and R7 in the interlock anti-backflow circuit 1, the PMOS4 is turned on, the PM3 outputs PM4, the potentials of the gates G2 of the PMOS2 are pulled to 0V by the D4, D5 and R19 in the self-locking anti-backflow circuit 2, the PMOS2 is turned on, and the PM4 outputs PM2; PM3 pulls the potential of the grid G1 of the PMOS1 to PM1 through R5 in the self-locking anti-backflow circuit 1, so that the PMOS1 is closed, and the power supply is prevented from backflow to output a power supply A; PM1 pulls the potential of the grid G6 of the PMOS6 to be consistent with PM2 through D6 and R20 in the interlocking anti-backflow circuit 2, the PMOS6 is closed, the power supply is prevented from being reversely output to the power supply C, and the power supply B is normally output through the PMOS3, the PMOS4 and the PMOS 2.

(7) As shown in fig. 8, 12-17, when the power source C is present and the power source A, B is not present, Q3 in the interlock circuit 2 is turned off and Q4 is turned on, so that the potential of the gate G5 of the PMOS5 is pulled to 0V, the PMOS5 is turned on, the power source C is output to the PM5, the gate G6 of the PMSO6 in the interlock anti-backflow circuit 2 is pulled to 0V by R20 and R21, the PMOS6 is turned on, and the PM5 is output to the PM6; PM5 pulls the potential of the grid G2 of the PMOS2 to be consistent with PM2 through R19 in the self-locking anti-backflow circuit 2, so that the PMOS2 is closed, the power supply is prevented from backflow and outputting to the power supply A, B, and the power supply C is normally output through the PMOS5 and the PMOS 6.

When the camera is used outdoors, a user often encounters the condition that the camera is not provided with an AC power supply and a DC power supply, and at the moment, the camera can be powered by the battery through the battery buckle, so that the camera is convenient and suitable for moving.

The sampling circuit and the undervoltage and overvoltage protection circuit compare PM2 with a preset value of the sampling circuit, and judge whether the voltage is safe voltage or not: if yes, the high level is output to NMOS-G through R14, so that the double NMOS is opened and normally output. If the voltage is judged to be unsafe, the low level is output to NMOS-G through R14, so that the double NMOS is closed, at the moment, the pin6 of the IC outputs the low level, and the LED is lightened to prompt the closing of the power supply output.

The invention adds reverse connection protection in the design, thus ensuring the safety of the equipment and reducing unnecessary loss. With reference to fig. 10, 12-17, after the power supply B is reversely connected, the positive electrode cannot reach the negative electrode of the power supply through Q1/Q2 in the interlocking circuit 1 and D1 in the interlocking anti-backflow circuit 1, and the interlocking circuit 1 and the interlocking anti-backflow circuit 1 do not work at this time, so that the PMOS3 and the PMOS4 cannot be opened, the main circuit cannot form a loop, and normal operation of the power supply and the rear-stage circuit in the reverse connection state is ensured.

The foregoing has been described schematically the invention and embodiments thereof, which are not limiting, but are capable of other specific forms of implementing the invention without departing from its spirit or essential characteristics. The drawings are also merely illustrative of one embodiment of the invention, the actual construction is not limited thereto, and any reference signs in the claims shall not be construed as limiting the scope of the claims concerned. Therefore, if one of ordinary skill in the art is informed by this disclosure, a structural manner and an embodiment similar to the technical scheme are not creatively designed without departing from the gist of the present invention, and all the structural manners and the embodiment are considered to be within the protection scope of the present patent. In addition, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" preceding an element does not exclude the inclusion of a plurality of such elements. The various elements recited in the product claims may also be embodied in software or hardware. The terms first, second, etc. are used to denote a name, but not any particular order.

Claims

1. A power switching circuit, characterized by: the self-locking anti-backflow circuit comprises a first switch, a third switch, a fourth switch, a first self-locking anti-backflow circuit, a first interlocking circuit and a first interlocking anti-backflow circuit;

the output end of the first self-locking backflow preventing circuit is connected with a first switch, the output end of the first interlocking circuit is connected with a third switch, and the output end of the first interlocking backflow preventing circuit is connected with a fourth switch;

the first interlocking circuit comprises resistors R1, R2, R3 and R4 and triodes Q1 and Q2; one end of the resistor R1 is used for being connected with the power supply A, the other end of the resistor R1 is respectively connected with the resistor R2 and the base electrode of the triode Q1, and the other end of the resistor R2 and the emitter electrode of the triode Q1 are grounded; the collector of the triode Q1 is respectively connected with one end of a resistor R3 and the base of the triode Q2, the other end of the resistor R3 and one end of a resistor R4 are respectively connected with a power supply B, the other end of the resistor R4 and a third switch are connected with the collector of the triode Q2, and the emitter of the triode Q2 is grounded;

the first self-locking anti-backflow circuit comprises a resistor R5 and diodes D1 and D2, one end of the resistor R5 is connected with the first switch, the other end of the resistor R5 is connected with the positive electrode of the diode D1, the negative electrode of the diode D1 is connected with the negative electrode of the diode D2, the positive electrode of the diode D2 is grounded, and the output of the third switch is connected between the resistor R5 and the positive electrode of the diode D1;

the first interlocking anti-backflow circuit comprises resistors R6 and R7 and a diode D3; the positive pole of diode D3 is used for connecting power A, and the negative pole of diode D3 is connected one end of resistance R6 and one end of resistance R7 respectively, and the fourth switch is connected to the other end of resistance R6, and the other end ground connection of resistance R7.

2. The power switching circuit according to claim 1, wherein: the automatic switching device also comprises a second switch, a second self-locking backflow preventing circuit, a fifth switch, a sixth switch, a second interlocking circuit and a second interlocking backflow preventing circuit; the output end of the first switch is respectively connected with the input ends of the second switch, the second interlocking circuit and the second interlocking backflow preventing circuit; the output end of the fourth switch is respectively connected with the input ends of the second switch, the second interlocking circuit and the second interlocking backflow preventing circuit; the input ends of the fifth switch and the second interlocking circuit are respectively used for being connected with a power supply C, and the output end of the fifth switch is respectively connected with the input ends of the sixth switch and the second self-locking backflow preventing circuit; the output end of the sixth switch and the output end of the second switch are connected with the power supply for output, and the output end of the fourth switch and the output end of the first switch are not directly connected with the power supply for output; the output end of the second self-locking backflow preventing circuit is connected with a second switch, the output end of the second interlocking circuit is connected with a fifth switch, and the output end of the second interlocking backflow preventing circuit is connected with a sixth switch;

the second interlocking circuit comprises resistors R15, R16, R17 and R18 and triodes Q3 and Q4; one end of the resistor R15 is connected with the output end of the first switch and the output end of the fourth switch, the other end of the resistor R15 is respectively connected with the resistor R16 and the base electrode of the triode Q3, and the other end of the resistor R16 and the emitter electrode of the triode Q3 are grounded; the collector of the triode Q3 is respectively connected with one end of a resistor R17 and the base of the triode Q4, the other end of the resistor R17 and one end of a resistor R18 are respectively connected with a power supply C, the other end of the resistor R18 and a fifth switch are connected with the collector of the triode Q4, and the emitter of the triode Q4 is grounded;

the second self-locking anti-backflow circuit comprises a resistor R19 and diodes D4 and D5, one end of the resistor R19 is connected with a second switch, the other end of the resistor R19 is connected with the anode of the diode D4, the cathode of the diode D4 is connected with the cathode of the diode D5, the anode of the diode D5 is grounded, and the output of the fifth switch is connected between the resistor R19 and the anode of the diode D4;

the second interlocking backflow preventing circuit comprises resistors R20 and R21 and a diode D6; the output end of the first switch and the output end of the fourth switch are connected with the positive electrode of a diode D6, the negative electrode of the diode D6 is respectively connected with one end of a resistor R20 and one end of a resistor R21, the other end of the resistor R20 is connected with a sixth switch, and the other end of the resistor R21 is grounded.

3. The power switching circuit according to claim 2, wherein: the second switch, the fifth switch and the sixth switch are PMOS tubes.

4. The power switching circuit according to claim 1, wherein: the first switch, the third switch and the fourth switch are PMOS tubes.

5. The power switching circuit according to claim 1, 2, 3 or 4, wherein: the system also comprises a seventh switch, a sampling circuit and an undervoltage and overvoltage protection circuit; the output end of the first switch and the output end of the fourth switch are connected with the seventh switch and the input end of the sampling circuit, the undervoltage and overvoltage protection is respectively connected with the output end of the sampling circuit and the seventh switch, the seventh switch is connected with the power supply output, or the output end of the second switch and the output end of the sixth switch are connected with the seventh switch and the input end of the sampling circuit, the undervoltage and overvoltage protection is respectively connected with the output end of the sampling circuit and the seventh switch, and the seventh switch is connected with the power supply output.

6. The power switching circuit according to claim 5, wherein: the seventh switch is a double NMOS tube.