CN109638083B - Fast recovery diode and preparation method thereof - Google Patents

Fast recovery diode and preparation method thereof Download PDF

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CN109638083B
CN109638083B CN201811635757.2A CN201811635757A CN109638083B CN 109638083 B CN109638083 B CN 109638083B CN 201811635757 A CN201811635757 A CN 201811635757A CN 109638083 B CN109638083 B CN 109638083B
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boron
front surface
region
phosphorus
photoresist
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CN109638083A (en
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张超
欧阳潇
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Jiejie Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention discloses a fast recovery diode, which comprises a front anode, a P+ boron-rich region, an N-light phosphorus region, an N-epitaxial layer, an N++ substrate region and a back cathode which are sequentially arranged from top to bottom, wherein the P+ boron-rich region and the N-light phosphorus region are provided with bilateral symmetry mesa grooves, and the P-light boron region is arranged between the mesa grooves at two sides of the N-light phosphorus region, and the preparation method comprises the following steps: the preparation of epitaxial materials, the front surface phosphorus injection, primary oxidation, primary photoetching, front surface boron injection, boron re-expansion, front surface boron supplement, platinum diffusion, front surface photoetching groove, mesa corrosion, glass passivation, front surface photoetching lead wire, front surface aluminum evaporation, front surface back surface reverse etching, back surface thinning, back surface silver evaporation, alloy evaporation and testing.

Description

Fast recovery diode and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a fast recovery diode and a preparation method thereof.
Background
The semiconductor power device is a basic electronic component for energy control and conversion of a power electronic system, and the continuous development of the power electronic technology opens up a wide application field for the semiconductor power device. Among the many semiconductor power devices, the fast recovery diode FRED (Fast Recovery Epitaxial Diode) is one of the most commonly used basic electronic components in power electronic circuits and plays a significant role in the circuit. The performance of the circuit is usually one of key components for judging whether the circuit design is successful or not and judging whether the circuit operates normally or not.
FRED (Fast Recovery Epitaxial Diode) A fast recovery diode made of epitaxial silicon wafer has the advantages of high frequency, high voltage, high current, low loss, no electromagnetic interference and the like, and FRED can be used as PFC diode, clamping diode and absorption diode independently or as a freewheeling diode matched with IGBT. FRED is widely used in the industrial, medical and aerospace fields of electric welders, switching power supplies, converters, choppers, inverters, and the like.
In a power electronic circuit, in order to reduce the turn-off loss of a diode and improve the operation efficiency and reliability of the whole machine, the diode is required to have a fast reverse recovery characteristic, that is, the FRED needs to have the characteristics of short reverse recovery time Trr, small reverse recovery charge Qrr, low on-state voltage drop Vf and small maximum reverse recovery current Irrm. The method of controlling the reverse recovery time Trr is to use a carrier lifetime control technique of a heavy metal element such as gold, platinum, or the like, so that Trr forms a trade-off relationship with Vf, namely: the smaller the Trr value, the larger the Vf value, so that the turn-off loss increases, reducing the reliability of the FRED itself.
In the conventional structure FRED as shown in fig. 1, the mesa structure FRED is fabricated according to the process flow as shown in fig. 2. The conventional FRED uses an N++ region as a substrate, and an epitaxially grown N-region as an epitaxial layer to prepare an epitaxial wafer. The mesa structure FRED is formed through the processes of front boron supplementing, boron re-expanding, platinum diffusing, front grooving, mesa corrosion, glass passivation, front aluminum steaming, front back etching, back thinning, back silver steaming, alloy steaming and the like. The process can obtain good Trr-Vf trade-off relation, and can meet the conventional circuit application. However, for higher-demand application environments, lower diode turn-off loss is required, which limits the application of the traditional structure FRED, and further optimizing the product structure of the FRED is required to obtain better Trr-Vf trade-off relationship so as to adapt to higher application demands.
Disclosure of Invention
The invention aims to provide a fast recovery diode and a preparation method thereof.
The technical scheme adopted by the invention is as follows:
a fast recovery diode, characterized by: the solar cell comprises a front anode, a P+ boron concentration region, an N-phosphorus dilution region, an N-epitaxial layer, an N++ substrate region and a back cathode which are sequentially arranged from top to bottom, wherein the P+ boron concentration region and the N-phosphorus dilution region are provided with bilateral symmetry mesa grooves, and the P-boron dilution region is arranged between the mesa grooves at two sides of the N-phosphorus dilution region.
The preparation method of the fast recovery diode comprises the following steps:
step 1: preparing an epitaxial material, wherein the crystal orientation of a substrate of an epitaxial wafer is < 1>, the impurity is arsenic, the resistivity is 0.001-0.005 omega cm, the thickness is 450-550um, the epitaxial impurity is phosphorus, the resistivity is 5-8 omega cm, and the thickness is 25-40um;
step 2: injecting phosphorus from the front side, wherein the dosage of the injected phosphorus from the front side is 1E11-1E12cm < -2 >, and the injection energy is 50-80KeV;
step 3: performing primary oxidation, wherein the process temperature of the silicon wafer is 1000-1150 ℃, and the thickness of an oxide layer is 1.4-2.0um;
step 4: performing primary photoetching, wherein the front photoresist is 100 photoresist, so as to form a required photoetching window;
step 5: front surface boron implantation, wherein the dosage of the front surface boron implantation is 1E13-1E14cm < -2 >, and the implantation energy is 60-100KeV;
step 6: boron re-expansion is carried out, and boron re-expansion junction pushing is carried out at the temperature of 1200-1250 ℃ to form a P-region;
step 7: supplementing boron on the front surface, coating a liquid boron source on the front surface of the silicon wafer, and performing pre-deposition in a diffusion furnace at 1050-1150 ℃;
step 8: platinum diffusion, coating a liquid platinum source on a silicon wafer, performing platinum diffusion in a diffusion furnace at 900-970 ℃, and adjusting the process time according to the Trr time requirement;
step 9: etching grooves on the front side by photoetching, coating 300 glue on the front side and the back side of the silicon wafer, and forming the required grooves by photoetching exposure;
step 10: etching a table surface, wherein the silicon wafer comprises the following components in volume ratio of HF, HNO3, CH3COOH and fuming nitric acid of (8-10): (6-8): (8-10): carrying out mesa corrosion in the corrosive liquid in the step (3-5), wherein the groove depth is required to be 15-40um, and the groove appearance is complete and smooth;
step 11: passivating glass, preparing glass powder, performing operations such as powdering, low-temperature presintering, powdering, high-temperature sintering and the like;
step 12: front photoetching leads, wherein front photoresist is 300 photoresist, and a required lead hole window is formed;
step 13: evaporating aluminum on the front surface, wherein the thickness of the front surface evaporating aluminum layer is 5+/-0.03 um or 7+/-0.05 um;
step 14: back etching the front surface, wherein the front surface photoresist is 100 photoresist, and a required back etching window is formed;
step 15: thinning the back according to different products;
step 16: back silver steaming, wherein the thickness of the back silver steaming is Ti=1400+/-200A, ni=5000+/-500A, ag=10000+/-1000A;
step 17: the alloy comprises the following technological conditions: 525+/-10 ℃/25+/-10 min;
step 18: and (5) testing.
The invention has the advantages that: the P+/P-/N-composite structure is formed on the front surface of the chip, the approximately symmetrical carrier concentration distribution is formed, the effect of anode emission efficiency adjustment is generated, the more optimized Trr-Vf tradeoff relationship is obtained, the turn-off loss of FRED is effectively reduced, and the reliability and stability of the RRED in the reverse recovery process are improved.
Drawings
The invention will be described in further detail with reference to the drawings and the detailed description.
FIG. 1 is a schematic diagram of a diode according to the background art of the invention;
FIG. 2 is a flow chart of a diode manufacturing process according to the background art of the invention;
FIG. 3 is a block diagram of a diode of the present invention;
fig. 4 is a process flow diagram of the preparation of the diode of the present invention.
Wherein: 1. a front side anode; 2. a P+ boron expansion region; 3. a mesa groove; 4. n-epitaxial layer; 5. an N++ substrate region; 6. a backside cathode; 7. a P+ concentrated boron region; 8. a P-light boron region; 9. n-light phosphorus zone.
Detailed Description
As shown in fig. 3-4, the fast recovery diode comprises a front anode 1, a p+ boron-rich region 7, an N-phosphorus-dilute region 9, an N-epitaxial layer 4, an n++ substrate region 5, a back cathode 6, wherein the p+ boron-rich region 7 and the N-phosphorus-dilute region 7 are sequentially arranged from top to bottom, mesa grooves 3 which are bilaterally symmetrical are formed in the p+ boron-rich region 7, and P-phosphorus-dilute regions 8 are arranged between the mesa grooves on two sides of the N-phosphorus-dilute region 9.
The preparation method of the fast recovery diode comprises the following steps:
step 1: preparing an epitaxial material, wherein the crystal orientation of a substrate of an epitaxial wafer is < 1>, the impurity is arsenic, the resistivity is 0.001-0.005 omega cm, the thickness is 450-550um, the epitaxial impurity is phosphorus, the resistivity is 5-8 omega cm, and the thickness is 25-40um;
step 2: injecting phosphorus from the front side, wherein the dosage of the injected phosphorus from the front side is 1E11-1E12cm < -2 >, and the injection energy is 50-80KeV;
step 3: performing primary oxidation, wherein the process temperature of the silicon wafer is 1000-1150 ℃, and the thickness of an oxide layer is 1.4-2.0um;
step 4: performing primary photoetching, wherein the front photoresist is 100 photoresist, so as to form a required photoetching window;
step 5: front surface boron implantation, wherein the dosage of the front surface boron implantation is 1E13-1E14cm < -2 >, and the implantation energy is 60-100KeV;
step 6: boron re-expansion is carried out, and boron re-expansion junction pushing is carried out at the temperature of 1200-1250 ℃ to form a P-region;
step 7: supplementing boron on the front surface, coating a liquid boron source on the front surface of the silicon wafer, and performing pre-deposition in a diffusion furnace at 1050-1150 ℃;
step 8: platinum diffusion, coating a liquid platinum source on a silicon wafer, performing platinum diffusion in a diffusion furnace at 900-970 ℃, and adjusting the process time according to the Trr time requirement;
step 9: etching grooves on the front side by photoetching, coating 300 glue on the front side and the back side of the silicon wafer, and forming the required grooves by photoetching exposure;
step 10: etching a table surface, wherein the silicon wafer comprises the following components in volume ratio of HF, HNO3, CH3COOH and fuming nitric acid of (8-10): (6-8): (8-10): carrying out mesa corrosion in the corrosive liquid in the step (3-5), wherein the groove depth is required to be 15-40um, and the groove appearance is complete and smooth;
step 11: passivating glass, preparing glass powder, performing operations such as powdering, low-temperature presintering, powdering, high-temperature sintering and the like;
step 12: front photoetching leads, wherein front photoresist is 300 photoresist, and a required lead hole window is formed;
step 13: evaporating aluminum on the front surface, wherein the thickness of the front surface evaporating aluminum layer is 5+/-0.03 um or 7+/-0.05 um;
step 14: back etching the front surface, wherein the front surface photoresist is 100 photoresist, and a required back etching window is formed;
step 15: thinning the back according to different products;
step 16: back silver steaming, wherein the thickness of the back silver steaming is Ti=1400+/-200A, ni=5000+/-500A, ag=10000+/-1000A;
step 17: the alloy comprises the following technological conditions: 525+/-10 ℃/25+/-10 min;
step 18: and (5) testing.
The manufacturing method of the invention is not only suitable for mesa FRED, but also can be used for planar FRED, punch-through FRED and other FRED structures, is not only suitable for FRED, but also can be used for BJT, SCR, MOSFET, MCT and other power semiconductor devices which can introduce the anode emission efficiency adjustment concept, is not only suitable for bulk silicon, but also can be used for semiconductor materials such as silicon carbide, gallium arsenide, indium phosphide, silicon germanium and the like.
The invention forms a P+/P-/N-composite structure on the front surface of the chip, forms approximately symmetrical carrier concentration distribution, generates the effect of anode emission efficiency adjustment, obtains a more optimized Trr-Vf tradeoff relationship, effectively reduces the turn-off loss of FRED and improves the reliability and stability of the RRED in the reverse recovery process.

Claims (1)

1. A preparation method of a fast recovery diode is characterized by comprising the following steps: the diode comprises a front anode, a P+ boron concentration region, an N-light phosphorus region, an N-epitaxial layer, an N++ substrate region and a back cathode which are sequentially arranged from top to bottom, wherein the P+ boron concentration region and the N-light phosphorus region are provided with bilateral symmetry mesa grooves, and the P-light boron region is arranged between the mesa grooves at two sides of the N-light phosphorus region, and the preparation method comprises the following steps:
step 1: preparing an epitaxial material, wherein the crystal orientation of a substrate of an epitaxial wafer is < 1>, the impurity is arsenic, the resistivity is 0.001-0.005 omega cm, the thickness is 450-550 mu m, the epitaxial impurity is phosphorus, the resistivity is 5-8 omega cm, and the thickness is 25-40 mu m;
step 2: injecting phosphorus from the front side, wherein the dosage of the injected phosphorus from the front side is 1E11-1E12cm < -2 >, and the injection energy is 50-80KeV;
step 3: performing primary oxidation, wherein the process temperature of the silicon wafer is 1000-1150 ℃, and the thickness of an oxide layer is 1.4-2.0 mu m;
step 4: performing primary photoetching, wherein the front photoresist is 100 photoresist, so as to form a required photoetching window;
step 5: front surface boron implantation, wherein the dosage of the front surface boron implantation is 1E13-1E14cm < -2 >, and the implantation energy is 60-100KeV;
step 6: boron re-expansion is carried out, and boron re-expansion junction pushing is carried out at 1200-1250 ℃ to form a P-light boron region;
step 7: supplementing boron on the front surface, coating a liquid boron source on the front surface of the silicon wafer, and performing pre-deposition in a diffusion furnace at 1050-1150 ℃;
step 8: platinum diffusion, coating a silicon wafer with a liquid platinum source, and performing platinum diffusion in a diffusion furnace at 900-970 ℃ for a long time
Adjusting according to the Trr time requirement;
step 9: etching grooves on the front side by photoetching, coating 300 photoresist on the front side and the back side of a silicon wafer, and forming the required grooves by photoetching exposure;
step 10: etching a table surface, wherein the silicon wafer comprises the following components in volume ratio of HF, HNO3, CH3COOH and fuming nitric acid of (8-10): (6-8): (8-10): carrying out mesa corrosion in the corrosive liquid in the step (3-5), wherein the groove depth is required to be 15-40 mu m, and the groove appearance is complete and smooth;
step 11: passivating glass, preparing glass powder, performing operations such as powdering, low-temperature presintering, powdering, high-temperature sintering and the like;
step 12: front photoetching leads, wherein front photoresist is 300 photoresist, and a required lead hole window is formed;
step 13: evaporating aluminum from the front surface, wherein the thickness of the front surface evaporating aluminum layer is 5+/-0.03 mu m or 7+/-0.05 mu m;
step 14: back etching the front surface, wherein the front surface photoresist is 100 photoresist, and a required back etching window is formed;
step 15: thinning the back according to different products;
step 16: back surface silver steaming, wherein the thickness of the back surface silver steaming is Ti=1400+/-200 a, ni=5000+/-500 a, ag=10000+/-1000 a;
step 17: the alloy comprises the following technological conditions: 525+/-10 ℃/25+/-10 min;
step 18: and (5) testing.
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