CN109637979B - Method for manufacturing grid - Google Patents
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- CN109637979B CN109637979B CN201811553856.6A CN201811553856A CN109637979B CN 109637979 B CN109637979 B CN 109637979B CN 201811553856 A CN201811553856 A CN 201811553856A CN 109637979 B CN109637979 B CN 109637979B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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Abstract
The invention discloses a manufacturing method of a grid, which comprises the following steps: providing a semiconductor substrate with a gate dielectric layer and a polysilicon gate sequentially formed on the surface; forming a hard mask layer formed by overlapping a first nitride layer and a second oxide layer; photoetching and etching to form a plurality of pseudo gate structures, wherein the width of the polysilicon gate comprises more than 2; forming a side wall; forming a source region and a drain region of the device; and removing the second oxide layer, respectively carrying out photoetching definition according to different widths of the polysilicon gates in the process of removing the second oxide layer, opening the top area of the polysilicon gate with more than one width capable of removing the second oxide layer once by each photoetching definition, then removing the second oxide layer in the opened area, and repeatedly carrying out the steps of photoetching opening and removing the second oxide layer to remove the second oxide layer on the top of all the polysilicon gates. The method can ensure that the hard mask layer at the top of the polysilicon gate can be well removed, and simultaneously can realize good protection on the structures at two sides of the polysilicon gate.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a gate.
Background
In the HKMG process, such as 28nm HKMG, a gate dielectric layer with a high dielectric constant (HK) and a Metal Gate (MG) are required to be formed at the same time, in the conventional HKMG process, a post-metal gate process is usually adopted, in the post-metal gate process, a Dummy gate structure is usually adopted, a gate dielectric layer, a channel region and a source/drain region of a device are formed by utilizing a polysilicon gate (Poly), i.e., a Dummy polysilicon gate (Dummy Poly), of the Dummy gate structure, and then replacement of the metal gate is performed, i.e., the polysilicon gate of the Dummy gate structure is removed (Dummy Poly remove, DPR), and then the metal gate is formed by filling a region where the polysilicon gate of the Dummy gate structure is removed with metal. Before DPR, a Hard Mask (HM) including an oxide layer is formed on the top of the polysilicon gate, so that the oxide layer of the Hard Mask needs to be removed before DPR.
In the 28nm HKMG process, in order to avoid damage (damage) to other regions such as an active region in the process of removing an oxide layer of a hard mask layer of a polysilicon gate, the other regions are protected by a photolithography, which is a general process: the method comprises the steps of firstly opening photoresist of a large polycrystalline silicon gate through one-step photoetching, then carrying out Etching Back (EB) of the Photoresist (PR), namely EB1, and opening PR on the rest polycrystalline silicon gates, wherein the method is mainly used for overcoming PR load (loading) on the large polycrystalline silicon gate, at the moment, all the polysilicon gates are already opened, then carrying out the etching back process for the second time, namely EB2, removing an oxide layer of a hard mask layer, and finally carrying out silicon nitride (SiN) trimming etching (slim), wherein the SiN is usually used as a side wall (spacer) of the polycrystalline silicon gate, and carrying out side wall pull-down (spacer pull down). After EB1, special attention is paid to the residual amount (Remain) of PR on a small block of poly, which is too high, so that PR on the poly is not completely opened, and HM cannot be completely removed; however, too low PR tends to result in silicon germanium (SGe) on the surface of the Active Area (AA) on both sides of the polysilicon gate and even no PR protection on AA, which eventually results in nickel silicide (Nisi) or SiGe damage. Control of PR remaining after EB1 is important, so it is relatively difficult to remove HM without creating damage. The prior art method will now be described in detail with reference to the accompanying drawings:
as shown in fig. 1A to 1E, the device structure diagram in each step of the conventional method is shown, and the conventional gate manufacturing method includes the following steps:
step one, as shown in fig. 1A, providing a semiconductor substrate 101, and sequentially forming a gate dielectric layer 103 and a polysilicon gate 104 on the surface of the semiconductor substrate 101.
The semiconductor substrate 101 is a silicon substrate.
The gate dielectric layer 103 includes a high dielectric constant layer, and an interface layer is further provided between the high dielectric constant layer and the semiconductor substrate 101.
A field oxide layer 102 is formed in the semiconductor substrate 101, and an active region is isolated by the field oxide layer 102; the active region includes an active region of a Core (Core) region and an active region of an Input Output (IO) region.
The field oxide layer 102 is a shallow trench field oxide and is formed by a shallow trench isolation process.
In the conventional method, the widths of the polysilicon gates 104 include two widths, and the width of the polysilicon gate 104 in the active region outside the core region is greater than the width of the polysilicon gate 104 in the active region in the core region.
The existing gate structure, i.e., the component corresponding to the metal gate formed subsequently, includes a core component and an input/output component, which are respectively located in the core region and outside the core region.
The component is a field effect transistor.
The components include n-type Field Effect Transistors (FETs), i.e., nfets, and p-type field effect transistors, i.e., pfets.
Step two, as shown in fig. 1A, forming a hard mask layer on the surface of the polysilicon gate 104; the hard mask layer is formed by stacking a first nitride layer 105 and a second oxide layer 106.
Step three, as shown in fig. 1A, performing photolithography and etching to form a plurality of dummy gate structures, wherein each dummy gate structure is formed by overlapping the etched gate dielectric layer 103, the etched polysilicon gate 104 and the hard mask layer; after etching, the width of the polysilicon gate 104 includes 2.
Step four, as shown in fig. 1A, a sidewall 108 is formed on the side surface of each dummy gate structure.
The material of the sidewall 108 includes a nitride layer, and in fig. 1A, the sidewall 108 further includes an oxide layer, which is shown as a mark 108a in fig. 1E.
And step five, as shown in fig. 1A, forming a source region and a drain region of the device in the active regions at two sides of the dummy gate structure.
An assembly enhancement process is included in the process of forming the source and drain regions of the assembly.
The component enhancement process includes a silicon germanium process. The assembly enhancement process forms a layer of silicon germanium 107 in the source or drain region of the p-type field effect transistor.
The method further comprises the step of forming a nitride layer 109 after the source region and the drain region are formed.
Sixthly, removing the second oxide layer 106 of the hard mask layer, wherein in the existing method, a photoresist etch-back (PREB) process is adopted when removing the second oxide layer 106, specifically:
as shown in fig. 1A, a photoresist pattern 201 is formed by performing a photolithography process, and an open region 202 of the photoresist pattern 201 corresponds to a top region of the polysilicon gate 104 having a larger size.
As shown in fig. 1B, a photoresist back-etching is performed, and the photoresist pattern 201 after the photoresist back-etching exposes the surface of the second oxide layer 106.
As shown in fig. 1C, the second oxide layer 106 is usually removed by a dry etching process, and during the etching process, the photoresist pattern 201 is used to protect the region between the polysilicon gates 104. In actual process, the thickness of the photoresist pattern 201 after PREB is not easily controlled: if the photoresist pattern 201 is thick, the second oxide layer 106 is not easily removed completely; if the thickness of the photoresist pattern 201 is small, the region between the polysilicon gates 104 is not easily protected, as shown in fig. 1C, the region between the polysilicon gates 104 is an active region, and an active region or a drain region is formed in the active region, and a silicon germanium layer 107 is also formed in a part of the active region or the drain region, and a NiSi layer may be formed under other conditions, which may damage these structures.
As shown in fig. 1D, the photoresist pattern 201 is then removed.
As shown in FIG. 1E, a trim etch of silicon nitride (SiN Slim) is performed. After the trimming and etching of the silicon nitride, the nitride layer in the side wall 108 is removed, and only the oxide layer 108a remains in the side wall 108; the silicon nitride layer 9 is also removed.
Disclosure of Invention
The invention aims to provide a manufacturing method of a grid, which can ensure that a hard mask layer at the top of a polysilicon gate can be well removed, and can also realize good protection on structures at two sides of the polysilicon gate.
In order to solve the above technical problem, the method for manufacturing a gate provided by the present invention comprises the following steps:
providing a semiconductor substrate, and sequentially forming a gate dielectric layer and a polysilicon gate on the surface of the semiconductor substrate.
Secondly, forming a hard mask layer on the surface of the polysilicon gate; the hard mask layer is formed by overlapping a first nitride layer and a second oxide layer.
Performing photoetching to form a plurality of pseudo gate structures, wherein each pseudo gate structure is formed by overlapping the etched gate dielectric layer, the etched polysilicon gate and the hard mask layer; and after etching, the width of the polysilicon gate is more than 2.
And step four, forming side walls on the side surfaces of the pseudo gate structures.
And fifthly, forming a source region and a drain region of the device in the active regions at two sides of the dummy gate structure.
Sixthly, removing the second oxide layer of the hard mask layer, in the process of removing the second oxide layer, respectively carrying out photoetching definition according to different widths of the polysilicon gates, opening the top area of the polysilicon gate with more than one width corresponding to the second oxide layer by each photoetching definition, then removing the second oxide layer in the opened area, and repeating the steps of opening the top area of the polysilicon gate with the corresponding width and removing the second oxide layer in the opened area by photoetching definition until the second oxide layer on the top of the polysilicon gate with the whole width is removed; through with the width difference the polycrystalline silicon gate top the hard mask layer the second oxide layer adopts photoetching process to open and get rid of respectively alone, can eliminate the not easily controlled defect of thickness of photoresist when adopting same photoresist to carry out back etching, can avoid simultaneously hard mask layer remains and avoids right the polycrystalline silicon gate or the surface of active area produces the destruction.
In a further improvement, the semiconductor substrate is a silicon substrate.
In a further improvement, the gate dielectric layer comprises a high dielectric constant layer, and an interface layer is arranged between the high dielectric constant layer and the semiconductor substrate.
In a further improvement, after the step six, the method further comprises the following steps:
and forming a contact etching stop layer.
An interlayer film is formed and planarized.
And removing the polysilicon gate.
And filling a metal material layer in the removal region of the polysilicon gate to form a metal gate, and forming HKMG by overlapping the gate dielectric layer comprising the high-dielectric-constant layer and the gate.
In a further improvement, a field oxide layer is formed in the semiconductor substrate provided in the first step, and an active region is isolated by the field oxide layer; the active region comprises an active region corresponding to the core region and an active region outside the core region.
In a further improvement, the widths of the polysilicon gates include two, and the width of the polysilicon gate in the active region outside the core region is greater than the width of the polysilicon gate in the active region in the core region.
In a further improvement, the components corresponding to the metal gate comprise a core component and an input-output component.
In a further refinement, the component is a field effect transistor.
The components include n-type field effect transistors and p-type field effect transistors.
And step four, after the side walls are formed, a step of forming a source region and a drain region of the component on the surface of the semiconductor substrate on two sides of the grid electrode is also included.
A further improvement is to include a device enhancement process in forming the source and drain regions of the device.
In a further refinement, the component enhancement process comprises a silicon germanium process.
In a further improvement, the device enhancement process forms a germanium-silicon layer in a source region or a drain region of the p-type field effect transistor.
The field oxide layer is shallow trench field oxide and is formed by adopting a shallow trench isolation process.
In a further improvement, the material of the sidewall in the fourth step includes a nitride layer.
In a further improvement, the sixth step further comprises a step of removing the first nitride layer.
In a further refinement, the metal material of the metal grid comprises aluminum.
The invention improves the problem generated when the second oxide layer of the hard mask layer at the top of the polysilicon gate is removed before the polysilicon gate is removed for forming the metal gate in the existing gate manufacturing method, and the invention separately opens and removes the second oxide layer of the hard mask layer at the top of the polysilicon gate with different widths by adopting a photoetching process, can eliminate the defect that the thickness of a photoresist is not easy to control when the same photoresist is used for back etching, can simultaneously avoid the hard mask layer residue and damage to the surface of the polysilicon gate or an active region, namely the invention can ensure that the hard mask layer at the top of the polysilicon gate is well removed, and can also realize good protection on the structures at two sides of the polysilicon gate.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1A to 1E are device configuration diagrams in respective steps of a conventional gate electrode manufacturing method;
FIG. 2 is a flow chart of a method of fabricating a gate electrode according to an embodiment of the present invention;
fig. 3A-3G are device structure diagrams in steps of a method according to an embodiment of the invention.
Detailed Description
FIG. 2 is a flow chart of a method for fabricating a gate according to an embodiment of the present invention; as shown in fig. 3A to fig. 3G, which are device structure diagrams in the steps of the method according to the embodiment of the present invention, the method for manufacturing a gate according to the embodiment of the present invention includes the following steps:
step one, as shown in fig. 3A, providing a semiconductor substrate 1, and sequentially forming a gate dielectric layer 3 and a polysilicon gate 4 on the surface of the semiconductor substrate 1.
The semiconductor substrate 1 is a silicon substrate.
The gate dielectric layer 3 includes a high dielectric constant layer, and an interface layer is further provided between the high dielectric constant layer and the semiconductor substrate 1.
A field oxide layer 2 is formed in the semiconductor substrate 1, and an active region is isolated by the field oxide layer 2; the active region comprises an active region corresponding to the core region and an active region outside the core region.
The field oxide layer 2 is formed by shallow trench field oxide and adopting a shallow trench isolation process.
In the method of the embodiment of the present invention, the widths of the polysilicon gates 4 include two widths, and the width of the polysilicon gate 4 in the active region outside the core region is greater than the width of the polysilicon gate 4 in the active region in the core region.
The gate structure of the embodiment of the invention, namely the component corresponding to the metal gate formed subsequently, comprises a core component and an input/output component which are respectively positioned in the core area and outside the core area.
The component is a field effect transistor.
The components include n-type field effect transistors and p-type field effect transistors.
Step two, as shown in fig. 3A, forming a hard mask layer on the surface of the polysilicon gate 4; the hard mask layer is formed by overlapping a first nitride layer 5 and a second oxide layer 6.
Step three, as shown in fig. 3A, performing photolithography and etching to form a plurality of dummy gate structures, wherein each dummy gate structure is formed by overlapping the etched gate dielectric layer 3, the etched polysilicon gate 4 and the hard mask layer; after etching, the width of the polysilicon gate 4 is more than 2.
Step four, as shown in fig. 3A, a side wall 8 is formed on the side surface of each dummy gate structure.
The material of the sidewall spacer 8 includes a nitride layer, and in fig. 3A, the sidewall spacer 8 further includes an oxide layer, which is shown as a mark 8a in fig. 3G.
And step five, as shown in fig. 3A, forming a source region and a drain region of the device in the active regions at two sides of the dummy gate structure.
An assembly enhancement process is included in the process of forming the source and drain regions of the assembly.
The component enhancement process includes a silicon germanium process. The assembly enhancement process forms a germanium-silicon layer 7 in the source region or the drain region of the p-type field effect transistor.
The method also comprises the step of forming a nitride layer 9 after the source region and the drain region are formed.
Sixthly, removing the second oxide layer 6 of the hard mask layer, in the process of removing the second oxide layer 6, respectively performing photoetching definition according to different widths of the polysilicon gate 4, opening the top region of the polysilicon gate 4 with more than one width capable of removing the second oxide layer 6 once by each photoetching definition, then removing the second oxide layer 6 in the opened region, and repeating the steps of opening the top region of the polysilicon gate 4 with the corresponding width and removing the second oxide layer 6 in the opened region by photoetching definition until the second oxide layer 6 on the top of the polysilicon gate 4 with the whole width is removed; through with the width difference the top of polycrystalline silicon gate 4 the hard mask layer the second oxide layer 6 adopts photoetching process to open and get rid of respectively alone, can eliminate the difficult defect of controlling of thickness of photoresist when adopting same photoresist to carry out the back etching, can avoid simultaneously hard mask layer remains and avoid right polycrystalline silicon gate 4 or the surface of active area produces the destruction.
The method of the embodiment of the invention comprises the polysilicon gate 4 with two sizes, namely widths, so that the processes of photoetching definition and silicon oxide removal are adopted twice, and the silicon oxide is usually removed by a dry etching process. The following will now be described with reference to the accompanying drawings:
as shown in fig. 3A, a first photoresist pattern 301 is formed by performing a first photolithography process, and an open region 302 of the first photoresist pattern 301 corresponds to a top region of the polysilicon gate 4 having a larger size.
As shown in fig. 3B, the second oxide layer 6 exposed in the open region 302 is removed by a dry etching process directly using the first photoresist pattern 301 as a mask without performing a photoresist etch back (PREB).
As shown in fig. 3C, the first photoresist pattern 301 is then removed.
As shown in fig. 3D, a second photolithography process is performed to form a second photoresist pattern 303, and an open region 304 of the second photoresist pattern 303 corresponds to a top region of the polysilicon gate 4 with a smaller size.
As shown in fig. 3E, the second oxide layer 6 exposed in the open region 304 is removed by a dry etching process directly using the second photoresist pattern 303 as a mask without performing a photoresist etch back (PREB).
As shown in fig. 3F, the second photoresist pattern 303 is then removed.
As shown in fig. 3G, a trim etch of silicon nitride (SiN Slim) is performed. After the trimming and etching of the silicon nitride, the nitride layer in the side wall 8 is removed, and only the oxide layer 8a remains in the side wall 8; the silicon nitride layer 9 is also removed.
And then a step of removing the first nitride layer 5 is included.
Then, the method also comprises the following steps:
and forming a contact etching stop layer.
An interlayer film is formed and planarized.
And removing the polysilicon gate 4.
And filling a metal material layer in the removed region of the polysilicon gate 4 to form a metal gate, and overlapping the gate dielectric layer 3 comprising the high-dielectric-constant layer and the gate to form the HKMG.
The metal material of the metal grid comprises aluminum.
The embodiment of the invention aims at solving the problem generated when the second oxide layer 6 of the hard mask layer at the top of the polysilicon gate 4 is removed before the polysilicon gate 4 is removed for forming a metal gate in the existing gate manufacturing method, and the embodiment of the invention separately adopts the photoetching process to open and remove the second oxide layer 6 of the hard mask layer at the top of the polysilicon gate 4 with different widths, so that the defect that the thickness of the photoresist is not easy to control when the same photoresist is used for back etching can be eliminated, the hard mask layer residue can be simultaneously avoided, and the damage to the surface of the polysilicon gate 4 or an active region can be avoided, namely the embodiment of the invention can ensure that the hard mask layer at the top of the polysilicon gate 4 can be well removed, and simultaneously, the structures at two sides of the polysilicon gate 4 can be well protected.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (12)
1. A method for manufacturing a gate electrode, comprising the steps of:
providing a semiconductor substrate, and sequentially forming a gate dielectric layer and a polysilicon gate on the surface of the semiconductor substrate;
secondly, forming a hard mask layer on the surface of the polysilicon gate; the hard mask layer is formed by overlapping a first nitride layer and a second oxide layer;
performing photoetching to form a plurality of pseudo gate structures, wherein each pseudo gate structure is formed by overlapping the etched gate dielectric layer, the etched polysilicon gate and the hard mask layer; after etching, the width of the polysilicon gate is more than 2;
forming a side wall on the side surface of each pseudo gate structure;
the side wall is made of a nitride layer; fifthly, forming a source region and a drain region of the device in the active regions at two sides of the pseudo gate structure;
sixthly, removing the second oxide layer of the hard mask layer, in the process of removing the second oxide layer, respectively carrying out photoetching definition according to different widths of the polysilicon gates, opening the top area of the polysilicon gate with more than one width corresponding to the second oxide layer by each photoetching definition, then removing the second oxide layer in the opened area, and repeating the steps of opening the top area of the polysilicon gate with the corresponding width and removing the second oxide layer in the opened area by photoetching definition until the second oxide layer on the top of the polysilicon gate with the whole width is removed; the corresponding photoresist before the photoresist is etched back in each photoetching definition completely fills and extends the top spacing areas of the active areas at two sides of the pseudo gate structure to the surface of the pseudo gate structure, and the second oxide layers of the hard mask layers at the tops of the polysilicon gates with different widths are respectively and independently opened and removed by adopting a photoetching process, so that the defect that the thickness of the photoresist is not easy to control when the same photoresist is used for etching back can be eliminated, the hard mask layer can be prevented from remaining, and the surface of the polysilicon gate or the active area can be prevented from being damaged;
step six is followed by the step of removing the first nitride layer;
then, trimming and etching silicon nitride to remove the silicon nitride in the side wall and realize the pull-down of the side wall;
then, the method also comprises the following steps:
forming a contact etching stop layer;
forming an interlayer film and planarizing the interlayer film;
removing the polysilicon gate;
and filling a metal material layer in the removal region of the polysilicon gate to form a metal gate, and forming HKMG by overlapping the gate dielectric layer comprising a high-dielectric-constant layer and the gate.
2. The method of manufacturing a gate electrode of claim 1, wherein: the semiconductor substrate is a silicon substrate.
3. The method of manufacturing a gate electrode of claim 2, wherein: the gate dielectric layer comprises a high dielectric constant layer, and an interface layer is arranged between the high dielectric constant layer and the semiconductor substrate.
4. The method of manufacturing a gate electrode of claim 1, wherein: forming a field oxide layer in the semiconductor substrate provided by the first step, and isolating an active region by the field oxide layer; the active region comprises an active region corresponding to the core region and an active region outside the core region.
5. The method of manufacturing a gate electrode of claim 4, wherein: the widths of the polysilicon gates comprise two widths, and the width of the polysilicon gate in the active region outside the core region is larger than that of the polysilicon gate in the active region in the core region.
6. The method of manufacturing a gate electrode of claim 1, wherein: the components corresponding to the metal gate comprise a core component and an input/output component.
7. The method of manufacturing a gate electrode of claim 6, wherein: the component is a field effect transistor;
the components include n-type field effect transistors and p-type field effect transistors.
8. The method of manufacturing a gate electrode of claim 7, wherein: an assembly enhancement process is included in the process of forming the source and drain regions of the assembly.
9. The method of manufacturing a gate electrode of claim 8, wherein: the component enhancement process includes a silicon germanium process.
10. The method of manufacturing a gate electrode of claim 9, wherein: and forming a germanium-silicon layer on the source region or the drain region of the p-type field effect transistor by the assembly enhancement process.
11. The method of manufacturing a gate electrode of claim 4, wherein: the field oxide layer is shallow trench field oxide and is formed by adopting a shallow trench isolation process.
12. The method of manufacturing a gate electrode of claim 1, wherein: the metal material of the metal grid comprises aluminum.
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