CN108022969A - Transistor and its manufacture method - Google Patents
Transistor and its manufacture method Download PDFInfo
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- CN108022969A CN108022969A CN201610944423.8A CN201610944423A CN108022969A CN 108022969 A CN108022969 A CN 108022969A CN 201610944423 A CN201610944423 A CN 201610944423A CN 108022969 A CN108022969 A CN 108022969A
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- 238000000034 method Methods 0.000 title claims abstract description 132
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 230000008569 process Effects 0.000 claims abstract description 78
- 238000000137 annealing Methods 0.000 claims abstract description 64
- 238000002955 isolation Methods 0.000 claims abstract description 38
- 150000002500 ions Chemical class 0.000 claims description 106
- 239000010410 layer Substances 0.000 claims description 103
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 26
- 229920005591 polysilicon Polymers 0.000 claims description 25
- 239000011229 interlayer Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 239000007789 gas Substances 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 239000011241 protective layer Substances 0.000 claims description 14
- 238000005224 laser annealing Methods 0.000 claims description 9
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 16
- 238000005516 engineering process Methods 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000006731 degradation reaction Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000008439 repair process Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- CKUAXEQHGKSLHN-UHFFFAOYSA-N [C].[N] Chemical compound [C].[N] CKUAXEQHGKSLHN-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- MEYZYGMYMLNUHJ-UHFFFAOYSA-N tunicamycin Natural products CC(C)CCCCCCCCCC=CC(=O)NC1C(O)C(O)C(CC(O)C2OC(C(O)C2O)N3C=CC(=O)NC3=O)OC1OC4OC(CO)C(O)C(O)C4NC(=O)C MEYZYGMYMLNUHJ-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A kind of transistor and its manufacture method, manufacture method include：Substrate is provided, the substrate includes device area and resistance region；The first isolation structure is formed on the substrate of the resistance region；Pseudo- grid structure is formed on the substrate of the device area, during dummy gate structure is formed, electric resistance structure is formed on first isolation structure；Source and drain doping area is formed in the substrate of dummy gate structure both sides；Ion doping is carried out to the electric resistance structure, to adjust electric resistance structure resistance value；Annealing process processing is carried out, to activate the ion in the ion and electric resistance structure of source and drain doped region；Remove dummy gate structure；Gate structure is formed in dummy gate structure situ.The manufacture method of transistor provided by the invention reduces the manufacture cost of transistor.
Description
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of transistor and its manufacture method.
Background technology
In semiconductor fabrication, as the development of super large-scale integration, integrated circuit feature size persistently reduce.For
The reduction of meeting market's demand size, the channel length of MOSFET element is also corresponding constantly to be shortened.However, with device channel length
Shortening, the distance between device source electrode and drain electrode also shortens therewith, therefore grid is deteriorated the control ability of raceway groove therewith, grid
The difficulty of voltage pinch off (pinch off) raceway groove is also increasing so that sub-threshold leakage (subthreshold leakage)
Phenomenon, i.e., so-called short-channel effect (SCE：Short-channel effects) it is easier to occur.
Therefore, in order to better conform to the reduction of characteristic size, semiconductor technology gradually starts from planar MOSFET transistor
To the three-dimensional transistor transient with more high effect, such as fin formula field effect transistor (FinFET).The grid of FinFET are extremely
Ultra-thin body (fin) can be controlled from both sides less, it is more stronger to the control ability of raceway groove than grid with planar MOSFET devices,
So as to suppress short-channel effect well；And FinFET has more preferable existing integrated circuit system relative to other devices
Make the compatibility of technology.
Wherein, polysilicon resistance can be largely used in integrated circuits.At present generally by polysilicon resistance is carried out from
To change the resistivity of the polysilicon resistance, the Doped ions can be N-type ion or p-type ion for son doping.
But manufacture cost of the prior art manufacture comprising polysilicon resistance transistor is higher.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of transistor and its manufacture method, reduces and manufacture being manufactured into for transistor
This.
To solve the above problems, the present invention provides a kind of manufacture method of transistor, including：Substrate, the substrate are provided
Including device area and resistance region；The first isolation structure is formed on the substrate of the resistance region；In the device area
Substrate on form pseudo- grid structure, during dummy gate structure is formed, resistance is formed on first isolation structure
Structure；Source and drain doping area is formed in the substrate of dummy gate structure both sides；Ion doping is carried out to the electric resistance structure, to adjust
Whole electric resistance structure resistance value；Annealing process processing is carried out, to activate the ion in the ion and electric resistance structure of source and drain doped region；Remove
Dummy gate structure；Gate structure is formed in dummy gate structure situ.
Optionally, described the step of carrying out annealing process processing to transistor, includes：Using spike annealing or laser annealing
Mode carries out annealing process processing.
Optionally, the annealing process is spike annealing, and the temperature of the annealing process is 950-1100 DEG C.
Optionally, the annealing process is laser annealing, and the temperature of the annealing process is 1200-1300 DEG C.
Optionally, described the step of carrying out ion doping to electric resistance structure, includes：N-type ion is carried out to the electric resistance structure
Doping；Alternatively, p-type ion doping is carried out to the electric resistance structure.
Optionally, described the step of carrying out ion doping to electric resistance structure, includes：To described by the way of ion implanting
Electric resistance structure carries out ion doping.
Optionally, the ion gun of the ion implanting is BF2, the energy range of ion implanting is 2-100keV, dosage model
Enclose for 1.0E13-1.0E16atm/cm2；Alternatively, the ion gun of the ion implanting is B, the energy range of ion implanting is 2-
100keV, dosage range 1.0E13-1.0E16atm/cm2。
Optionally, the ion gun of the ion implanting is P, and the energy range of ion implanting is 2-100keV, dosage range
For 1.0E13-1.0E16atm/cm2；Alternatively, the ion gun of the ion implanting is As, the energy range of ion implanting is 2-
100keV, dosage range 1.0E13-1.0E16atm/cm2。
Optionally, the step of offer substrate includes：Multiple discrete fins are formed on the substrate of the device area
Portion；Described the step of forming the first isolation structure in the substrate of resistance region, includes：Forming the process of the first isolation structure
In, form the second isolation structure in the substrate between the device area fin；It is described to form pseudo- grid structure in device area
The step of include：It is developed across the fin and covers the atop part of the fin and sidewall surfaces form pseudo- grid structure；Institute
Stating the step of source and drain doping area is formed in the substrate of pseudo- grid structure both sides includes：The shape in the fin of dummy gate structure both sides
Into source and drain doping area.
Optionally, it is described that pseudo- grid structure, and the shape on first isolation structure are formed on the substrate of device area
Include into the step of electric resistance structure：Form the polysilicon film of covering substrate；Hard mask layer is formed on the polysilicon film；With institute
It is mask to state hard mask layer, etches the polysilicon film, the first polysilicon layer is formed on the first isolation structure respectively, in device
The second polysilicon layer is formed on area substrate, first polysilicon layer is used to form electric resistance structure, second polysilicon layer
For forming pseudo- grid structure.
Optionally, after forming source and drain doping area in the substrate of dummy gate structure both sides, the electric resistance structure is carried out
Before ion doping, the manufacture method further includes：Interlayer dielectric layer is formed on the substrate of the resistance region and device area,
The interlayer dielectric layer exposes dummy gate structure and electric resistance structure.
Optionally, described the step of carrying out ion doping to electric resistance structure, includes：In the inter-level dielectric of the device area
Graph layer is formed on layer, the graph layer covers the device area and exposes the resistance region；Using the graph layer to cover
Film, removes the hard mask layer at the top of the electric resistance structure, is formed and exposed at the top of the electric resistance structure in the interlayer dielectric layer
First opening；Ion doping is carried out to the electric resistance structure of first open bottom.
Optionally, the material of the hard mask layer is silicon nitride.
Optionally, the technique for removing the hard mask layer at the top of electric resistance structure is dry etching, the dry etching
Technological parameter is：The gas flow of carbon tetrafluoride is 5sccm to 100sccm, the gas flow of fluoromethane for 8sccm extremely
50sccm, the gas flow of oxygen are 10sccm to 100sccm, and sputtering power is 50w to 300w, DC voltage for 30V extremely
200V, chamber pressure are 10mToor to 2000mToor, and the process time is 4s to 50s.
Optionally, described the step of removing pseudo- grid structure, includes：Remove the hard mask layer of pseudo- grid structural top；Remove pseudo- grid
Structure, forms the second opening in the interlayer dielectric layer；It is described pseudo- grid structure situ formed gate structure the step of
Including：Gate structure is formed in the described second opening.
Optionally, after the progress annealing process processing, before removing dummy gate structure, the manufacture method further includes：
Protective layer is formed on the electric resistance structure.
Optionally, the material of the protective layer is silica, silicon oxynitride, silicon oxide carbide, carbonitride of silicium or carbon nitrogen oxidation
Silicon.
Optionally, the technique for forming protective layer is chemical vapor deposition method.
Optionally, the material of the protective layer is silica；The technological parameter of the chemical vapor deposition method includes：Instead
It is tetraethoxysilane and oxygen to answer gas, and reaction temperature is 300 DEG C to 500 DEG C, and pressure is 3mTorr to 200mTorr, wherein
The gas flow of tetraethoxysilane is 100sccm to 8000sccm.
Correspondingly, the present invention, which provides a kind of use, is previously formed the transistor that method is formed.
Compared with prior art, technical scheme has the following advantages：
After the present invention forms source and drain doping area in the substrate of pseudo- grid structure both sides, ion doping is carried out to electric resistance structure,
Then annealing process processing is together carried out to source and drain doping area and electric resistance structure, to activate the ion of source and drain doped region and resistance junction
Ion in structure.And existing technical solution is that after forming source and drain doping area in the substrate of pseudo- grid structure both sides, source and drain is mixed
Miscellaneous area carries out the first annealing process processing；After the processing of the first annealing process, ion doping is carried out to electric resistance structure；To resistance junction
Structure carries out the second annealing process processing, and compared with existing technical solution, the present invention has only carried out an annealing process processing, from
And the heat budget of transistor manufacture is reduced, and the energy has been saved, and technological process is simplified, thereby reduce the system of transistor
Cause this.
In addition, technical solution of the present invention has only carried out an annealing process processing, reduce and transistor progress high temperature is added
The number of heat treatment, so as to reduce the heat budget of transistor, and less heat budget is difficult to the decline that causes device performance, from
And improve the electric property and stability of transistor.
The present invention provides a kind of transistor formed using above-mentioned forming method, due to forming the mistake of the transistor
An annealing process processing has only been carried out in journey, so as to reduce the heat budget of transistor manufacture, and has saved the energy, and simplify
Technological process, thereby reduces the manufacture cost of transistor.
Brief description of the drawings
Fig. 1 to Figure 11 be transistor of the present invention one embodiment of manufacture method in each step counter structure schematic diagram.
Embodiment
From background technology, manufacture cost of the prior art manufacture comprising polysilicon resistance transistor is higher.With reference to one
The reason for manufacturing process analyzing crystal control of kind transistor causes this higher.
The manufacturing process of the transistor, including：Substrate is provided, the substrate includes device area and resistance region；
Isolation structure is formed on the substrate of the resistance region；Pseudo- grid structure is formed on the substrate of the device area；Forming institute
During stating pseudo- grid structure, electric resistance structure is formed on the isolation structure；The shape in the substrate of dummy gate structure both sides
Into source and drain doping area；First annealing process processing is carried out to source and drain doping area, to activate the ion of source and drain doped region；Moved back first
After ignition technique processing, ion doping is carried out to the electric resistance structure, to adjust electric resistance structure resistance value；The electric resistance structure is carried out
Second annealing process processing, to activate the ion in electric resistance structure；Remove dummy gate structure；In dummy gate structure original position
Place forms gate structure.
In the manufacturing process, source and drain doping area has been carried out the first annealing process processing after, electric resistance structure is carried out from
Sub- doping process, has then carried out electric resistance structure the processing of the second annealing process, due to having carried out twice annealing process, from
And the heat budget that result in transistor manufacture is higher, and since the process costs of annealing process processing are higher, correspondingly, cause crystalline substance
The manufacture cost of body pipe is higher.
In addition, transistor is carried out twice annealing process, the heat budget of transistor is added, and excessive heat budget
The performance degradation of device can be caused, so as to reduce the electric property and stability of transistor.
In order to solve the above technical problem, the present invention provides a kind of manufacture method of transistor, including：Substrate is provided,
The substrate includes device area and resistance region；The first isolation structure is formed on the substrate of the resistance region；Described
Pseudo- grid structure is formed on the substrate of device area, during dummy gate structure is formed, on first isolation structure
Form electric resistance structure；Source and drain doping area is formed in the substrate of dummy gate structure both sides；Ion is carried out to the electric resistance structure
Doping, to adjust electric resistance structure resistance value；Annealing process processing is carried out, to activate in the ion and electric resistance structure of source and drain doped region
Ion；Remove dummy gate structure；Gate structure is formed in dummy gate structure situ.
After the present invention forms source and drain doping area in the substrate of pseudo- grid structure both sides, ion doping is carried out to electric resistance structure,
Then annealing process processing is together carried out to source and drain doping area and electric resistance structure, to activate the ion of source and drain doped region and resistance junction
Ion in structure.Scheme compared to existing technology：After forming source and drain doping area in the substrate of pseudo- grid structure both sides, source and drain is mixed
Miscellaneous area carries out the first annealing process processing；After the processing of the first annealing process, ion doping is carried out to electric resistance structure；To resistance junction
Structure carries out the second annealing process processing, and The present invention reduces an annealing process to be handled, so as to reduce the heat of transistor fabrication
Budget, has saved the energy, and simplifies technological process, thereby reduces the manufacture cost of transistor.
In addition, technical solution of the present invention reduces the heat budget of transistor fabrication, and less heat budget due to reducing
It is difficult to the decline for causing device performance, so as to improve the electric property and stability of transistor.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 11 be transistor of the present invention one embodiment of manufacture method in each step counter structure schematic diagram.This reality
Example is applied by taking fin formula field effect transistor as an example.But it should be recognized that the manufacturing method of the present invention can be also used for other partly leading
Body device, such as：Planar ransistor.
With reference to reference to figure 1 and Fig. 2, wherein, Fig. 1 is the stereogram (only illustrating two fins) of semiconductor structure, and Fig. 2 is
Cross-sectional views of the Fig. 1 along AA1 directions, there is provided substrate 100, the substrate 100 include device area (not shown) and electricity
Hinder region (not shown).
In the present embodiment, the substrate 100 of the device area is used to form core devices, and the resistance region is used to be formed
Electric resistance structure.In other embodiments, the substrate of the device area can be also used for being formed peripheral devices (such as：Input/defeated
Go out device).
In the present embodiment, the substrate 100 is silicon substrate.In other embodiments, the substrate can also be germanium, germanium
Silicon, carborundum, GaAs or gallium indium, the substrate can also be the germanium lining on silicon substrate or insulator on insulator
Bottom.
In the present embodiment, described the step of providing substrate 100, includes：Formed on the substrate 100 of the device area more
A discrete fin 110.
Specifically, the step of forming the substrate 100 and fin 110 includes：Initial substrate is provided, in the initial substrate
It is upper to form patterned first hard mask layer 200；It is mask with first hard mask layer 200, etches the initial substrate, shape
Into multiple discrete protrusions；Initial substrate after etching includes device area and resistance area as substrate 100, the substrate 100
Domain, the protrusion on the device area substrate 100 is fin 110.
With reference to figure 3, the first isolation structure 101 is formed on the substrate 100 of the resistance region.
It is described to include form the first isolation structure 101 on the substrate 100 of resistance region the step of in the present embodiment：
During forming the first isolation structure 101, the second isolation structure 111 is formed between the fin 110 of the device area.
First isolation structure 101 provides technique platform to be subsequently formed electric resistance structure, and is used for resistance region device
With the buffer action of device area device, second isolation structure 111 be used for risen between the adjacent fin of device area 110 every
From effect.
In the present embodiment, the material of 101 and second isolation structure 111 of the first isolation structure is silica.At other
In embodiment, the material of first isolation structure and the second isolation structure can also be silicon nitride or silicon oxynitride.
It should be noted that in the present embodiment, 101 and second isolation structure 111 of the first isolation structure is shallow trench
Isolation structure.In other embodiments, first isolation structure and the second isolation structure can also be that localized oxidation of silicon is isolated
Structure.
With reference to reference to figure 4 and Fig. 5, Fig. 5 be based on cross-sectional views of the Fig. 4 along BB1 (as shown in Figure 1) direction,
Pseudo- grid structure (not indicating) is formed on the substrate 100 of the device area II (as shown in Figure 5)；Forming dummy gate structure
During, electric resistance structure 130 is formed on first isolation structure 101.
Dummy gate structure takes up space position to be subsequently formed gate structure.
It should be noted that in the present embodiment, it is described to include the step of device area II forms pseudo- grid structure：Formed horizontal
Across the fin 110 and cover the atop part of the fin 110 and the pseudo- grid structure of sidewall surfaces.
Specifically, the step of forming dummy gate structure and electric resistance structure 130 includes：Form the polycrystalline of covering substrate 100
Silicon fiml 122 (as shown in Figure 4)；The second hard mask layer 210 (as shown in Figure 4) is formed on the polysilicon film 122；With described
Two hard mask layers 210 are mask, etch the polysilicon film 122, form the first polysilicon on the first isolation structure 101 respectively
Layer (not shown), forms the second polysilicon layer (not shown), first polysilicon layer is used on II substrate 100 of device area
Electric resistance structure 130 is formed, second polysilicon layer is used to form pseudo- grid structure.
In the present embodiment, the material of second hard mask layer 210 is silicon nitride.In other embodiments, described second
The material of hard mask layer can also be silica, silicon oxynitride, carbonitride of silicium or carbon silicon oxynitride.
In the present embodiment, dummy gate structure includes pseudo- gate oxide 120 (as shown in Figure 5), and positioned at the pseudo- grid
The pseudo- gate electrode layer 121 on 120 surface of oxide layer.
It should be noted that the puppet gate electrode layer 121 is formed by the second polysilicon layer, and correspondingly, in the present embodiment, institute
It is polycrystalline silicon material to state pseudo- gate electrode layer 121.In other embodiments, pseudo- gate electrode layer can be with silica, silicon nitride, nitrogen oxygen
The materials such as SiClx, carborundum, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon.
It should also be noted that, after forming dummy gate structure and electric resistance structure 130, retain positioned at dummy gate structure and
Second hard mask layer 210 at the top of electric resistance structure 130.Subsequently when carrying out flatening process, second hard mask layer 210 is used
In the stop position for defining flatening process.
It should also be noted that, in the present embodiment, the device area II includes the first device area III (such as Fig. 5 institutes
Show) and the second device area IV (as shown in Figure 5), the first device area III substrates 100 are used to form P-type device, described
Second device area IV substrates 100 are used to form N-type device.
In other embodiments, the first device area substrate can be used for forming N-type device, second device region
Domain substrate is used to form P-type device, alternatively, the first device area substrate and the second device area substrate are used to form N
Type device, alternatively, the first device area substrate and the second device area substrate are used to form P-type device.
With reference to figure 6, source and drain doping area (not indicating) is formed in the substrate 100 of dummy gate structure both sides.
In the present embodiment, the step of forming the source and drain doping area, includes：In the fin 110 of dummy gate structure both sides
Form source and drain doping area.
Specifically, photoresist layer (not shown), the light are formed on the first isolation structure 101 of the resistance region I
Photoresist layer covers the electric resistance structure 130；Using the photoresist layer as mask, in the fin 110 of dummy gate structure both sides
Groove (not shown) is formed, filling semiconductor material forms stressor layers 150 in the groove using epitaxy technique；Answered described
Doped ions form source and drain doping area in power floor 150；Remove the photoresist layer.
In the present embodiment, use doping treatment in situ to form the source and drain during the stressor layers 150 are formed and mix
Miscellaneous area.In other embodiments, the stressor layers can also be doped with processing to be formed after the stressor layers are formed
State source and drain doping area.
It should be noted that after forming source and drain doping area in the substrate 100 of dummy gate structure both sides, the manufacturer
Method further includes：Interlayer dielectric layer 102, the inter-level dielectric are formed on the substrate 100 of the resistance region I and device area II
Layer 102 exposes dummy gate structure and electric resistance structure 130.
The material of the interlayer dielectric layer 102 is insulating materials, in the present embodiment, the material of the interlayer dielectric layer 102
For silica.In other embodiments, the material of the interlayer dielectric layer can also be silicon nitride, silicon oxynitride, silicon oxide carbide,
Carbonitride of silicium or carbon silicon oxynitride.
Specifically, on the substrate 100 of the resistance region I and device area II formed interlayer dielectric layer 102 the step of
Including：Interlayer deielectric-coating is formed on the substrate 100, is higher than second hard mask layer 210 at the top of the inter-level dielectric film
Top；Using flatening process, the inter-level dielectric film higher than the top of the second hard mask layer 210 is removed, forms inter-level dielectric
Layer 102, the top of interlayer dielectric layer 102 are flushed with the top of the second hard mask layer 210.
With reference to reference to figure 7 and Fig. 8, ion doping 132 (with reference to figure 8) is carried out to the electric resistance structure 130, to adjust resistance
130 resistance value of structure.
By carrying out ion doping 132 to the electric resistance structure 130 to change the resistivity of the electric resistance structure 130, and
Doping concentration is higher, and resistivity is lower.
In the present embodiment, described the step of carrying out ion doping 132 to electric resistance structure 130, includes：In the device area
Graph layer 220 (with reference to figure 7) is formed on II interlayer dielectric layer 102, the graph layer 220 covers the device area II and reveals
Go out the electric resistance structure 130；It is mask with the graph layer 220, removes second hard mask layer at the top of electric resistance structure 130
210 (as shown in Figure 6), form the first opening 131 for exposing the top of electric resistance structure 130 in the interlayer dielectric layer 102
(with reference to figure 7)；Ion doping 132 is carried out to the electric resistance structure 130 of the described first 131 bottoms of opening.
First opening 131 is used to provide locus for the doping process of the subsequently electric resistance structure 130, and described the
One opening 131 is additionally operable to be subsequently formed for protecting the protective layer at the top of electric resistance structure 130 to provide locus.
In the present embodiment, the material of second hard mask layer 210 is silicon nitride, removed using dry etch process described in
Second hard mask layer 210 at the top of electric resistance structure 130.Specifically, the technological parameter of the dry etch process is：Carbon tetrafluoride
Gas flow be 5sccm to 100sccm, the gas flow of fluoromethane is 8sccm to 50sccm, and the gas flow of oxygen is
10sccm to 100sccm, sputtering power are 50w to 300w, and DC voltage is 30V to 200V, chamber pressure for 10mToor extremely
2000mToor, process time are 4s to 50s.
In other embodiments, wet-etching technology can also be used；Alternatively, dry etch process and wet-etching technology
The technique being combined, removes the second hard mask layer at the top of the electric resistance structure.
It should be noted that described the step of carrying out ion doping 132 to electric resistance structure 130, includes：To the resistance junction
Structure 130 carries out p-type ion doping, that is to say, that carries out p-type ion doping to the electric resistance structure 130 of the first 131 bottoms of opening.Phase
Ying Di, the electric resistance structure 130 after doping are p-type electric resistance structure.
In the present embodiment, ion doping 132 is carried out to the electric resistance structure 130 by the way of ion implanting.In order to incite somebody to action
The resistivity of the electric resistance structure 130 is adjusted to desired value, and the ion energy and dosage of the ion implanting need to be controlled reasonable
In the range of.Specifically, the ion gun of the ion implanting is BF2, the energy range of ion implanting is 2-100keV, dosage range
For 1.0E13-1.0E16atm/cm2.In other embodiments, the ion gun of the ion implanting can also be B, ion implanting
Energy range be 2-100keV, dosage range 1.0E13-1.0E16atm/cm2。
In other embodiments, described the step of carrying out ion doping 132 to electric resistance structure 130, includes：To the resistance
Structure 130 carries out N-type ion doping, that is to say, that carries out N-type ion doping to the electric resistance structure 130 of the first 131 bottoms of opening.
Correspondingly, the electric resistance structure 130 after doping is N-type electric resistance structure.
Specifically, ion doping is carried out to the electric resistance structure 130 by the way of ion implanting.In order to by the resistance
The resistivity of structure 130 is adjusted to desired value, and the ion energy and dosage of the ion implanting need to control in the reasonable scope.Tool
Body, the ion gun of the ion implanting is P, and the energy range of ion implanting is 2-100keV, dosage range 1.0E13-
1.0E16atm/cm2；Alternatively, the ion gun of the ion implanting is As, the energy range of ion implanting is 2-100keV, dosage
Scope is 1.0E13-1.0E16atm/cm2。
With reference to figure 9, annealing process processing is carried out, to activate the ion in the ion of source and drain doped region and electric resistance structure 130.
On the one hand, being handled by the annealing process makes Doped ions relaxation in the electric resistance structure 130 to lattice position,
So as to fulfill activation, and then effectively change the resistivity of the electric resistance structure 130.On the other hand, the annealing process is passed through
Processing makes the Doped ions in the source and drain doping area be activated, and annealing process processing can also repair the source and drain
Lattice damage in doped region, and then improve the electric property of transistor.
It should be noted that after forming source and drain doping area and completing to 130 ion doping 132 of electric resistance structure, source and drain is mixed
Miscellaneous area and electric resistance structure 130 carry out annealing process processing jointly, reduce the heat budget of transistor manufacture, have saved the energy, and
And technological process is simplified, thereby reduce the manufacture cost of transistor.
In addition, source and drain doping area and electric resistance structure 130 are subjected to annealing process processing jointly, so that reducing reduces crystalline substance
The heat budget that body pipe makes, and less heat budget is difficult to the decline that causes device performance, and then improve the electricity of transistor
Performance and stability.
It should be noted that in the present embodiment, annealing process before processing is being carried out, is removing the top of electric resistance structure 130
Graph layer 220 (with reference to figure 8).
It is described spike annealing, laser annealing mode to be used to carry out annealing process transistor progress annealing process processing
Processing.In the present embodiment, annealing process processing is carried out to transistor using spike annealing mode.
If the technological temperature of spike annealing is excessive, transistor is easily set to deform and performance degradation, so as to influence crystal
The electric property of pipe, if the technological temperature of spike annealing is too low, is difficult to activate the electric resistance structure 130 and source and drain doping area
Doped ions, and be difficult to repair the lattice damage in the source and drain doping area.Therefore, in the present embodiment, the spike annealing
Technological temperature is 950-1100 DEG C.
It should be noted that in other embodiments, laser annealing mode can also be used to carry out lehr attendant to transistor
Skill processing.
If the technological temperature of laser annealing is excessive, transistor is easily set to deform and performance degradation, so as to influence crystal
The electric property of pipe, if the technological temperature of laser annealing is too low, is difficult to realize activate the electric resistance structure 130 and source and drain doping
The purpose of area's Doped ions, and be difficult to repair the lattice damage in the source and drain doping area.Specifically, the work of the laser annealing
Skill temperature is 1200-1300 DEG C.
With reference to figure 10, dummy gate structure (not marking) is removed.
Specifically, described the step of removing pseudo- grid structure, includes：Remove the second hard mask layer 210 of pseudo- grid structural top
(with reference to figure 9)；Pseudo- grid structure is removed, the second opening 301 is formed in the interlayer dielectric layer 102.
Second opening 301 provides locus to be subsequently formed gate structure.
In the present embodiment, the substrate 100 of the device area II is used to form core devices；Correspondingly, it is described to remove puppet
The step of grid structure, includes：Etching removes the pseudo- gate electrode layer 121 of the first device area III and the second device area IV
(as shown in Figure 9) and pseudo- gate oxide 120 (as shown in Figure 9), forms in the interlayer dielectric layer 102 and exposes the fin
110 the second opening 301.
In other embodiments, the substrate of the device area be used for formed peripheral devices (such as：Input/output device
Part), correspondingly, in the step of removing dummy gate structure, only remove the pseudo- gate electrode layer, the shape in the interlayer dielectric layer
Into the second opening for exposing the pseudo- gate oxide, a part of the puppet gate oxide as the gate dielectric layer of peripheral devices.
In the present embodiment, in the processing step with along with, etching removes the first device area III and the second device region
The pseudo- grid structure of domain IV.Specifically, the etching technics is dry etch process.
In other embodiments, can also be combined using wet-etching technology or dry etch process and wet etching
Technique, etching remove the pseudo- grid structure of first device area and the second device area.
It should be noted that after the progress annealing process processing, before removing dummy gate structure, the manufacture method is also
Including：Protective layer 103 is formed on the electric resistance structure 130.
The protective layer 103 is used in subsequently the technical process of dummy gate structure is removed, and protects the electric resistance structure
130, avoid the electric resistance structure 130 from being lost or be removed.
In the present embodiment, the material of the protective layer 103 is silica.In other embodiments, the material of the protective layer
Material can also be silicon oxynitride, silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.
In the present embodiment, the technique for forming the protective layer 103 is chemical vapor deposition method.Specifically, the chemistry
The technological parameter of gas-phase deposition includes：Reacting gas is tetraethoxysilane and oxygen, and reaction temperature is 300 DEG C to 500
DEG C, pressure is 3mTorr to 200mTorr, and wherein the gas flow of tetraethoxysilane is 100sccm to 8000sccm.
With reference to figure 11, gate structure 160 is formed in dummy gate structure situ.Correspondingly, in the described second opening
Gate structure 160 is formed in 301 (with reference to figures 10).
In the present embodiment, the gate structure 160 is metal gate structure.Specifically, the step of metal gate structure is formed
Suddenly include：Gate dielectric film (not shown) is formed on the described second 301 bottoms of opening and side wall, the gate medium tunic also covers
The top of interlayer dielectric layer 102；Work function film (not shown) is formed on the gate dielectric film；Form the work function film
Afterwards, the metal film (not shown) of full second opening 301 of filling is formed, the top of the metal film is higher than the inter-level dielectric
The top of layer 102；Grinding removes the metal film higher than the top of interlayer dielectric layer 102, forms metal layer 163；And grind and go
Except the work function film and gate dielectric film higher than the top of the interlayer dielectric layer 102, formed positioned at the described second 301 bottoms of opening and
The gate dielectric layer 161 of side wall and the work-function layer 162 on the gate dielectric layer 161.
In the present embodiment, the material of the gate dielectric layer 161 is high-k gate dielectric material, wherein, high-k gate dielectric material refers to
, for relative dielectric constant more than the gate dielectric material of silica relative dielectric constant, high-k gate dielectric material can be HfO2、
HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3.In the present embodiment, the material of the gate dielectric layer 161 is
HfO2。
In the present embodiment, the material of the metal layer 163 is W.In other embodiments, the material of the metal layer may be used also
Think Al, Cu, Ag, Au, Pt, Ni or Ti.
In other embodiments, the substrate of the device area be used for formed peripheral devices (such as：Input/output device
Part), remove dummy gate structure the step of in, retain positioned at second open bottom pseudo- gate oxide；Correspondingly, formed
In the step of gate dielectric layer, on the pseudo- gate oxide and the second opening sidewalls form the gate dielectric layer.
In the present embodiment, after forming source and drain doping area in the substrate 100 (as shown in Figure 1) of pseudo- grid structure both sides, to electricity
The progress ion doping 132 (as shown in Figure 8) (as shown in Figure 5) of structure 130 is hindered, then to source and drain doping area and electric resistance structure 130
Annealing process processing is together carried out, to activate the ion in the ion of source and drain doped region and electric resistance structure 130.And existing technology
Scheme is that after forming source and drain doping area in the substrate of pseudo- grid structure both sides, source and drain doping area is carried out at the first annealing process
Reason；After the processing of the first annealing process, ion doping is carried out to electric resistance structure；Electric resistance structure is carried out at the second annealing process
Reason, compared with existing technical solution, the present invention has only carried out an annealing process processing, so as to reduce transistor manufacture
Heat budget, and the energy has been saved, and technological process is simplified, thereby reduce the manufacture cost of transistor.
In addition, reduce and transistor is heated at high temperature due to reducing an annealing process processing in the present embodiment
Number of processing, so as to reduce the heat budget of transistor, excessive heat budget can cause the performance degradation of device, and then improve
Transistor electricity performance and stability.
With continued reference to Figure 11, the structure diagram of one embodiment of transistor of the present invention is shown.Correspondingly, the present invention provides
A kind of transistor formed using forming method described in previous embodiment.
Due to only having carried out an annealing process processing during the transistor is formed, so as to reduce transistor
The heat budget of manufacture, and the energy has been saved, and technological process is simplified, thereby reduce the manufacture cost of transistor.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the scope of restriction.
Claims (20)
- A kind of 1. manufacture method of transistor, it is characterised in that including：Substrate is provided, the substrate includes device area and resistance region；The first isolation structure is formed in the substrate of the resistance region；Pseudo- grid structure is formed on the substrate of the device area, during dummy gate structure is formed,Electric resistance structure is formed on first isolation structure；Source and drain doping area is formed in the substrate of dummy gate structure both sides；Ion doping is carried out to the electric resistance structure, to adjust electric resistance structure resistance value；Annealing process processing is carried out, to activate the ion in the ion and electric resistance structure of source and drain doped region；Remove dummy gate structure；Gate structure is formed in dummy gate structure situ.
- 2. the manufacture method of transistor as claimed in claim 1, it is characterised in that described to be carried out to transistor at annealing process The step of reason, includes：Annealing process processing is carried out using spike annealing or laser annealing mode.
- 3. the manufacture method of transistor as claimed in claim 2, it is characterised in that the annealing process is spike annealing, institute The temperature for stating annealing process is 950-1100 DEG C.
- 4. the manufacture method of transistor as claimed in claim 2, it is characterised in that the annealing process is laser annealing, institute The temperature for stating annealing process is 1200-1300 DEG C.
- 5. the forming method of transistor as claimed in claim 1, it is characterised in that described that ion doping is carried out to electric resistance structure The step of include：N-type ion doping is carried out to the electric resistance structure；Alternatively, p-type ion doping is carried out to the electric resistance structure.
- 6. the manufacture method of transistor as claimed in claim 1, it is characterised in that described that ion doping is carried out to electric resistance structure The step of include：Ion doping is carried out to the electric resistance structure by the way of ion implanting.
- 7. the manufacture method of transistor as claimed in claim 6, it is characterised in that the ion gun of the ion implanting is BF2, The energy range of ion implanting is 2-100keV, dosage range 1.0E13-1.0E16atm/cm2；Alternatively, the ion gun of the ion implanting is B, the energy range of ion implanting is 2-100keV, and dosage range is 1.0E13-1.0E16atm/cm2。
- 8. the manufacture method of transistor as claimed in claim 6, it is characterised in that the ion gun of the ion implanting is P, from The energy range of son injection is 2-100keV, dosage range 1.0E13-1.0E16atm/cm2；Alternatively, the ion gun of the ion implanting is As, the energy range of ion implanting is 2-100keV, and dosage range is 1.0E13-1.0E16atm/cm2。
- 9. the manufacture method of transistor as claimed in claim 1, it is characterised in that described the step of providing substrate includes： Multiple discrete fins are formed on the substrate of the device area；Described the step of forming the first isolation structure in the substrate of resistance region, includes：Forming the process of the first isolation structure In, form the second isolation structure in the substrate between the device area fin；It is described to include the step of device area forms pseudo- grid structure：It is developed across the fin and covers the part of the fin Top and sidewall surfaces form pseudo- grid structure；Described the step of source and drain doping area is formed in the substrate of pseudo- grid structure both sides, includes：Fin in dummy gate structure both sides Source and drain doping area is formed in portion.
- 10. the manufacture method of transistor as claimed in claim 1, it is characterised in that the shape on the substrate of device area Include into pseudo- grid structure, and in the step of formation electric resistance structure on first isolation structure：Form the polycrystalline of covering substrate Silicon fiml；Hard mask layer is formed on the polysilicon film；Using the hard mask layer as mask, the polysilicon film is etched, forms the first polysilicon on the first isolation structure respectively Layer, forms the second polysilicon layer on device area substrate, and first polysilicon layer is used to being formed electric resistance structure, and described second Polysilicon layer is used to form pseudo- grid structure.
- 11. the manufacture method of transistor as claimed in claim 10, it is characterised in that the substrate in dummy gate structure both sides Behind middle formation source and drain doping area, before carrying out ion doping to the electric resistance structure, the manufacture method further includes：In the resistance Interlayer dielectric layer is formed on the substrate of region and device area, the interlayer dielectric layer exposes dummy gate structure and resistance junction Structure.
- 12. the manufacture method of transistor as claimed in claim 11, it is characterised in that described to mix electric resistance structure progress ion Miscellaneous step includes：Graph layer is formed on the interlayer dielectric layer of the device area, the graph layer covers the device region Simultaneously expose the resistance region in domain；Using the graph layer as mask, the hard mask layer at the top of the electric resistance structure is removed, is formed in the interlayer dielectric layer Expose the first opening at the top of the electric resistance structure；Ion doping is carried out to the electric resistance structure of first open bottom.
- 13. the manufacture method of transistor as claimed in claim 12, it is characterised in that the material of the hard mask layer is nitridation Silicon.
- 14. the manufacture method of transistor as claimed in claim 12, it is characterised in that hard at the top of the removal electric resistance structure The technique of mask layer is dry etching, and the technological parameter of the dry etching is：The gas flow of carbon tetrafluoride for 5sccm extremely 100sccm, the gas flow of fluoromethane is 8sccm to 50sccm, and the gas flow of oxygen is 10sccm to 100sccm, sputtering Power is 50w to 300w, and DC voltage is 30V to 200V, and chamber pressure is 10mToor to 2000mToor, process time 4s To 50s.
- 15. the manufacture method of transistor as claimed in claim 12, it is characterised in that described the step of removing pseudo- grid structure wraps Include：Remove the hard mask layer of pseudo- grid structural top；Pseudo- grid structure is removed, the second opening is formed in the interlayer dielectric layer；It is described to include the step of pseudo- grid structure situ forms gate structure：Grid knot is formed in the described second opening Structure.
- 16. the manufacture method of transistor as claimed in claim 1, it is characterised in that after the progress annealing process processing, go Before dummy gate structure, the manufacture method further includes：Protective layer is formed on the electric resistance structure.
- 17. the manufacture method of transistor as claimed in claim 16, it is characterised in that the material of the protective layer is oxidation Silicon, silicon oxynitride, silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.
- 18. the forming method of transistor as claimed in claim 16, it is characterised in that the technique for forming protective layer is change Learn gas-phase deposition.
- 19. the manufacture method of transistor as claimed in claim 18, it is characterised in that the material of the protective layer is oxidation Silicon；The technological parameter of the chemical vapor deposition method includes：Reacting gas is tetraethoxysilane and oxygen, and reaction temperature is 300 DEG C to 500 DEG C, pressure is 3mTorr to 200mTorr, wherein the gas flow of tetraethoxysilane for 100sccm extremely 8000sccm。
- A kind of 20. transistor formed such as any one of claim 1 to 19 forming method.
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| CN109637979A (en) * | 2018-12-19 | 2019-04-16 | 上海华力集成电路制造有限公司 | The manufacturing method of grid |
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| US20120217586A1 (en) * | 2011-02-25 | 2012-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits with resistors and methods of forming the same |
| CN104733314A (en) * | 2013-12-18 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN102237310A (en) * | 2010-04-29 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Integrated circuit and method of manufacturing same |
| US20120217586A1 (en) * | 2011-02-25 | 2012-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits with resistors and methods of forming the same |
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