CN109637575B - Double-data reading verification method and equipment for flash memory storage unit - Google Patents
Double-data reading verification method and equipment for flash memory storage unit Download PDFInfo
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Abstract
The embodiment of the invention provides a method and equipment for double-data reading verification. The method is mainly used in the program verification operation of the flash memory storage unit so as to quickly find the high threshold value storage unit and the low threshold value storage unit. In the subsequent programming process, the same word line voltage and different programming bit line voltages are adopted for the high-threshold memory cells and the low-threshold memory cells, and the bit line voltage adopted for the high-threshold memory cells is greater than the bit line voltage adopted for the low-threshold memory cells, so that the threshold variation of the high-threshold memory cells is reduced, and the high-threshold memory cells and the low-threshold memory cells can synchronously reach a programming state (P state).
Description
Technical Field
The present invention relates to the field of flash memory cells, and more particularly, to a method and apparatus for dual data read verification of flash memory cells.
Background
Fig. 1 shows a schematic diagram of threshold variation of a flash memory unit cell. As shown in fig. 1, the erase state (E state) device is programmed to a program state (P state), a voltage stepped by an incremental step program pulse Δ ISPP is applied to a word line of the flash memory unit, and a bit line voltage (Vbl) is applied to a bit line of the flash memory unit to program. The larger Δ ISPP that programs a device, the shorter the programming time, but the less accurate (widening the P-state); the smaller the Δ ISPP, the more programming steps are required, the longer the programming time, but the higher the programming accuracy.
If both high speed and high accuracy are desired, it is desirable to achieve high accuracy by adjusting the bit line voltage (Vbl) of the devices in a particular region while ensuring a high Δ ISPP (i.e., speed is ensured). FIG. 2 illustrates the division of memory unit elements into high threshold memory cells (HV) according to their thresholdT) And a low threshold memory cell (LV)T). High threshold memory cells refer to memory cells having threshold values distributed in a region less than, but close to, the threshold voltage of the programmed state. Low threshold memory cell (LV)TArea cells) refers to the threshold of a memory cell having a threshold distribution less than the high thresholdA memory cell of a region of the value voltage. For this purpose, the HV needs to be first identifiedTDevice and LVTDevice, then to HVTDevice and LVTThe device employs different programming conditions. HV (high voltage) deviceTDevice and LVTCommon to the programming conditions of the devices is that the same ISPP voltage is applied to the word line, with the difference that a different bit line voltage is used than on the bit line, i.e. for HVTThe device uses a high bit line voltage Vbl, while for LVTThe device uses a low bit line voltage Vbl. After entering a programming state, programming the device; then verifying the programming result, and if the verification is passed, finishing the programming; and if the verification fails, increasing the grid voltage of the device by the incremental step programming pulse delta ISPP, and then programming the device.
To distinguish HVTDevice and LVTAnd the device adopts two single data verification operations. That is, during a read operation, the gate terminal of the memory cell is set to be read twice by the VR bitline voltage and the PVR bitline voltage. Since the single data verification method is used twice, two read operations are required to discriminate HVTDevice and LVTThe device takes two reading times, so the time efficiency is not high.
CN102298966A shows a two-time single data verification method for existing programming conditions. To distinguish HVTDevice and LVTThe device, CN102298966A, employs two single data verification operations. Fig. 3 shows a working principle diagram of two single-data verifications, and fig. 4 shows a flow chart of a two-single-data verification method. That is, during a read operation, the gate terminal of the memory cell is set to be read twice by the VR bitline voltage and the PVR bitline voltage. Assume that when the VTH of the device is less than the gate voltage at read, the data read is 1: then if D1 is 0, the device is in the program region P; if D1 is 1 and D2 is 0, then the device is at HVTState; and if D1 is 1 and D2 is 1, then the device is in LVTState. Because the prior art uses two single data verification methods, two read operations are required to distinguish HVTDevice and LVTThe device takes two reading times, soThe time efficiency is not high.
Disclosure of Invention
In order to solve the above technical problem, the present invention provides a method for distinguishing a high threshold device from a low threshold device, that is, a method and an apparatus for dual data read verification of a flash memory cell.
According to one aspect of the present invention, there is provided a dual data read verification method for flash memory cells arranged in an array and connected to corresponding bit lines and word lines, wherein the threshold voltage distribution of high threshold memory cells is less than the programmed state threshold voltage (Vth)VR) But greater than the threshold voltage (V) of the low threshold memory cellPVR) The threshold voltage of the low-threshold memory cell is distributed to be lower than the threshold voltage (V) of the low-threshold memory cellPVR) The program state threshold voltage is a verify voltage, the threshold voltage of the low threshold memory cell is a pre-verify voltage, the method comprising: determining a current threshold voltage of the memory cell; if the current threshold voltage is less than the pre-verification voltage, determining that the memory cell is a low threshold memory cell; determining the memory cell as a high threshold memory cell if the current threshold voltage is greater than or equal to the pre-verify voltage and less than or equal to the verify voltage; determining that the memory cell is in a programmed state if the current threshold voltage is greater than the verify voltage.
Optionally, in the dual data verification mode, two data are read in one program verify operation.
Optionally, the method of setting a program verify voltage on a word line and a normal read voltage on a bit line by obtaining two read results in one read operation to distinguish between a high threshold memory device and a low threshold memory device, the method comprising the following three phases: a pre-charging stage: charging a storage capacitor on a capacitive node (So); a current induction stage: discharging a storage capacitance on a capacitance node (so) by a storage cell, during said discharging: the voltage of the capacitor node (so) and the current, discharge time and pre-charge time of the memory cellVoltage dependence of the capacitive node (so): cSO*(VSO_PRE-VSO(t))＝ICELLT, wherein CSOIs the capacitance on the capacitive node (so), is constant; vSO_PREIs the voltage of the capacitor node (so) during pre-charging, and is also a constant; i isCELLIs the current of the memory cell, related to the threshold of the memory device; vSO(t) is the voltage on the capacitive node (so) at time t; t is the discharge time and the flip-flop voltage V of the latch is knownLATWhen the memory cell current (I) is turned overCELL) Is also constant with time (t); and (3) a discharging stage: each node is discharged after the data latch operation is finished.
Optionally, according to a verification voltage VPVRAnd VVRTwo reference currents I are correspondingly generatedREF_PVRAnd IREF_VRAnd then deducing the corresponding discharge time required for turning over the latch according to the corresponding relation between the current and the discharge time.
Alternatively, setting the current sense time corresponds to setting the reference current, assuming that t is set_PVR-corresponds to IREF_PVRAt t_PVRAt time, if VSO<VLATThen, ICELL>IREF_PVRThreshold value V of memory cellCELL<VPVROn the contrary, if VSO>VLATThen, ICELL<IREF_PVRThreshold value V of memory cellCELL>VPVR. Similarly, set t_VRCorresponds to IREF_VRAt t_VRAt time, if VSO<VLATThen, ICELL>IREF_VRThreshold value V of memory cellCELL<VVROn the contrary, if VSO>VLATThen, ICELL<IREF_VRThreshold value V of memory cellCELL>VVR。
Optionally, during the time of one current sensing, two times of data latching and two times of comparison results latching are performed, and the two results are used to determine the threshold interval of the memory cell.
Optionally, readThe obtained data and the corresponding threshold voltage distribution relation of the storage unit are as follows: let VSO<VLATThe latched data is 1 and vice versa is 0, and the data twice are referred to as D1 and D2, respectively, where D1 corresponds to t_PVRD2 corresponds to t_VR: if D1 is equal to 1 and D2 is equal to 1, the threshold distribution of the memory cell is VCELL<VPVRTherefore, the memory cells are distributed in the low threshold region; if D1 is equal to 0 and D2 is equal to 1, the threshold distribution of the memory cell is VPVR<VCELL<VVRSo that the memory cells are distributed in the high threshold region; if D1 is equal to 0 and D2 is equal to 0, the threshold distribution of the memory cell is VCELL>VPVRTherefore, the memory cells are distributed in the low threshold region; and if D1 is equal to 1 and D2 is equal to 0, invalid data is indicated.
Optionally, the double data verification mode is applied in a two-bit memory cell (MLC) programming mode, and the double data verification mode and the single data verification mode are used in combination by a read mode selector.
Alternatively, for MSB programming in the failed P2 state, a double data verify mode is used for three verify voltages (Vr1, Vr2 and Vr 3; after the P2 state is passed, a single data verify mode is used at Vr 3.
Alternatively, when the P1 state is not passed, the double data verification mode is adopted for all three verification voltages (Vr1, Vr2 and Vr 3); after passing the P1 state, the single data verification mode is used at Vr2 and Vr 3.
Alternatively, when the P1 state is not passed, the double data verification mode is adopted for all three verification voltages (Vr1, Vr2 and Vr 3); after passing the P1 state but not passing the P2 state, using double data verification mode at Vr2 and Vr 3; after passing the P2 state, the single data verification mode is used at Vr 3.
Alternatively, the dual data read verify method can also be applied in a single bit (SLC), three bit (TLC), more bit memory cell programming mode.
Optionally, two latches LATCH are included in the read circuit for storing data for the double data verify mode. Optionally, for the MSB storage structure, four latches LATCH are included in the read circuit to store the MSB, LSB and verified double data, respectively.
According to another aspect of the present invention, there is also provided a dual data read verify device for flash memory cells arranged in an array and connected to corresponding bit lines and word lines, wherein the high threshold cells have threshold voltages distributed less than a programmed state threshold voltage (Vth)VR) But greater than the threshold voltage (V) of the low threshold memory cellPVR) The threshold voltage of the low-threshold memory cell is distributed to be lower than the threshold voltage (V) of the low-threshold memory cellPVR) The program state threshold voltage is a verify voltage, the threshold voltage of the low threshold memory cell is a pre-verify voltage, the dual data read verify device is configured to: determining a current threshold voltage of the memory cell; if the current threshold voltage is less than the pre-verification voltage, determining that the memory cell is a low threshold memory cell; determining the memory cell as a high threshold memory cell if the current threshold voltage is greater than or equal to the pre-verify voltage and less than or equal to the verify voltage; determining that the memory cell is in a programmed state if the current threshold voltage is greater than the verify voltage.
Drawings
Fig. 1 shows a schematic diagram of threshold variation of a flash memory unit cell.
FIG. 2 shows the classification of devices as high threshold devices (HV) according to thresholdT) And low threshold devices (LV)T) Schematic representation of (a).
Fig. 3 shows a working principle diagram of two single data verifications.
FIG. 4 shows a flow diagram of a two-time single data validation method.
FIG. 5 shows a schematic flow chart of a programming operation.
Fig. 6 shows a circuit example of a double data reading method according to an embodiment of the present invention.
Fig. 7 illustrates a timing diagram of a double data reading method according to an embodiment of the present invention.
FIG. 8 shows a threshold distribution map of MLC memory unit cells.
FIG. 9 shows a flow chart of the application of the double data verify mode in MLC programming.
Fig. 10, 11 and 12 illustrate the application of the double data verify mode in MLC programming.
FIG. 13 shows a system framework for the application of the double data verify mode in MLC programming.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The following embodiments will be described with reference to the accompanying drawings for the purpose of explaining the present invention.
The technical solutions of the embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be noted that throughout the drawings, like elements are represented by like or similar reference numerals. It is noted that the terms "a is connected to B" and "a is connected to B" herein, as will be understood by those skilled in the art, may be that a is directly connected to B, or that a is connected to B via one or more other components. In addition, "connected" and "connected" herein may be physically and electrically connected, and may also be electrically coupled or coupled, and the like.
It should be noted that in the context of the present invention, a verify operation refers to an operation that evaluates or improves the threshold voltage exhibited by programmed memory cells with respect to the threshold voltage distribution, while a program operation refers to an operation that changes the threshold voltage of memory cells.
In order to solve the problem of low read efficiency of the double data read verification, an embodiment of the present invention provides a method for double data read verification, which is mainly used in the program verification operation of a flash memory cell to quickly find a memory cell (HVT area cell) with a high threshold. Where a high threshold memory cell refers to a memory cell having a threshold value distributed in an area smaller than but close to the programmed state. What corresponds to this is a low threshold memory cell (LVT zone cell), i.e. a memory cell having a smaller threshold distribution than a high threshold memory cell. In the subsequent programming process, the same word line voltage and different programming bit line voltages are applied to the HVT area cells and the LVT area cells, and the line voltage applied to the HVT area cells is higher than that applied to the LVT area cells, so that the threshold variation of the HVT area cells is reduced, and the HVT area cells and the LVT area cells can reach a programming state (P state) synchronously.
For this purpose, the HV needs to be first identifiedTDevice and LVTDevice, then to HVTDevice and LVTThe device employs different programming conditions. HV (high voltage) deviceTDevice and LVTCommon to the programming conditions of the devices is that the same ISPP voltage is applied to the word line, with the difference that a different bit line voltage is used than on the bit line, i.e. for HVTThe device uses a high Vbl voltage, while for LVTThe device uses a low Vbl voltage.
FIG. 5 shows a schematic flow chart of a programming operation. After entering the programming state, the device is first programmed, as shown in FIG. 5; then verifying the programming result, and if the verification is passed, finishing the programming; if the verification fails, the gate voltage of the device is increased by delta ISPP, and then the device is programmed. If the threshold voltage Vth is larger than VR, the device is in a programming state, and the verification is finished; if VR is>Vth>PVR, indicating that the device is HVTA device using a high Vbl voltage BLFV; if Vth is less than PVR, it indicates that the device is LVTThe device, uses a low Vbl voltage BLPV. As shown in fig. 3, verify operations are performed using the same word line voltage but different bit line voltages for LVT devices and HVT devices.
Fig. 6 shows a circuit example of a double data reading method according to an embodiment of the present invention. As shown in fig. 6, unlike the conventional structure, the circuit of the double data read method according to the embodiment of the present invention includes two Latches (LATCH) for latching two read data in one read operation. The double-data reading verification method provided by the embodiment of the invention is still divided into three time periods of pre-charging, current sensing time and discharging time in time sequence. In the pre-charging phase: charging a capacitance on a capacitance node (so); in the current induction phase: the current on the memory unit element flows through the capacitance on the capacitance node (so), discharging it. The discharge speed is related to the magnitude of the current, and the discharge speed is faster when the current is larger. A charging stage: charging a storage capacitor on a capacitive node (So);
a current induction stage: discharging a storage capacitance on a capacitance node (so) by a storage cell, during said discharging: the voltage magnitude of the so node is related to the current of the memory cell, the discharge time, and the pre-charge is related to the voltage of the capacitor node (so). CSO*(VSO_PRE-VSO(t))＝ICELLT, wherein CSOIs the capacitance on the capacitive node (so), is constant; vSO_PREPrecharge is the voltage of the capacitive node (so), which is constant; i isCELLIs the current of the memory cell, related to the threshold of the memory device; vSO(t) is the voltage on the capacitive node (so) at time t; t is the discharge time. The latch has a known flip voltage of VLATWhen the turning moment corresponds to ICELLAnd time t will be constant.
The current of the memory cell is related to the threshold value thereof, the larger the difference between the threshold value of the memory cell and the read bias condition is, the larger the current is, and the threshold voltage and the read current are in one-to-one correspondence for a given read bias state, according to the verification voltage VPVRAnd VVRTwo reference currents I are correspondingly generatedREF_PVRAnd IREF_VRAnd then deducing the corresponding discharge time required for turning over the latch according to the corresponding relation between the current and the discharge time.
Setting the current sense time corresponds to setting the reference current, assuming that t is set_PVRCorresponds to IREF_PVRAt t_PVRAt time, if VSO<VLATThen, ICELL>IREF_PVRThreshold value V of memory cellCELL<VPVROn the contrary, if VSO>VLATThen, ICELL<IREF_PVRThreshold value V of memory cellCELL>VPVR. Similarly, set t_VRCorresponds to IREF_VRAt t_VRAt time, if VSO<VLATThen, ICELL>IREF_VRThreshold value V of memory cellCELL<VVROn the contrary, if VSO>VLATThen, ICELL<IREF_VRTo storeThreshold value V of storage unitCELL>VVR。
Setting two time points to respectively latch, and respectively obtaining the relationship between data and the threshold distribution area where the device is located as follows: the threshold voltage distribution relationship of the data and the corresponding memory cells is as follows:
first, let VSO<VLATThe latch data is 1 and otherwise 0,. And named the twice data as D1 and D2, where D1 corresponds to t_PVRD2 corresponds to t_VR。
If D1 is equal to 1 and D2 is equal to 1, the threshold of the device is distributed at VCELL<VPVRTherefore, the devices are distributed in the low threshold region.
If D1 is equal to 0 and D2 is equal to 1, the threshold of the device is distributed at VPVR<VCELL<VVRThe devices are distributed in the high threshold region.
If D1 is equal to 0 and D2 is equal to 0, the threshold of the device is distributed at VCELL>VVRThe device is distributed in the programmed state.
If D1 is equal to 1 and D2 is equal to 0, the data is invalid.
And (3) a discharging stage: each node is discharged after the data latch operation is finished.
Fig. 7 illustrates a timing diagram of a double data reading method according to an embodiment of the present invention. As shown in FIG. 7, during the precharge phase, the capacitor node (so) is charged to VDD, bl by applying voltages VDD + VTH, SEL, VPASS to PCH and applying verify voltages to the memory cells.
In the sensing phase, the purpose of the PCH bias voltage is to ensure that the capacitor node (so) does not drop below the Vth _ sa voltage, so when the capacitor node (so) is higher than Vth _ sa, so the so has no charging path but only a discharging path (verification current of the memory cell). Setting two induction times to record the threshold voltage and V of the memory cell respectivelyPVRAnd VVRAnd storing the data.
In the discharge phase, the word lines, bit lines and associated charge and discharge nodes are discharged.
FIG. 8 shows a threshold distribution map of MLC memory unit cells.
The following describes the concept of the present patent for double data verification by taking the application of the double data verification mode in MLC programming as an example, and the following is a flowchart of the application of the double data verification mode in MLC programming. FIG. 9 shows a flow chart of the application of the double data verify mode in MLC programming. As shown in figure 9 of the drawings,
for the timing of programming, the normal program timing is unchanged, but the double data read and single data read verify can be used in combination as the case may be. In example 1 as shown in fig. 10, when the P2 state is not passed, the double data verify mode can be adopted for all of the three verify voltages (Vr1, Vr2, Vr 3); after passing the P2 state, the single data verify mode is used at Vr 3.
In example 2 as shown in fig. 11, the double data verify mode may be adopted for all three verify voltages (Vr1, Vr2, Vr3) when the P1 state is not passed, and the single data verify mode is used for Vr2, Vr3 after the P1 state is passed.
In example 3 shown in fig. 12, at the time of failing the P1 state, the double data verify mode can be adopted for all of the three verify voltages (Vr1, Vr2, Vr 3); after passing the P1 state but not passing the P2 state, using double data verification mode at Vr2 and Vr 3; after passing the P2 state, the single data verify mode is used at Vr 3. The specific embodiments of this patent are not limited in this respect.
FIG. 13 shows a system framework for the application of the double data verify mode in MLC programming. The system frame comprises a device area, a voltage generation and transmission selection in a bit line direction, a page buffer including a reading circuit in a word line direction, and a control logic circuit including a reading mode selector. The special description is that: 1. in the read circuit, for the case of MSB, 4 latches are required, storing 2 bits of program data, respectively, and two bits of data in one read. 2. For the reading mode selector, the mode of needing double data verification or the mode of single data verification can be judged according to different requirements. The embodiment of the invention performs two times of latching to two read data in the process of performing one-time programming verification on the same memory cellTo distinguish HVTDevice and LVTA device. The method of the invention reduces the time of one-time programming verification, including the time of pre-charging, the time of voltage establishment on the word line, the sensing time and the like.
The embodiment of the invention provides a double-data verification mode, which aims to quickly find out a high-threshold storage unit by reading two data in one-time programming verification.
A program verification voltage is set on a word line, a normal read voltage is set on a bit line, a program verification time sequence comprises three parts, namely, a first step of charging a capacitor node, a second step of discharging the capacitor node by using a storage unit current, and a third step of discharging a relevant node.
In the second step, the discharge speed of the capacitor is in direct proportion to the discharge current, and V/T is I/C.
In the second step, for a selected LATCH voltage, the data greater than LATCH, unlike the data less than the LATCH voltage, is 0 and 1, respectively. Then, for a selected latch voltage, the magnitude of the discharge current, i.e., the current of the memory cell, can be determined based on the data of the latch voltage at a given time T. Specifically, for the case of being larger than the latch voltage, a small current is caused, and for the case of being larger than the latch voltage, a large current is caused.
In the second step, two-step latching is adopted, so that the currents of large, medium and small third grades can be distinguished, and the memory cell with a high threshold value can be found through the distribution relation between the currents and the threshold values of the memory unit elements.
In applying the double data verification mode to the two-bit memory cell (MLC) programming mode, in the system architecture, a read mode selector is required to combine the double data verification mode and the single data verification mode proposed in this patent, taking MSB programming as an example, example 1, when the P2 state is not passed, the double data verification mode can be applied to all three verification voltages (Vr1, Vr2, Vr3), and after the P2 state is passed, the single data verification mode is applied to Vr 3. Example 2, the double data verify mode may be employed for all three verify voltages (Vr1, Vr2, Vr3) when the P1 state is not passed, and the single data verify mode may be employed at Vr2, Vr3 after the P1 state is passed. Example 3, the double data verify mode may be employed at all three verify voltages (Vr1, Vr2, Vr3) when the P1 state is not passed, at Vr2, Vr3 when the P1 state is passed but the P2 state is not passed, and at Vr3 the single data verify mode is employed after the P2 state is passed. The specific application is not limited to the above examples.
The method according to the embodiment of the present invention is not limited to the programming mode of MLC, and may be used in the programming mode of single bit (SLC), three bit (TLC), more bit memory cells, etc.
In circuit implementation, embodiments of the present invention require that there be two LATCHs in the read circuit for storing data for the double data verify mode. As for the MSB storage structure, then four latches are needed to store the MSB, LSB and verified double data, respectively.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.
Claims (14)
1. A double data read verification method for flash memory cells arranged in an array and connected to corresponding bit lines and word lines, wherein the threshold voltage distribution of high threshold memory cells is less than the programmed state threshold voltage (Vthreshold)VR) But greater than the threshold voltage (V) of the low threshold memory cellPVR) The threshold voltage of the low threshold memory cell is distributed to be lower than the threshold voltage (V) of the low threshold memory cellPVR) The program state threshold voltage is a verify voltage, the threshold voltage of the low threshold memory cell is a pre-verify voltage, the method comprising:
determining a current threshold voltage of the memory cell;
if the current threshold voltage is less than the pre-verification voltage, determining that the memory cell is a low threshold memory cell;
determining the memory cell as a high threshold memory cell if the current threshold voltage is greater than or equal to the pre-verify voltage and less than or equal to the verify voltage;
determining that the memory cell is in a programmed state if the current threshold voltage is greater than the verify voltage;
wherein in the double data verification mode, two data are read in one program verify operation.
2. The dual data read verify method of claim 1, wherein a high threshold memory device and a low threshold memory device are distinguished by obtaining two read results in one read operation, the method sets a program verify voltage on a word line and a normal read voltage on a bit line, the method comprising the following three phases:
a pre-charging stage: charging a storage capacitor on a capacitive node (So);
a current induction stage: discharging a storage capacitance on a capacitance node (so) by a storage cell, during said discharging: the voltage magnitude of the capacitance node (so) point is related to the current of the memory cell, the discharge time and the voltage of the capacitance node (so) during pre-charging:
CSO*(VSO_PRE-VSO(t))＝ICELL*t，
wherein C isSOIs the capacitance on the capacitive node (so), is constant; vSO_PREIs the voltage of the capacitor node (so) during pre-charging, and is also a constant; i isCELLIs the current of the memory cell, related to the threshold of the memory device; vSO(t) is the voltage on the capacitive node (so) at time t; t is the discharge time and the flip-flop voltage V of the latch is knownLATWhen the memory cell current (I) is turned overCELL) Is also constant with time (t);
and (3) a discharging stage: each node is discharged after the data latch operation is finished.
3. The dual data read verify method of claim 2, wherein V is a verify voltagePVRAnd VVRTwo reference currents I are correspondingly generatedREF_PVRAnd IREF_VRAnd then deducing the corresponding discharge time required for turning over the latch according to the corresponding relation between the current and the discharge time.
4. The dual data read verification method of claim 3, wherein setting the current sense time corresponds to setting the reference current, assuming t is set_PVRCorresponds to IREF_PVRAt t_PVRTime of day, if VSO<VLATThen, ICELL>IREF_PVRThreshold value V of memory cellCELL<VPVROn the contrary, if VSO>VLATThen, ICELL<IREF_PVRThreshold value V of memory cellCELL>VPVR(ii) a Similarly, set t_VRCorresponds to IREF_VRAt t_VRAt time, if VSO<VLATThen, ICELL>IREF_VRThreshold value V of memory cellCELL<VVROn the contrary, if VSO>VLATThen, ICELL<IREF_VRThreshold value V of memory cellCELL>VVR。
5. The dual data read verify method of claim 4, wherein the data is latched twice and compared within a time of one current sensing, the two comparison results are latched, and the threshold interval of the memory cell is determined by using the two comparison results.
6. The dual data read verification method of claim 5, wherein the read data and the threshold voltage distributions corresponding to the memory cells thereof are as follows:
let VSO<VLATThe latched data is 1 and vice versa is 0, and the data twice are referred to as D1 and D2, respectively, where D1 corresponds to t_PVRD2 corresponds to t_VR：
If D1 is equal to 1 and D2 is equal to 1, the threshold distribution of the memory cell is VCELL<VPVRTherefore, the memory cells are distributed in the low threshold region;
if D1 is equal to 0 and D2 is equal to 1, the threshold distribution of the memory cell is VPVR<VCELL<VVRSo that the memory cells are distributed in the high threshold region;
if D1 is equal to 0 and D2 is equal to 0, the threshold distribution of the memory cell is VCELL>VPVRTherefore, the memory cells are distributed in the low threshold region; and
if D1 is equal to 1 and D2 is equal to 0, invalid data is indicated.
7. The dual data read verify method of claim 1, wherein the dual data verify mode is applied in a two-bit memory cell (MLC) program mode, the dual data verify mode and the single data verify mode being used in combination by a read mode selector.
8. The double data read verify method of claim 7, wherein for MSB programming in the failed P2 state, a double data verify mode is used for all three verify voltages (Vr1, Vr2, Vr 3; after the P2 state is passed, a single data verify mode is used at Vr 3.
9. The double data read verify method of claim 7, wherein the double data verify mode is employed for all three verify voltages (Vr1, Vr2, Vr3) when the P1 state is not passed; after passing the P1 state, the single data verify mode is used at Vr2 and Vr 3.
10. The double data read verify method of claim 7, wherein the double data verify mode is employed for all three verify voltages (Vr1, Vr2, Vr3) when the P1 state is not passed; after passing the P1 state but not passing the P2 state, using double data verification mode at Vr2 and Vr 3; after passing the P2 state, the single data verify mode is used at Vr 3.
11. The dual data read verification method of claim 1, further applicable in single bit (SLC), three bit (TLC), more bit memory cell programming modes.
12. The dual data read verify method of claim 1, wherein the read circuit includes two latches LATCH for storing data for the dual data verify mode.
13. The dual data read verify method of claim 1, wherein for a MSB storage configuration, four latches LATCH are included in the read circuit to store the MSB, LSB and verified dual data, respectively.
14. A double data read verify device for flash memory cells arranged in an array and connected to corresponding bit lines and word lines, wherein the threshold voltage distribution of the high threshold memory cells is less than the programmed state threshold voltage (Vth)VR) But greater than the threshold voltage (V) of the low threshold memory cellPVR) The threshold voltage of the low threshold memory cell is distributed to be lower than the threshold voltage (V) of the low threshold memory cellPVR) The program state threshold voltage is a verify voltage, the threshold voltage of the low threshold memory cell is a pre-verify voltage, the dual data read verify device is configured to:
determining a current threshold voltage of the memory cell;
if the current threshold voltage is less than the pre-verification voltage, determining that the memory cell is a low threshold memory cell;
determining the memory cell as a high threshold memory cell if the current threshold voltage is greater than or equal to the pre-verify voltage and less than or equal to the verify voltage;
determining that the memory cell is in a programmed state if the current threshold voltage is greater than the verify voltage;
wherein in the double data verification mode, two data are read in one program verify operation.
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