CN109631954A - Realize the proframmable linear Hall sensor chip structure of on piece temperature compensation function - Google Patents
Realize the proframmable linear Hall sensor chip structure of on piece temperature compensation function Download PDFInfo
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- CN109631954A CN109631954A CN201910080482.9A CN201910080482A CN109631954A CN 109631954 A CN109631954 A CN 109631954A CN 201910080482 A CN201910080482 A CN 201910080482A CN 109631954 A CN109631954 A CN 109631954A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
- G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
- G01D5/14—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
- G01D5/142—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage using Hall-effect devices
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D3/00—Indicating or recording apparatus with provision for the special purposes referred to in the subgroups
- G01D3/028—Indicating or recording apparatus with provision for the special purposes referred to in the subgroups mitigating undesired influences, e.g. temperature, pressure
- G01D3/036—Indicating or recording apparatus with provision for the special purposes referred to in the subgroups mitigating undesired influences, e.g. temperature, pressure on measuring arrangements themselves
Abstract
The present invention relates to a kind of proframmable linear Hall sensor chip structures for realizing on piece temperature compensation function, including signal acquisition module to be converted into differential voltage signal, and amplify recovery for generating differential output current signal；Module is filtered, is connected with the signal acquisition module, for carrying out first-order filtering and filtering out the signal of specific frequency point, provides the driving capability of Hall voltage output；Signal processing module is connected with the signal acquisition module and filtering processing module, for detecting temperature and carrying out Digital Signal Processing, provides the clock of different timing for each module.Using the chip structure, provide a kind of gain adjustment scheme of more convenient and efficient, so that the proframmable linear Hall can meet the client application of different sensitivity demand, while the response time of linear Hall is accelerated, is more suitable for the application of some quick responses.Temperature sensor and digital backoff algorithm, ensure that the precision of sensor application detection.
Description
Technical field
The present invention relates to the current sensor fields, in particular to a kind of reality of sensor field more particularly to quick response
The proframmable linear Hall sensor chip structure of existing on piece temperature compensation function.
Background technique
Linear hall sensor is generally by Hall element, hall signal amplification and demodulator circuit, the composition such as driving circuit.It
Input be magnetic field strength, output is voltage.Wherein output voltage is directly proportional to input magnetic field strength.So referred to as line
Property Hall sensor, this kind of circuit requirement high sensitivity, the linearity is good, and temperature drift is small, high reliablity, and integrated level is high, chip area
The features such as small.
The characteristics of according to linear hall sensor, it can be applied to the detection in various magnetic fields.In some application fields such as
Position sensor, proximity sensor, power induction, current sensor etc. are widely adopted.And different applications is to linear Hall
The sensitivity requirement of sensor is all inconsistent, so client needs to be programmed linear hall sensor, namely programmable
Linear hall sensor, by modes such as built-in EEPROM or MTP come the sensitivity of linear adjustment Hall sensor and quiet
The indexs such as state output voltage.
Proframmable linear Hall current sensor a kind of typical case as shown in Figure 1, current sense as shown in Figure 1
Device mould group scheme includes a conductor, flows through an electric current Ip to be detected on the conductor；A magnetism gathering rings are surrounded outside conductor
(Ring Concentrator), linear hall sensor chip (Hs) is placed on the opening of magnetism gathering rings, for detection of aggregation
Magnetic field strength Bp.The magnetic field strength is directly proportional with by the electric current Ip of conductor.Pass through the spirit of adjusting proframmable linear Hall simultaneously
The indexs such as sensitivity and quiescent output voltage can be converted into the variation of electric current to be detected the change of linear hall sensor output voltage
Change, and this output voltage can be made to change in a certain range.
That is:
Vh=Si × Ip+Vq；
Wherein Vh is the voltage output of proframmable linear Hall sensor.Si be current sensor sensitivity, Ip be to
Electric current is detected, Vq is the quiescent voltage output of the linear hall sensor device when electric current to be detected is 0.Si and Vq can root
According to application demand, adjusted by client programming.
Existing proframmable linear Hall sensor is usually voltage-type Hall sensor, the output voltage warp of Hall element
It is demodulated after crossing amplification, then filtering generates the output of linear hall sensor.The mode of sensitivity is adjusted generally by adjustment
The amplification factor of front-end amplifier such as adjusts mutual conductance (gm) Lai Shixian that electric current namely inputs device.The mode of temperature-compensating
It is typically also to be completed by the way of pure simulation, or through a D/A (digital-to-analogue conversion).Traditional proframmable linear Hall
It is not high in the presence of programming precision, program the problems such as complexity is high.Such as by adjusting the implementation of gm, itself is a with temperature by gm
The parameter of variation is spent, the temperature-compensating that can make is more complicated, needs to can be only achieved the precision of needs using multiple segmented compensations.It is pure
The compensation way of simulation both increases hardware complexity using the mode of D/A.And common filtering mode can also generate it is non-
Often big time delay, keeps the response time of proframmable linear Hall slack-off.
Summary of the invention
The purpose of the present invention is overcoming the above-mentioned prior art, provide that a kind of hardware development is at low cost, programming
Simply, the proframmable linear Hall sensor chip structure of the small realization on piece temperature compensation function of temperature drift.
To achieve the goals above, the proframmable linear Hall sensor core of realization on piece temperature compensation function of the invention
Chip architecture is as follows:
The proframmable linear Hall sensor chip structure of the realization on piece temperature compensation function, is mainly characterized by, institute
The chip structure stated includes:
Signal acquisition module is converted into differential voltage signal, and amplify extensive for generating differential output current signal
It is multiple；
Module is filtered, is connected with the signal acquisition module, for carrying out first-order filtering and filtering out specific frequency
The signal of rate point provides the driving capability of Hall voltage output；
Signal processing module is connected with the signal acquisition module and filtering processing module, for detect temperature and
Digital Signal Processing is carried out, provides the clock of different timing for each module.
Preferably, the signal acquisition module includes:
Silicon Hall element array is connected with the signal processing module, for generating a pair of of differential output current letter
Number；
Integrator is connected with the silicon Hall element array and signal processing module, is used within the period two
The differential current signal that Hall element generates is integrated into differential voltage signal.
Preferably, the signal acquisition module further includes voltage sample amplification and signal rectification module, with the product
Device is divided to be connected with signal processing module, for Hall voltage signal to be amplified and recovered.
Preferably, the filtering processing module includes:
Frequency overlapped-resistable filter is connected, for carrying out single order filter with the voltage sample amplification and signal rectification module
Wave filters out the signal of Nyquist sampling frequency or more；
Adaptive frequency trapper is connected, for filtering out spy with the frequency overlapped-resistable filter and signal processing module
Determine the signal of Frequency point；
Drive module is connected with the adaptive frequency trapper, for providing the driving energy of Hall voltage output
Power completes High frequency filter and adjusts quiescent output voltage.
Preferably, the filtering processing module further includes reference voltage and current generating module, with the driving mould
Block is connected with signal processing module, for providing reference voltage and electric current to chip.
Preferably, the signal processing module includes:
Digital processing module, with the silicon Hall element array, integrator, voltage sample amplification and signal rectification mould
Block, adaptive frequency trapper are connected with reference voltage and current generating module, for carrying out Digital Signal Processing and being
Each analog module provides the clock of different timing；
Clock oscillator is connected with the digital processing module, for providing digital operation for digital processing module
Clock, and the work clock of specific time sequence is provided for adaptive frequency trapper；
Temperature sensor is connected, for detecting temperature with the digital processing module.
Preferably, the digital processing module includes:
First multiplying module is connected；
Second multiplying module is connected with the first multiplying module；
First addition module is connected with the first multiplying module；
Second addition module is connected with the second multiplying module；
First programmable module is connected with the first multiplying module and the second multiplying module；
Second programmable module is connected with first addition module；
Third programmable module is connected with second addition module；
Register module is connected with first programmable module, the first addition module and the second addition module；
Clock generation module is connected with the register module.
Preferably, the group of the silicon Hall element array is combined into a Hall element, two Hall elements or four suddenly
That element.
Preferably, the silicon Hall element array includes the first Hall element and the second Hall element, and it is connected with each other.
Preferably, the Hall element of the silicon Hall element array uses cross Hall element.
Preferably, the integrator includes integrating capacitor, both ends respectively with silicon Hall element array and voltage sample
Amplification and signal rectification module are connected.
Preferably, the integrating capacitor according to the demand of application end gear demand and adjusting step change coarse adjustment digit and
Fine tuning digit.
Preferably, the integrating capacitor is composed in parallel by 8 binary weight capacitors and is controlled by 8, for realizing 8
Fine tuning.
Using the proframmable linear Hall sensor chip structure of realization on piece temperature compensation function of the invention, due to
Which provide a kind of gain adjustment schemes of more convenient and efficient, so that the proframmable linear Hall can meet different sensitivity need
The client application asked, while the response time of linear Hall is accelerated, it is more suitable for the application of some quick responses, such as
The application of current sensor.Temperature sensor and digital backoff algorithm, export the sensitivity of sensor and quiescent voltage with temperature
Degree variation all very littles, ensure that the precision of sensor application detection.
Detailed description of the invention
Fig. 1 is typical case of the proframmable linear Hall in current sensor of the prior art.
Fig. 2 is the totality of the proframmable linear Hall sensor chip structure of realization on piece temperature compensation function of the invention
Circuit diagram.
Fig. 3 is the Hall of the proframmable linear Hall sensor chip structure of realization on piece temperature compensation function of the invention
The embodiment schematic diagram of element arrays.
Fig. 4 is the signal of the proframmable linear Hall sensor chip structure of realization on piece temperature compensation function of the invention
Obtain the schematic diagram of module.
Fig. 5 is the Hall of the proframmable linear Hall sensor chip structure of realization on piece temperature compensation function of the invention
The time diagram of element manipulation clock.
Fig. 6 is the filtering of the proframmable linear Hall sensor chip structure of realization on piece temperature compensation function of the invention
The schematic diagram of processing module.
Fig. 7 is the signal of the proframmable linear Hall sensor chip structure of realization on piece temperature compensation function of the invention
The schematic diagram of processing module.
Appended drawing reference:
100 silicon Hall element arrays
200 integrators
The amplification of 300 voltage samples and signal rectification module
400 frequency overlapped-resistable filters
500 adaptive frequency trappers
600 drive modules
700 reference voltages and current generating module
800 digital processing modules
900 clock oscillators
1000 temperature sensors
810 first programmable modules
820 second programmable modules
830 third programmable modules
840 first multiplying modules
850 second multiplying modules
860 first addition modules
870 second addition modules
880 register modules
890 clock generation modules
The first Hall element of H1
The second Hall element of H2
Specific embodiment
It is further to carry out combined with specific embodiments below in order to more clearly describe technology contents of the invention
Description.
The proframmable linear Hall sensor chip structure of the realization on piece temperature compensation function of the invention, wherein institute
The chip structure stated includes:
Silicon Hall element array 100 is connected with the signal processing module, for generating a pair of of differential output current
Signal；
Integrator 200 is connected with the silicon Hall element array 100 and signal processing module, within the period
The differential current signal that two Hall elements generate is integrated into differential voltage signal.
As the preferred embodiment of the present invention, the signal acquisition module further includes that voltage sample amplification and signal are whole
Flow module 300 is connected with the integrator 200 and signal processing module, for Hall voltage signal to be amplified and restored
Out.
As the preferred embodiment of the present invention, the filtering processing module includes:
Frequency overlapped-resistable filter 400 is connected, for carrying out with the voltage sample amplification and signal rectification module 300
First-order filtering filters out the signal of Nyquist sampling frequency or more；
Adaptive frequency trapper 500 is connected with the frequency overlapped-resistable filter 400 and signal processing module, is used for
Filter out the signal of specific frequency point；
Drive module 600 is connected with the adaptive frequency trapper 500, for providing Hall voltage output
Driving capability completes High frequency filter and adjusts quiescent output voltage.
As the preferred embodiment of the present invention, the filtering processing module further includes that reference voltage and electric current generate mould
Block 700 is connected with the drive module 600 and signal processing module, for providing reference voltage and electric current to chip.
As the preferred embodiment of the present invention, the signal processing module includes:
Digital processing module 800, with the silicon Hall element array 100, integrator 200, voltage sample amplification and letter
Number rectification module 300, adaptive frequency trapper 500 are connected with reference voltage and current generating module 700, for being counted
Word signal processing and the clock of different timing is provided for each analog module；
Clock oscillator 900 is connected with the digital processing module 800, for providing for digital processing module 800
Digital operation clock, and the work clock of specific time sequence is provided for adaptive frequency trapper 500；
Temperature sensor 1000 is connected, for detecting temperature with the digital processing module 800.
As the preferred embodiment of the present invention, the digital processing module 800 includes:
First multiplying module 840 is connected with the temperature sensor 1000；
Second multiplying module 850 is connected with the temperature sensor 1000 and the first multiplying module 840
It connects；
First addition module 860 is connected with the first multiplying module 840；
Second addition module 870 is connected with the second multiplying module 850；
First programmable module 810, with 850 phase of the first multiplying module 840 and the second multiplying module
Connection；
Second programmable module 820 is connected with first addition module 860；
Third programmable module 830 is connected with second addition module 870；
Register module 880, with first programmable module 810, the first addition module 860 and the second addition module
870 are connected；
Clock generation module 890 is connected with the register module 880.
As the preferred embodiment of the present invention, the group of the silicon Hall element array 100 be combined into a Hall element,
Two Hall elements or four Hall elements.
As the preferred embodiment of the present invention, the silicon Hall element array 100 include the first Hall element H1 and
Second Hall element H2, and be connected with each other.
As the preferred embodiment of the present invention, the Hall element of the silicon Hall element array 100 is using cross
Hall element.
As the preferred embodiment of the present invention, the integrator 200 include integrating capacitor, both ends respectively with silicon suddenly
You amplify with voltage sample element arrays 100 and signal rectification module 300 is connected.
As the preferred embodiment of the present invention, the integrating capacitor is according to application end gear demand and adjusting step
Demand changes coarse adjustment digit and fine tuning digit.
As the preferred embodiment of the present invention, the integrating capacitor is composed in parallel and by 8 binary weight capacitors by 8
Position control, for realizing 8 fine tunings.
In a specific embodiment of the invention, including silicon Hall element array 100, by one, two or more Hall members
Part array composition, generates the differential current signal directly proportional to external magnetic field；Integrator 200, in a certain period of time
Current signal is integrated into voltage signal；Voltage sample amplification and signal rectification module 300, for Hall voltage signal to be amplified
With recover；Frequency overlapped-resistable filter 400, for avoiding subsequent sampling circuit that signal aliasing phenomenon occurs after filtering；Adaptively
Frequency trap 500, for filtering out the signal of specific frequency point, and this specific frequency point can be adaptive；Drive module 600,
For providing the driving capability of Hall voltage output, it is completed at the same time High frequency filter and quiescent output voltage is adjusted；Reference voltage and
Current generating module 700, for providing reference voltage and electric current to entire chip；Digital processing module 800 carries out digital signal
Processing, and the clock of different timing is provided to each analog module, it is clock group CKA, clock group CKB, clock group respectively
CKC, clock group CKD；Clock oscillator 900 provides digital reference work clock CKREF for 800；And temperature sensor
1000, temperature is detected, temperature compensated reference is provided.
Silicon Hall element array 100 is made of two Hall element arrays；Two Hall elements are under different chopper clocks
Work inputs as current signal, for generating a pair of of differential output current signal.
Integrator 200, for the differential current signal that two Hall elements generate to be integrated into a certain period of time
Differential voltage signal；
Voltage sample amplification and signal rectification module 300, for Hall voltage signal to be further amplified and recovered
Come；
Frequency overlapped-resistable filter 400 filters out the signal of Nyquist sampling frequency or more, avoids for carrying out first-order filtering
Signal aliasing phenomenon occurs for subsequent sampling circuit；
Adaptive frequency trapper 500, for filtering out the signal of specific frequency point, and this specific frequency point can be adaptive
It answers, changes with the variation of sampling clock；
Drive module 600 is completed at the same time High frequency filter and Static output for providing the driving capability of Hall voltage output
The function that voltage is adjusted；
Reference voltage and current generating module 700, for providing reference voltage and electric current to entire chip；
Digital processing module 800, carry out Digital Signal Processing, and to each analog module provide different timing when
Clock, the digital processing module embed multiple programmable (MTP) memory module, in conjunction with temperature compensation algorithm of the invention, are used to
There is provided when production line end is such as surveyed eventually and when client application sensitivity and the adjusting of quiescent output voltage with
And temperature adjustmemt.
Clock oscillator 900 provides digital operation clock for 800, and provides for adaptive frequency trapper 500 specific
The work clock of timing；
And temperature sensor 1000, temperature is detected, output is set of number signal, is input to digital processing module
800, in conjunction with built-in temperature correction algorithm, temperature-compensating is provided for sensitivity and quiescent output voltage.
With reference to the attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description.
Silicon Hall element array 100, for generating a pair of difference Hall current signal directly proportional to external magnetic field.Silicon is suddenly
Your element arrays can be combined using one, two or four etc., the present embodiment by two Hall element arrays form H1,
H2.As shown in figure 3, Hall element uses cross Hall, there are four port, respectively C1, C2, C3, C4, Hall element is being cut
It works under wave frequency rate, four phase chopper clocks are respectively CK1, CK2, CK3, CK4.Suddenly with one in two Hall elements H1, H2
For your element H1, when CK1 high level is effective, corresponding 1 working condition, i.e. the input of C1, C4 as reference current Ibias
End, the output end of C2, C3 as difference current output In and Ip.And so on, when CK2 high level is effective, corresponding work shape
State 2, when CK3 high level, corresponding working state 3, when CK4 high level is effective, corresponding working state 4.That is, the work of H1
The switching of state 1234 is clockwise.And the switching of another Hall element H2 working condition is on the contrary, when CK1 high level, it is right
Working condition 3 is answered, when CK2 is high level, corresponding working state 2, when CK3 is high level, corresponding working state 1, CK4 is height
When level, corresponding working state 4.That is, the working condition of H2 from (3), (2), (1) to 4 switching be that inverse clock is reversed.
It is connected again by mode as shown in Figure 4 based on two Halls H1, H2 under the work of four phase chopper clocks.Work
For the timing of clock as shown in figure 5, when CKr is high level, the both ends adjustable integrating capacitor Cin are switched on and off short circuit, carry out resetting behaviour
Make.When CKi is high level, integrator starts integration operation, time of integration 4t.In integration period, CK1, CK2, CK3,
Four phase copped wave work clocks of the CK4 as double Hall H1, H2, are alternately respectively high level, and the time span of high level is all t,
Output difference current signal Iop and Ion.Two-pass DINSAR current signal Iop, Ion gives integrator 200, long by the time of integration
Output signal Vop1, Von1 after degree 4t.When CKs is high level, voltage sample amplification and signal rectification module 300 are to 200
Output signal Vop1, Von1 carry out output signal Vop2 and Von2 after sampling and rectifying operation.
Iop-Ion=2 × Ihall；
Vop1-Von1=(Iop-Ion) × Cint × (4t)；
That is, Vop1-Von1=8 × Ihall × Cint × t；
Wherein Ihall is the Hall current signal that Hall element generates, and Cint is integrating capacitor, and t is time of integration parameter.
From the above equation, we can see that being achieved that by adjusting time of integration parameter t and adjustable integrating capacitor Cint value and adjusting hall signal amplification
The gain of link, namely have adjusted the sensitivity of linear hall sensor.This programme t is controlled by two, realizes two coarse adjustment, point
Application end is not corresponded to four gears of linear Hall different sensitivity demand.Cint is controlled by 8, by 8 binary weight electricity
Appearance composes in parallel, and realizes 8 fine tunings.Coarse adjustment position can certainly be changed according to the demand of application end gear demand and adjusting step
Several and fine tuning digit.This programme is one of case study on implementation.
Vop2, Von2 are used as the input of frequency overlapped-resistable filter 400 first, how filter out subsequent adaptive frequency trapper 500
Frequency-portions more than Qwest's frequency avoid the generation of sampling process aliasing.The output of frequency overlapped-resistable filter 400
Vop3, Von3, as the input signal of adaptive frequency trapper 500, adaptive frequency trapper 500 is using after multiple repairing weld
The mode being averaged realizes that sample frequency is the multiple of CKs, and the frequency of average calculating operation is CKs, and first trap frequency point is
CKs, the sample frequency that specific implementation can be derived from adaptation frequency trap 500 is 2 × CKs, then the band of frequency overlapped-resistable filter 400
Width is the frequency of CKs, then trap frequency point is the integral multiple of CKs.It is filtered using frequency overlapped-resistable filter and trapper, significantly
Accelerate the reaction time of linear Hall.
As shown in fig. 6, output signal Vop4, Von4 of adaptive frequency trapper 500 is as the defeated of drive module 600
Enter, while drive module 600 realizes that difference turns the function of Single-end output, filters out high-frequency signal.Other the one of drive module 600
End input Voff, is provided by reference voltage and current generating module 700.In the implementation case Voff by 8 digit word bit Cbits <
7:0 > control, practical application and can also be realized according to the requirement of Adjustment precision and range using other digits in realizing.
As shown in fig. 7, clock oscillator 900, provides digital reference work clock CKREF for digital processing module 800, when
The clock of clock oscillator is a timing reference input close to zero-temperature coefficient, in the implementation case the frequency of clock oscillator by
Charging/discharging voltage relevant with a negative temperature coefficient mobility to the PTAT current of temperature direct ratio codetermines.I.e.
Wherein, f is oscillator clock frequency, and I is PTAT current, and μ is mobility.
Temperature sensor 1000, for the environment temperature of detection chip work, exporting a 8 digit numeric code x is practical temperature
The difference of degree and room temperature.
X=Ta-T0；
Wherein Ta is the chip actual work temperature detected, and T0 is room temperature.X is the difference of actual temperature and room temperature, as
One input of digital processing module 800.
Digital processing module 800 includes three multiple programmable modules MTP0810, MTP1820, MTP2830, two multiplication
Computing module MATH1840, MATH2850, two addition modules ADDER1860, ADDER2870 and a register module
880, a clock generation module 890.
MTP0 is used to deposit parameter a1, a2, b1, b2, Tsel<1:0>.
Wherein a1 is sensitivity temperature coefficient, and b1 is that sensitivity at room temperature configures target value, and a2 is quiescent output voltage temperature
Coefficient is spent, b2 is that quiescent output voltage configures target value at room temperature.A1, a2 can pass through test high temperature and spirits different at room temperature
Sensitivity and quiescent output voltage obtain.Tsel<1:0>is used to realize coarse adjustment to sensitivity.
MPT1820, MTP2830 are respectively intended to 8 digit numeric codes of storage, are supplied to client and are used to sensitivity and Static output
Voltage carries out client programming use.
First the 840, second multiplying module of multiplying module (MATH1) (MATH2) 850 carries out multiplication fortune respectively
A1 × x+b1 and a2 × x+b2 is calculated, realizes that sensitivity and quiescent output voltage correct the single order of temperature.
First multiplying module 840 is added with the first addition module 860 execution that is output to of the second programmable module 820
It is stored to register module 880 after operation, generates the integrating capacitor Cint value that Cintc<7:0>is used to control integrator 200, realizes
The fine tuning of sensitivity.
Second multiplying module, 850 third programmable module and 830 second addition module 870 that is output to execute addition
It is stored to register module 880 after operation, generates the output valve that Cbits<7:0>is used to control voltage and current generation module 700
Voff realizes the adjusting of quiescent output voltage.
Input of another two outputs Tsela<1:0>of register module 880 as clock generation module 890, into
The coarse adjustment of line sensitivity, namely the time of integration t by adjusting integrator 200 realize application end to different sensitivity gear
Demand.
The input of clock generation module 890 is the output CLKREF of clock oscillator 900, and clock generation module 890 is distinguished
Export four clock signal groups CKA, CKB, CKC, CKD.
Wherein clock group CKA, including CK1, CK2, CK3, CK4, when four phases as silicon Hall element array 100 work
Clock.
Wherein clock group CKB, including CKi, CKr, the work clock as integrator 200.
Wherein clock group CKC, including CKs and corresponding non-overlapping clock, as voltage sample amplification and signal rectification module
300 work clock.
Wherein CKD, the work clock including CK11, CK12, CKa, CKS1 etc., as adaptive frequency trapper 500.
The plus-minus of the programming and the temperature correction that directly carry out client with numerical portion in this programme controls simulation part later
The adjusting of the sensitivity and quiescent output voltage that divide, simplifies design method.
To the temperature adjustmemt of sensitivity, time of integration t is controlled by numerical portion two digits and realizes coarse adjustment, it is corresponding different
Application end sensitivity gear.Integrating capacitor Cint value is adjusted by eight-digit number word control bit, in the same sensitivity gear
Fine tuning is inside carried out again.The parameter t and Cint of adjustment are not varied with temperature substantially.And traditional adjustment sensitivity fine tuning and coarse adjustment
Mode be all to be completed by adjusting the output impedance R of electric current namely mutual conductance gm and amplifier mostly, value is inherently deposited
In temperature drift characteristic.So that temperature-compensating becomes more complicated, basic need can be only achieved higher precision by temperature section compensation.
The parameter t and Cint of coarse adjustment and fine tuning can ignore the variation of temperature in this case.Numerical portion can using first compensation phase
To reach same precision, hardware design and programming mode are enormously simplified.
Using the proframmable linear Hall sensor chip structure of realization on piece temperature compensation function of the invention, provide
A kind of gain adjustment scheme of more convenient and efficient, so that the proframmable linear Hall can meet the client of different sensitivity demand
End application, while the response time of linear Hall is accelerated, it is more suitable for the application of some quick responses, such as current sense
The application of device.Temperature sensor and digital backoff algorithm vary with temperature the sensitivity of sensor and quiescent voltage output all
Very little ensure that the precision of sensor application detection.
In this description, the present invention is described with reference to its specific embodiment.But it is clear that can still make
Various modifications and alterations are without departing from the spirit and scope of the invention.Therefore, the description and the appended drawings should be considered as illustrative
And not restrictive.
Claims (13)
1. a kind of proframmable linear Hall sensor chip structure for realizing on piece temperature compensation function, which is characterized in that described
Chip structure include:
Signal acquisition module is converted into differential voltage signal, and amplify recovery for generating differential output current signal；
Module is filtered, is connected with the signal acquisition module, for carrying out first-order filtering and filtering out specific frequency point
Signal, provide Hall voltage output driving capability；
Signal processing module is connected, for detecting temperature and progress with the signal acquisition module and filtering processing module
Digital Signal Processing provides the clock of different timing for each module.
2. the proframmable linear Hall sensor chip structure according to claim 1 for realizing on piece temperature compensation function,
It is characterized in that, the signal acquisition module includes:
Silicon Hall element array (100), is connected with the signal processing module, for generating a pair of of differential output current letter
Number；
Integrator (200) is connected with the silicon Hall element array (100) and signal processing module, within the period
The differential current signal that two Hall elements generate is integrated into differential voltage signal.
3. the proframmable linear Hall sensor chip structure according to claim 2 for realizing on piece temperature compensation function,
It is characterized in that, the signal acquisition module further includes voltage sample amplification and signal rectification module (300), with the product
Device (200) are divided to be connected with signal processing module, for Hall voltage signal to be amplified and recovered.
4. the proframmable linear Hall sensor chip structure according to claim 1 for realizing on piece temperature compensation function,
It is characterized in that, the filtering processing module includes:
Frequency overlapped-resistable filter (400) is connected, for carrying out with the voltage sample amplification and signal rectification module (300)
First-order filtering filters out the signal of Nyquist sampling frequency or more；
Adaptive frequency trapper (500) is connected with the frequency overlapped-resistable filter (400) and signal processing module, is used for
Filter out the signal of specific frequency point；
Drive module (600) is connected with the adaptive frequency trapper (500), for providing Hall voltage output
Driving capability completes High frequency filter and adjusts quiescent output voltage.
5. the proframmable linear Hall sensor chip structure according to claim 4 for realizing on piece temperature compensation function,
It is characterized in that, the filtering processing module further includes reference voltage and current generating module (700), with the driving mould
Block (600) is connected with signal processing module, for providing reference voltage and electric current to chip.
6. according to the proframmable linear Hall sensor chip knot of realization on piece temperature compensation function described in claim 3 and 5
Structure, which is characterized in that the signal processing module includes:
Digital processing module (800), with the silicon Hall element array (100), integrator (200), voltage sample amplification and
Signal rectification module (300), adaptive frequency trapper (500) are connected with reference voltage and current generating module (700), use
The clock of different timing is provided in progress Digital Signal Processing and for each analog module；
Clock oscillator (900) is connected with the digital processing module (800), for mentioning for digital processing module (800)
The work clock of specific time sequence is provided for digital operation clock, and for adaptive frequency trapper (500)；
Temperature sensor (1000) is connected, for detecting temperature with the digital processing module (800).
7. the proframmable linear Hall sensor chip structure according to claim 6 for realizing on piece temperature compensation function,
It is characterized in that, the digital processing module (800) includes:
First multiplying module (840) is connected with the temperature sensor (1000)；
Second multiplying module (850) is connected with the temperature sensor (1000) and the first multiplying module (840)
It connects；
First addition module (860) is connected with the first multiplying module (840)；
Second addition module (870) is connected with the second multiplying module (850)；
First programmable module (810), with the first multiplying module (840) and the second multiplying module (850)
It is connected；
Second programmable module (820) is connected with first addition module (860)；
Third programmable module (830) is connected with second addition module (870)；
Register module (880), with first programmable module (810), the first addition module (860) and the second addition mould
Block (870) is connected；
Clock generation module (890) is connected with the register module (880).
8. the proframmable linear Hall sensor chip structure according to claim 2 for realizing on piece temperature compensation function,
It is characterized in that, the group of the silicon Hall element array (100) is combined into a Hall element, two Hall elements or four suddenly
That element.
9. the proframmable linear Hall sensor chip structure according to claim 2 for realizing on piece temperature compensation function,
It is characterized in that, the silicon Hall element array (100) includes the first Hall element (H1) and the second Hall element (H2), and
It is connected with each other.
10. the proframmable linear Hall sensor chip structure according to claim 2 for realizing on piece temperature compensation function,
It is characterized in that, the Hall element of the silicon Hall element array (100) uses cross Hall element.
11. the proframmable linear Hall sensor chip structure according to claim 3 for realizing on piece temperature compensation function,
It is characterized in that, the integrator (200) includes integrating capacitor, both ends respectively with silicon Hall element array (100) and electricity
Pressure amplifier and signal rectification module (300) are connected.
12. the proframmable linear Hall sensor chip knot according to claim 11 for realizing on piece temperature compensation function
Structure, which is characterized in that the integrating capacitor according to the demand of application end gear demand and adjusting step change coarse adjustment digit and
Fine tuning digit.
13. the proframmable linear Hall sensor chip knot according to claim 11 for realizing on piece temperature compensation function
Structure, which is characterized in that the integrating capacitor is composed in parallel by 8 binary weight capacitors and controlled by 8, for realizing 8
Fine tuning.
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