CN109616419B - Preparation method, array substrate and the liquid crystal display panel of thin film transistor (TFT) - Google Patents
Preparation method, array substrate and the liquid crystal display panel of thin film transistor (TFT) Download PDFInfo
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- CN109616419B CN109616419B CN201811344322.2A CN201811344322A CN109616419B CN 109616419 B CN109616419 B CN 109616419B CN 201811344322 A CN201811344322 A CN 201811344322A CN 109616419 B CN109616419 B CN 109616419B
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- 239000010409 thin film Substances 0.000 title claims abstract description 57
- 239000000758 substrate Substances 0.000 title claims abstract description 48
- 238000002360 preparation method Methods 0.000 title claims abstract description 47
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 239
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims abstract description 97
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910052733 gallium Inorganic materials 0.000 claims abstract description 56
- 229910052738 indium Inorganic materials 0.000 claims abstract description 55
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 54
- 239000004065 semiconductor Substances 0.000 claims abstract description 54
- 239000011787 zinc oxide Substances 0.000 claims abstract description 48
- 239000011241 protective layer Substances 0.000 claims abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 70
- 239000010408 film Substances 0.000 claims description 69
- 229910004205 SiNX Inorganic materials 0.000 claims description 62
- 238000000034 method Methods 0.000 claims description 45
- 229910052681 coesite Inorganic materials 0.000 claims description 39
- 229910052906 cristobalite Inorganic materials 0.000 claims description 39
- 239000000377 silicon dioxide Substances 0.000 claims description 39
- 229910052682 stishovite Inorganic materials 0.000 claims description 39
- 229910052905 tridymite Inorganic materials 0.000 claims description 39
- ZMXDDKWLCZADIW-UHFFFAOYSA-N N,N-Dimethylformamide Chemical compound CN(C)C=O ZMXDDKWLCZADIW-UHFFFAOYSA-N 0.000 claims description 35
- 239000000203 mixture Substances 0.000 claims description 35
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 239000002904 solvent Substances 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 9
- 238000001291 vacuum drying Methods 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 229910052758 niobium Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000000243 solution Substances 0.000 description 30
- 239000013078 crystal Substances 0.000 description 25
- 239000002033 PVDF binder Substances 0.000 description 23
- 229920002981 polyvinylidene fluoride Polymers 0.000 description 23
- 239000000463 material Substances 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 12
- 238000001755 magnetron sputter deposition Methods 0.000 description 12
- 150000001336 alkenes Chemical class 0.000 description 11
- 238000001069 Raman spectroscopy Methods 0.000 description 9
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 239000011521 glass Substances 0.000 description 8
- 238000007747 plating Methods 0.000 description 8
- 239000012528 membrane Substances 0.000 description 7
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 6
- 229910052725 zinc Inorganic materials 0.000 description 6
- 239000011701 zinc Substances 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 4
- 238000001237 Raman spectrum Methods 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000001035 drying Methods 0.000 description 4
- 239000000428 dust Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 4
- 239000004744 fabric Substances 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 230000010287 polarization Effects 0.000 description 4
- 238000004528 spin coating Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000005406 washing Methods 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 3
- 239000005977 Ethylene Substances 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 238000012512 characterization method Methods 0.000 description 3
- 238000003486 chemical etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000012769 display material Substances 0.000 description 1
- 125000002573 ethenylidene group Chemical group [*]=C=C([H])[H] 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920000131 polyvinylidene Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- AKJVMGQSGCSQBU-UHFFFAOYSA-N zinc azanidylidenezinc Chemical compound [Zn++].[N-]=[Zn].[N-]=[Zn] AKJVMGQSGCSQBU-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
- H01L21/441—Deposition of conductive or insulating materials for electrodes
- H01L21/445—Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Abstract
The present invention provides the preparation method, array substrate and liquid crystal display panel of a kind of thin film transistor (TFT).The preparation method of thin film transistor (TFT) on grid layer the following steps are included: form the first insulating layer of β type Kynoar；Indium gallium zinc oxide semiconductor layer is formed on the first insulating layer of the β type Kynoar；Source electrode and drain electrode is formed on the indium gallium zinc oxide semiconductor layer；Insulating protective layer is formed in the source electrode and drain electrode.The present invention can be improved the reliability of device.
Description
Technical field
The present invention relates to microelectronics technology more particularly to a kind of preparation method of thin film transistor (TFT), array substrate and
Liquid crystal display panel.
Background technique
Semiconductor display technology emerges different technological innovations in continuous development, and indium gallium zinc oxide semiconductor is made
The features such as novel display material, with carrier mobility height, turn-off characteristic is good, easy to industrialized production, is based on
The thin film transistor (TFT) of indium gallium zinc oxide semiconductor is also widely used in field of liquid crystal display.
But since indium gallium zinc oxide characteristic of semiconductor is easy by ultraviolet light, the influence of steam and foreign ion can be produced
It is abnormal that raw threshold voltage shift etc. easily causes characteristic, thus insulating protective layer is arranged in thin film transistor (TFT) and aoxidizes to indium gallium zinc
Nitride layer carries out insulation protection.The thin film transistor (TFT) for being typically based on indium gallium zinc oxide semiconductor includes being sequentially laminated on substrate
Grid layer, inorganic insulation protective layer, indium gallium zinc oxide layer, source electrode and drain electrode and inorganic insulation protective layer.Specifically, one
As use SiO2、SiNxAs inorganic insulation protective layer, it can play and foreign ion is prevented to spread, protect indium gallium zinc oxide layer
Effect, in addition, the inorganic insulation protective layer is formed using chemical vapor deposition.
However, due to using SiO2、SiNxInorganic insulation layer, so as to cause the voltage endurance capability of film transistor device
Deficiency, the problems such as being easy to happen electrostatic breakdown, thus thin film transistor (TFT) in the prior art has that reliability is low.
Summary of the invention
The present invention provides the preparation method, array substrate and liquid crystal display panel of a kind of thin film transistor (TFT), can be improved device
The reliability of part.
In a first aspect, the present invention provides a kind of preparation method of thin film transistor (TFT), method includes the following steps: in grid
The first insulating layer of β type Kynoar is formed on layer；Indium gallium zinc is formed on the first insulating layer of the β type Kynoar
Oxide semiconductor layer；Source electrode and drain electrode is formed on the indium gallium zinc oxide semiconductor layer；In the source electrode and drain electrode
Form insulating protective layer.
Second aspect, the present invention provides a kind of array substrate, including thin film transistor (TFT), and thin film transistor (TFT) includes successively
It is layered in the first insulating layer, indium gallium zinc oxide semiconductor layer, source electrode and the leakage of the grid layer, β type Kynoar on substrate
Pole and insulating protective layer, wherein the source electrode and drain electrode same layer setting.
The third aspect, the present invention provide a kind of liquid crystal display panel, including array substrate as described above and the array
The opposite substrate that substrate is oppositely arranged, and the layer of liquid crystal molecule being folded between the array substrate and opposite substrate.
Preparation method, array substrate and the liquid crystal display panel of thin film transistor (TFT) of the invention, the preparation of thin film transistor (TFT)
Method on grid layer the following steps are included: form the first insulating layer of β type Kynoar；In the β type Kynoar
The first insulating layer on formed indium gallium zinc oxide semiconductor layer；On the indium gallium zinc oxide semiconductor layer formed source electrode and
Drain electrode；Insulating protective layer is formed in the source electrode and drain electrode.The present invention passes through in grid layer and indium gallium zinc oxide semiconductor
Polyvinylidene fluoride material is utilized with resistant to chemical etching, weather-proof in the first insulating layer that β type Kynoar is formed between layer
Property, dielectric constant is high, breakdown characteristics are strong, can ultraviolet light the features such as, and use inorganic insulating membrane conduct in the prior art
The problems such as the case where protective layer, is compared, and can be improved the voltage endurance capability of film transistor device, is also not susceptible to electrostatic breakdown.Cause
And device reliability of the invention is higher.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to make simply to introduce, it should be apparent that, the accompanying drawings in the following description is this hair
Bright some embodiments for those of ordinary skill in the art without creative efforts, can be with root
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is the flow diagram of the preparation method for the thin film transistor (TFT) that the embodiment of the present invention one provides；
Fig. 2 a is the schematic diagram for showing the detailed process of film crystal tube preparation method of the invention；
Fig. 2 b is the schematic diagram for showing the detailed process of film crystal tube preparation method of the invention；
Fig. 2 c is the schematic diagram for showing the detailed process of film crystal tube preparation method of the invention；
Fig. 2 d is the schematic diagram for showing the detailed process of film crystal tube preparation method of the invention；
Fig. 2 e is the schematic diagram for showing the detailed process of film crystal tube preparation method of the invention；
Fig. 3 is the anti-breakdown voltage characteristics figure of β type the first insulating layer of Kynoar in the present invention；
Fig. 4 is the Raman spectrogram of β type the first insulating layer of Kynoar in the present invention；
Fig. 5 is longitudinal schematic diagram of thin film transistor (TFT) in a kind of array substrate of the offer of the embodiment of the present invention six；
Fig. 6 is a kind of structural schematic diagram for liquid crystal display panel that the embodiment of the present invention seven provides.
Description of symbols:
1-substrate；
2-grid layers；
First insulating layer of 3-β type Kynoar；
4-indium gallium zinc oxide semiconductor layers；
5-source electrodes；
6-drain electrodes；
7-insulating protective layers；
8-thin film transistor (TFT)s；
9-liquid crystal display panels；
91-array substrates；
92-opposite substrates；
93-layer of liquid crystal molecule.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
All other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.
Embodiment one
Fig. 1 is the preparation method flow diagram for the thin film transistor (TFT) that the embodiment of the present invention one provides.As shown in Figure 1, this
The preparation method for the thin film transistor (TFT) that embodiment provides can specifically include following steps:
S11, the first insulating layer that β type Kynoar is formed on grid layer.
S12, indium gallium zinc oxide semiconductor layer is formed on the first insulating layer of β type Kynoar；
S13, source electrode and drain electrode is formed on indium gallium zinc oxide semiconductor layer；
S14, insulating protective layer is formed in source electrode and drain electrode.
Specifically, indium gallium zinc oxide semiconductor layer characteristic in thin film transistor (TFT) is easy by ultraviolet light, steam and
The influence of foreign ion, the characteristics such as threshold voltage shift easily cause drift, it is therefore desirable to carry out insulation protection to it, thus need
Protective layer is formed in the two sides of indium gallium zinc oxide semiconductor layer, specific in this preparation method, in grid layer and indium gallium zinc oxygen
Between compound semiconductor layer, the first insulating layer of β type Kynoar is formed, forms source on indium gallium zinc oxide semiconductor layer
Pole and drain electrode, and insulating protective layer is formed in source electrode and drain electrode, by the first insulating layer of the β type Kynoar and
Insulating protective layer protects indium gallium zinc oxide semiconductor layer.
Polyvinylidene fluoride material has that resistant to chemical etching, weatherability, dielectric constant are high, breakdown characteristics are strong, can resist purple
The advantages that outer smooth.However, Kynoar usually has tri- kinds of crystal structures of α, β and γ, the wherein β and γ phase of Kynoar
Crystal form molecular chain structure makes intermolecular dipole moment very big since TTT conformation is presented, and shows good dielectric property, but γ phase
It is generally necessary to prepare at a higher temperature, it is unfavorable for mass production, colleague's dielectric property is also weaker than beta phase polyvinylidene fluoride.Mirror
In the dielectricity that β type Kynoar is excellent, present inventor selects β type Kynoar as the material of protective layer.
Thus, the present embodiment is compared with using the case where inorganic insulating membrane is as protective layer in the prior art, since β type is poly-
First insulating dielectric constants of vinylidene are higher, can be improved the voltage endurance capability of film transistor device, are also not susceptible to
The problems such as electrostatic breakdown.The present inventor has also carried out voltage endurance capability test to the thin film transistor (TFT) using this method preparation, tests
As a result, it has been found that the pressure voltage of thin film transistor (TFT) is promoted from 100V, 200V or so to 1000V, voltage endurance capability, which has, significantly to be mentioned
It rises.The thin film transistor (TFT) reliability thus prepared using the preparation method of the thin film transistor (TFT) of the present embodiment is higher.
Optionally, the first insulating layer that β type Kynoar is formed on grid layer includes that doping is formed on grid layer
There is SiO2And/or SiNxβ type Kynoar the first insulating layer.SiO is adulterated in β type polyvinylidene fluoride material2Or
SiNx, the content of the β type crystal in the first insulating layer of Kynoar can be increased, in order to make β type crystal content increasing
Add effect more significant, SiO can be adulterated simultaneously in β type polyvinylidene fluoride material2And SiNx。
As an alternative embodiment, to adulterate SiO simultaneously in β type polyvinylidene fluoride material2And SiNxFor
It is illustrated, the first insulating layer that β type Kynoar is formed on grid layer includes: to use n,N-Dimethylformamide as molten
α type Kynoar/SiO that agent compound concentration is 10%~30%2/SiNxBlend solution is applied to institute by homogeneous blend solution
It states on grid layer, then forms a film in 50~150 DEG C of vacuum drying 30min~60min；Wherein, α type polyvinylidene fluoride in blend solution
Alkene, SiO2、SiNxPercent mass ratio be (60~100): (0~20): (0~30), the film with a thickness of 150nm-
350nm.Certainly, herein, if SiO2、SiNxMass percent be 0 indicate, do not include in the homogeneous blend solution
SiO2、SiNx.That is, without doping in the first insulating layer of the β type Kynoar generated.If SiO2、SiNxQuality hundred
Divide than not indicated for 0, includes SiO in the homogeneous blend solution2、SiNx.That is, the first of the β type Kynoar generated is exhausted
Doped with SiO in edge layer2、SiNx。
In general, common polyvinylidene fluoride material long-chain molecule is mostly α type Kynoar, special intermolecular
The β type Kynoar with polarity spatial molecular structure can be just obtained under the action of active force and temperature and other external force,
Thus β type Kynoar is prepared with α type Kynoar in the present embodiment.Meanwhile using α type Kynoar/SiO2/
SiNxHomogeneous blend solution, i.e., doped with SiO in α type Kynoar solution2、SiNxAs described above, being to increase life
The content of β type crystal in first insulating layer of the β type Kynoar after, so that the first of β type Kynoar insulate
The dielectricity of layer is more preferably.In addition, in this method, by α type Kynoar/SiO2/SiNxHomogeneous blend solution coating is in grid layer
On, then after 50~150 DEG C of vacuum drying 30min~60min, solvent volatilization, just formed doped with SiO2、SiNxβ type it is poly-
Vinylidene.Can be there are many coating method in addition, blend solution is applied on the grid layer, such as can choose rotation
Rubbing method and slot coated method, the invention is not limited in this regard, as long as can will be on blend solution even spread to grid layer
It can.
In addition, inorganic insulation protective layer is formed in the prior art using chemical vapour deposition technique, higher cost, and
Had using the method in the present embodiment easy to operation, raw material is cheap and easy to get, with short production cycle, easy processing, can operate strong
The advantages that, production cost is reduced significantly.
Further, in source electrode and drain electrode formed insulating protective film include: in source electrode and drain electrode formed doped with
SiO2And/or SiNxβ type Kynoar second insulating layer.In this way, equal in indium gallium zinc oxide semiconductor layer two sides
Provided with β type Kynoar insulating layer, due to the unique high dielectric constant characteristic of β type polyvinylidene fluoride material, ultraviolet light
Etc. characteristics, protect indium gallium zinc oxide semiconductor layer not influenced by steam, foreign ion and ultraviolet light, so that according to this system
The antistatic breakdown capability for the thin film transistor (TFT) that Preparation Method is produced is strong, avoids gallium zinc oxide semiconductor layer by ultraviolet light
Property variation caused by influence.In addition, identically as the formation of above-mentioned first insulating layer, in the process for forming second insulating layer
In, SiO is adulterated in β type polyvinylidene fluoride material2Or SiNx, the β type crystalline substance in the second insulating layer of Kynoar can be increased
The content of body can be in β type polyvinylidene fluoride material simultaneously in order to keep the increase effect of content of β type crystal more significant
Adulterate SiO2And SiNx。
Optionally, to adulterate SiO simultaneously in β type polyvinylidene fluoride material2And SiNxFor come when being illustrated, in source
The step of forming the second insulating layer of β type Kynoar in pole and drain electrode forms β type polyvinylidene fluoride with above-mentioned on grid layer
The step of first insulating layer of alkene, is identical, that is, includes: that n,N-Dimethylformamide is used to prepare mass percent concentration as solvent
For 10%~30% α type Kynoar/SiO2/SiNxThe blend solution is applied to the source electrode by homogeneous blend solution
In drain electrode, then form a film in 50~150 DEG C of vacuum drying 30min~60min；Wherein, α type gathers inclined fluorine in the blend solution
Ethylene, SiO2、SiNxPercent mass ratio be (60~100): (0~20): (0~30), the film with a thickness of 150nm-
350nm.So, it is provided in indium gallium zinc oxide semiconductor layer two sides doped with SiO2、SiNxβ type polyvinylidene fluoride
Alkene insulating layer.Certainly, herein, if SiO2、SiNxMass percent be 0 indicate, do not include in the homogeneous blend solution
SiO2、SiNx.That is, without doping in the second insulating layer of the β type Kynoar generated.If SiO2、SiNxQuality hundred
Divide than not indicated for 0, includes SiO in the homogeneous blend solution2、SiNx.That is, the second of the β type Kynoar generated is exhausted
Doped with SiO in edge layer2、SiNx。
Optionally, it is formed on grid layer before the first insulating layer of β type Kynoar, further includes being formed on substrate
The step of grid layer.Also, it can also include the steps that cleaning base plate before forming grid layer on substrate.
Optional grid layer, source electrode, drain electrode film thickness be 150nm~300nm, grid layer, source electrode, drain electrode are by metal shape
At, and the metal that grid layer, source electrode, drain electrode use is selected from least one of Cu, Al, Mo, Ti, Nb, Ag.For forming grid
Pole layer, source electrode, drain electrode metal, can be one of Cu, Al, Mo, Ti, Nb, Ag, be also possible to Cu, Al, Mo, Ti, Nb,
Two or more combination in Ag.For example, can be the gold that 30nm is first laminated when the metal of grid layer selects Cu, Ti
Belong to Ti, then the Cu of 120nm is laminated, so as to form the grid with a thickness of 150nm.Selection for metal species, and formed thick
The selection of degree can be selected according to actual needs, and the invention is not limited thereto illustrates.
The preparation method of thin film transistor (TFT) in the present embodiment gathers inclined fluorine the following steps are included: forming β type on grid layer
First insulating layer of ethylene；Indium gallium zinc oxide semiconductor layer is formed on the first insulating layer of β type Kynoar；In indium gallium
Source electrode and drain electrode is formed on zinc oxide semiconductor layer；Insulating protective layer is formed in source electrode and drain electrode.The present embodiment by
The first insulating layer that β type Kynoar is formed between grid layer and indium gallium zinc oxide semiconductor layer, is utilized polyvinylidene fluoride
Alkene material have the characteristics that resistant to chemical etching, weatherability, dielectric constant are high, breakdown characteristics are strong, can ultraviolet light, and it is existing
It is compared using inorganic insulating membrane as the case where protective layer in technology, since the first insulating dielectric of β type Kynoar is normal
Number is higher, the problems such as can be improved the voltage endurance capability of film transistor device, be also not susceptible to electrostatic breakdown.Thus use this reality
It is higher to apply the thin film transistor (TFT) reliability that the preparation method of the thin film transistor (TFT) of example is prepared.
Embodiment two
Fig. 2 a~Fig. 2 e is the schematic diagram for showing the detailed process of film crystal tube preparation method of the invention.In embodiment
On the basis of one, the present embodiment enumerates specific example, process conditions, technological parameter to each step in previous embodiment one
Etc. being further explained, for the part being the same as example 1, details are not described herein again.
The preparation method of the thin film transistor (TFT) of the present embodiment, comprising the following steps:
1) ultrasonic washing instrument is used, it is first that the acetone of 10cm × 10cm × 0.5mm glass substrate 1 or alcohol is super
Sound cleans 30 minutes removal surface organic matters and bulky grain, takes out cleaned using with spirituous non-dust cloth later, then
5min is cleaned by pure water, using nitrogen injection, until drying is stand-by.
2) as shown in Figure 2 a, on the glass substrate 1 after step 1) cleaning, grid is prepared using magnetron sputtering membrane process
Layer 2, specifically, being initially formed Ti layers of metal of 30nm, re-forms the Ni metal layer (not shown) of 120nm, thus on Ti layers
Form the grid layer 2 of 150nm.
3) as shown in Figure 2 b, using n,N-Dimethylformamide (DMF) to prepare mass percent concentration as solvent is 10%
α type Kynoar/SiO2/SiNx(α type Kynoar relative molecular mass distribution is 91000~107000, SiO2/
SiNxParticle size is distributed as 5nm~8nm) homogeneous blend solution, the blend solution is applied to using method of spin coating
On the grid layer 2 formed in step 2), after being then dried in vacuo 30min~60min under conditions of 50 DEG C, be solidified into a thickness of
The film of 350nm, to be formed doped with SiO2、SiNxβ type Kynoar the first insulating layer 3.
Wherein, α type Kynoar, SiO in the blend solution2、SiNxPercent mass ratio be 95:1:4.It will be at
The tables such as β type Kynoar insulating layer Raman spectrum, dielectric constant instrument, petrographic microscope and scanning electron microscope after film
Sign means confrontation breakdown voltage, crystal structure, dielectric constant etc. are measured.Measurement result is that anti-breakdown voltage is 1350V,
Dielectric constant is 12.6.Fig. 3 is the anti-breakdown voltage characteristics figure of β type the first insulating layer of Kynoar in the present invention, wherein
Horizontal axis is electric field, and the longitudinal axis is polarization intensity, and You Tuzhong is it is also seen that the poly- inclined fluorine prepared using the method for the present embodiment two
The anti-breakdown voltage of ethylene insulating film layer is 1350V.Fig. 4 is the Raman of β type the first insulating layer of Kynoar in the present invention
Spectrogram.Wherein, horizontal axis is Raman shift, and the longitudinal axis is optical absorption peak intensity.It can be observed out by Fig. 4 and use the present embodiment two
The Kynoar insulating film layer prepared of method there is beta crystal eigen vibration peak, the i.e. 838- type of β type Kynoar
Vibration peak illustrates that this preparation method can prepare distinctive β type Kynoar insulating film layer.
4) magnetron sputtering plating work is used on the β type Kynoar insulating film 3 as shown in Figure 2 c, generated in step 3)
Skill prepares indium gallium zinc oxide semiconductor layer 4, and form a film partial pressure of oxygen 3%, and film forming chamber pressure chamber is 3mTorr, and film layer thickness is 60nm,
Sputtering power is 120kw.
5) on the indium gallium zinc oxide semiconductor layer 4 as shown in Figure 2 d, generated in step 4), magnetron sputtering plating is used
Technique prepares source electrode 5 and drain electrode 6, specifically, being initially formed Ti layers of metal of 30nm, the metal of 120nm is re-formed on Ti layers
Cu layers (not shown), the source electrode 5 with a thickness of 150nm and drain electrode 6 is consequently formed.
6) on the source electrode 5 and drain electrode 6 as shown in Figure 2 e, generated in the step 5), using technique identical with step 3) and
Condition preparation, system are formed doped with SiO2、SiNxThe β type Kynoar with a thickness of 350nm second insulating layer 7.Herein
The second insulating layer of β type Kynoar has excellent ultraviolet light characteristic.It can thus be avoided ultraviolet light causes indium gallium zinc
Oxide semiconductor layer characteristic is deteriorated, and can be improved TFT device threshold voltage stability.
The present embodiment is each formed with the β type polyvinylidene fluoride with a thickness of 350nm in the two sides of indium gallium zinc oxide semiconductor layer
Alkene insulating film layer, can not only improve the voltage endurance capability of film transistor device, also can be avoided ultraviolet light and aoxidize to indium gallium zinc
The thin film transistor (TFT) for influencing caused by object semiconductor layer, thus being prepared using the preparation method of the thin film transistor (TFT) of the present embodiment
Reliability is higher.
Embodiment three
On the basis of example 1, the present embodiment enumerates specific example, to each step in previous embodiment one
Process conditions, technological parameter etc. are further explained, and for the part being the same as example 1, details are not described herein again.
The preparation method of the thin film transistor (TFT) of the present embodiment, comprising the following steps:
1) ultrasonic washing instrument is used, it is first that the acetone of 10cm × 10cm × 0.5mm glass substrate 1 or alcohol is super
Sound cleans 30 minutes removal surface organic matters and bulky grain, takes out cleaned using with spirituous non-dust cloth later, then
5min is cleaned by pure water, using nitrogen injection, until drying is stand-by.
2) as shown in Figure 2 a, on the glass substrate 1 after step 1) cleaning, grid is prepared using magnetron sputtering membrane process
Layer 2, specifically, being initially formed Ti layers of metal of 30nm, re-forms the Ni metal layer (not shown) of 170nm, thus on Ti layers
Form the grid layer 2 of 200nm.
3) as shown in Figure 2 b, using n,N-Dimethylformamide (DMF) to prepare mass percent concentration as solvent is 10%
α type Kynoar/SiO2/SiNx(α type Kynoar relative molecular mass distribution is 91000~107000, SiO2/
SiNxParticle size is distributed as 5nm~8nm) homogeneous blend solution, the blend solution is applied to using method of spin coating
On the grid layer 2 formed in step 2), after being then dried in vacuo 30min~60min under conditions of 80 DEG C, be solidified into a thickness of
The film of 300nm, to be formed doped with SiO2、SiNxβ type Kynoar the first insulating layer 3.
Wherein, α type Kynoar, SiO in the blend solution2、SiNxPercent mass ratio be 90:2:8.In addition,
This is dried in vacuo under conditions of being in 80 DEG C, and compared with 50 DEG C of condition in embodiment two, temperature is increased, and can be increased molten
The evaporation rate of agent accelerates the speed of film-forming, so that it is brilliant to improve β type in the first insulating layer 3 of β type Kynoar
The content of body.By β type Kynoar insulating layer Raman spectrum, dielectric constant instrument, petrographic microscope and the scanning after film forming
The characterization methods such as electron microscope confrontation breakdown voltage, crystal structure, dielectric constant etc. are measured.Measurement result is to resist
Wearing voltage is 1100V, dielectric constant 10.4.Fig. 3 is the anti-breakdown potential of β type the first insulating layer of Kynoar in the present invention
Press performance plot, wherein horizontal axis is electric field, and the longitudinal axis is polarization intensity, You Tuzhong it is also seen that using the present embodiment three method
The anti-breakdown voltage for the Kynoar insulating film layer prepared is 1100V.Fig. 4 is the β type Kynoar in the present invention
The Raman spectrogram of one insulating layer.Wherein, horizontal axis is Raman shift, and the longitudinal axis is optical absorption peak intensity.Can be observed by Fig. 4 makes
There is the beta crystal feature vibration of β type Kynoar in the Kynoar insulating film layer prepared with the method for the present embodiment three
Dynamic peak, i.e. 838- type vibration peak, illustrate that this preparation method can prepare distinctive β type Kynoar insulating film layer.
4) magnetron sputtering plating work is used on the β type Kynoar insulating film 3 as shown in Figure 2 c, generated in step 3)
Skill prepares indium gallium zinc oxide semiconductor layer 4, and form a film partial pressure of oxygen 4%, and film forming chamber pressure chamber is 3.5mTorr, and film layer thickness is
50nm, sputtering power 110kw.
5) on the indium gallium zinc oxide semiconductor layer 4 as shown in Figure 2 d, generated in step 4), magnetron sputtering plating is used
Technique prepares source electrode 5 and drain electrode 6, specifically, being initially formed Ti layers of metal of 30nm, the metal of 170nm is re-formed on Ti layers
Cu layers (not shown), the source electrode 5 with a thickness of 200nm and drain electrode 6 is consequently formed.
6) on the source electrode 5 and drain electrode 6 as shown in Figure 2 e, generated in the step 5), using technique identical with step 3) and
Condition preparation, system are formed doped with SiO2、SiNxThe β type Kynoar with a thickness of 300nm second insulating layer 7.Herein
The second insulating layer of β type Kynoar has excellent ultraviolet light characteristic.It can thus be avoided ultraviolet light causes indium gallium zinc
Oxide semiconductor layer characteristic is deteriorated, and can be improved TFT device threshold voltage stability.
The present embodiment is each formed with the β type polyvinylidene fluoride with a thickness of 300nm in the two sides of indium gallium zinc oxide semiconductor layer
Alkene insulating film layer, can not only improve the voltage endurance capability of film transistor device, also can be avoided ultraviolet light and aoxidize to indium gallium zinc
The thin film transistor (TFT) for influencing caused by object semiconductor layer, thus being prepared using the preparation method of the thin film transistor (TFT) of the present embodiment
Reliability is higher.
Example IV
On the basis of example 1, the present embodiment enumerates specific example, to each step in previous embodiment one
Process conditions, technological parameter etc. are further explained, and for the part being the same as example 1, details are not described herein again.
The preparation method of the thin film transistor (TFT) of the present embodiment, comprising the following steps:
1) ultrasonic washing instrument is used, it is first that the acetone of 10cm × 10cm × 0.5mm glass substrate 1 or alcohol is super
Sound cleans 30 minutes removal surface organic matters and bulky grain, takes out cleaned using with spirituous non-dust cloth later, then
5min is cleaned by pure water, using nitrogen injection, until drying is stand-by.
2) as shown in Figure 2 a, on the glass substrate 1 after step 1) cleaning, grid is prepared using magnetron sputtering membrane process
Layer 2, specifically, being initially formed Ti layers of metal of 30nm, re-forms the Ni metal layer (not shown) of 220nm, thus on Ti layers
Form the grid layer 2 of 250nm.
3) as shown in Figure 2 b, using n,N-Dimethylformamide (DMF) to prepare mass percent concentration as solvent is 10%
α type Kynoar/SiO2/SiNx(α type Kynoar relative molecular mass distribution is 91000~107000, SiO2/
SiNxParticle size is distributed as 5nm~8nm) homogeneous blend solution, the blend solution is applied to using method of spin coating
On the grid layer 2 formed in step 2), after being then dried in vacuo 30min~60min under conditions of 120 DEG C, it is solidified into thickness
For the film of 250nm, to be formed doped with SiO2、SiNxβ type Kynoar the first insulating layer 3.
Wherein, α type Kynoar, SiO in the blend solution2、SiNxPercent mass ratio be 85:5:10.This
Outside, this is dried in vacuo under conditions of being in 120 DEG C, with 50 DEG C in embodiment two, in embodiment three compared with 80 DEG C of condition,
Temperature increases, and the evaporation rate that can increase solvent accelerates the speed of film-forming, to improve β type Kynoar
The content of β type crystal in first insulating layer 3.By β type Kynoar insulating layer Raman spectrum, the dielectric constant after film forming
The characterization methods such as instrument, petrographic microscope and scanning electron microscope fight the amounts of progress such as breakdown voltage, crystal structure, dielectric constant
It surveys.Measurement result is that anti-breakdown voltage is 800V, dielectric constant 8.9.Fig. 3 is the β type Kynoar first in the present invention
The anti-breakdown voltage characteristics figure of insulating layer, wherein horizontal axis is electric field, and the longitudinal axis is polarization intensity, and You Tuzhong is it is also seen that use
The anti-breakdown voltage for the Kynoar insulating film layer that the method for the present embodiment four is prepared is 800V.Fig. 4 is the β in the present invention
The Raman spectrogram of the first insulating layer of type Kynoar.Wherein, horizontal axis is Raman shift, and the longitudinal axis is optical absorption peak intensity.By
Fig. 4 can observe that β type polyvinylidene fluoride occurs in the Kynoar insulating film layer prepared using the method for the present embodiment four
The beta crystal eigen vibration peak of alkene, i.e. 838- type vibration peak illustrate that this preparation method can prepare distinctive β type polyvinylidene fluoride
Alkene insulating film layer.
4) magnetron sputtering plating work is used on the β type Kynoar insulating film 3 as shown in Figure 2 c, generated in step 3)
Skill prepares indium gallium zinc oxide semiconductor layer 4, and form a film partial pressure of oxygen 5%, and film forming chamber pressure chamber is 4mTorr, and film layer thickness is 40nm,
Sputtering power is 100kw.
5) on the indium gallium zinc oxide semiconductor layer 4 as shown in Figure 2 d, generated in step 4), magnetron sputtering plating is used
Technique prepares source electrode 5 and drain electrode 6, specifically, being initially formed Ti layers of metal of 30nm, the metal of 220nm is re-formed on Ti layers
Cu layers (not shown), the source electrode 5 with a thickness of 250nm and drain electrode 6 is consequently formed.
6) on the source electrode 5 and drain electrode 6 as shown in Figure 2 e, generated in the step 5), using technique identical with step 3) and
Condition preparation, system are formed doped with SiO2、SiNxThe β type Kynoar with a thickness of 250nm second insulating layer 7.Herein
The second insulating layer of β type Kynoar has excellent ultraviolet light characteristic.It can thus be avoided ultraviolet light causes indium gallium zinc
Oxide semiconductor layer characteristic is deteriorated, and can be improved TFT device threshold voltage stability.
The present embodiment is each formed with the β type polyvinylidene fluoride with a thickness of 250nm in the two sides of indium gallium zinc oxide semiconductor layer
Alkene insulating film layer, can not only improve the voltage endurance capability of film transistor device, also can be avoided ultraviolet light and aoxidize to indium gallium zinc
The thin film transistor (TFT) for influencing caused by object semiconductor layer, thus being prepared using the preparation method of the thin film transistor (TFT) of the present embodiment
Reliability is higher.
Embodiment five
On the basis of example 1, the present embodiment enumerates specific example, to each step in previous embodiment one
Process conditions, technological parameter etc. are further explained, and for the part being the same as example 1, details are not described herein again.
The preparation method of the thin film transistor (TFT) of the present embodiment, comprising the following steps:
1) ultrasonic washing instrument is used, it is first that the acetone of 10cm × 10cm × 0.5mm glass substrate 1 or alcohol is super
Sound cleans 30 minutes removal surface organic matters and bulky grain, takes out cleaned using with spirituous non-dust cloth later, then
5min is cleaned by pure water, using nitrogen injection, until drying is stand-by.
2) as shown in Figure 2 a, on the glass substrate 1 after step 1) cleaning, grid is prepared using magnetron sputtering membrane process
Layer 2, specifically, being initially formed Ti layers of metal of 30nm, re-forms the Ni metal layer (not shown) of 270nm, thus on Ti layers
Form the grid layer 2 of 300nm.
3) as shown in Figure 2 b, using n,N-Dimethylformamide (DMF) to prepare mass percent concentration as solvent is 10%
α type Kynoar/SiO2/SiNx(α type Kynoar relative molecular mass distribution is 91000~107000, SiO2/
SiNxParticle size is distributed as 5nm~8nm) homogeneous blend solution, the blend solution is applied to using method of spin coating
On the grid layer 2 formed in step 2), after being then dried in vacuo 30min~60min under conditions of 150 DEG C, it is solidified into thickness
For the film of 200nm, to be formed doped with SiO2、SiNxβ type Kynoar the first insulating layer 3.
Wherein, α type Kynoar, SiO in the blend solution2、SiNxPercent mass ratio be 80:8:12.This
Outside, this is dried in vacuo under conditions of being in 150 DEG C, and 50 DEG C in embodiment two, 80 DEG C in embodiment three, in example IV
120 DEG C of condition is compared, and temperature increases, and the evaporation rate that can increase solvent accelerates the speed of film-forming, to mention
The content of β type crystal in first insulating layer 3 of high β type Kynoar.It is however noted that due to vacuum drying temperature
When spending high, the evaporation rate that will lead to solvent is too fast, and it is brilliant to reduce β type in the first insulating layer 3 of β type Kynoar instead
The content of body.Thus in the present invention, it is preferred to vacuum drying temperature be 80 DEG C, 120 DEG C, to guarantee the speed of solvent volatilization
Will not too fast, also will not be excessively slow, contain to farthest improve β type crystal in first insulating layer 3 of β type Kynoar
Amount.β type Kynoar insulating layer Raman spectrum, dielectric constant instrument, petrographic microscope and scanning electron after film forming is shown
The characterization methods such as micro mirror confrontation breakdown voltage, crystal structure, dielectric constant etc. are measured.Measurement result is anti-breakdown voltage
For 650V, dielectric constant 7.6.Fig. 3 is the anti-breakdown voltage characteristics of β type the first insulating layer of Kynoar in the present invention
Figure, wherein horizontal axis is electric field, and the longitudinal axis is polarization intensity, and You Tuzhong using the method for the present embodiment five it is also seen that prepared
Kynoar insulating film layer anti-breakdown voltage be 650V.Fig. 4 is β type the first insulating layer of Kynoar in the present invention
Raman spectrogram.Wherein, horizontal axis is Raman shift, and the longitudinal axis is optical absorption peak intensity.It can be observed by Fig. 4 and use this implementation
There is the beta crystal eigen vibration peak, i.e. of β type Kynoar in the Kynoar insulating film layer that the method for example five is prepared
838- type vibration peak illustrates that this preparation method can prepare distinctive β type Kynoar insulating film layer.
4) magnetron sputtering plating work is used on the β type Kynoar insulating film 3 as shown in Figure 2 c, generated in step 3)
Skill prepares indium gallium zinc oxide semiconductor layer 4, and form a film partial pressure of oxygen 6%, and film forming chamber pressure chamber is 4.5mTorr, and film layer thickness is
30nm, sputtering power 90kw.
5) on the indium gallium zinc oxide semiconductor layer 4 as shown in Figure 2 d, generated in step 4), magnetron sputtering plating is used
Technique prepares source electrode 5 and drain electrode 6, specifically, being initially formed Ti layers of metal of 30nm, the metal of 270nm is re-formed on Ti layers
Cu layers (not shown), the source electrode 5 with a thickness of 300nm and drain electrode 6 is consequently formed.
6) on the source electrode 5 and drain electrode 6 as shown in Figure 2 e, generated in the step 5), using technique identical with step 3) and
Condition preparation, system are formed doped with SiO2、SiNxThe β type Kynoar with a thickness of 200nm second insulating layer 7.Herein
The second insulating layer of β type Kynoar has excellent ultraviolet light characteristic.It can thus be avoided ultraviolet light causes indium gallium zinc
Oxide semiconductor layer characteristic is deteriorated, and can be improved TFT device threshold voltage stability.
The present embodiment is each formed with the β type polyvinylidene fluoride with a thickness of 200nm in the two sides of indium gallium zinc oxide semiconductor layer
Alkene insulating film layer, can not only improve the voltage endurance capability of film transistor device, also can be avoided ultraviolet light and aoxidize to indium gallium zinc
The thin film transistor (TFT) for influencing caused by object semiconductor layer, thus being prepared using the preparation method of the thin film transistor (TFT) of the present embodiment
Reliability is higher.
Embodiment six
Fig. 5 is longitudinal schematic diagram of thin film transistor (TFT) in a kind of array substrate of the offer of the embodiment of the present invention six.Such as Fig. 5 institute
Show, the present embodiment provides a kind of array substrate (not shown), including thin film transistor (TFT) 8, and thin film transistor (TFT) 8 includes successively layer
The first insulating layer 3, indium gallium zinc oxide semiconductor layer 4,5 and of source electrode of folded grid layer 2 on substrate 1, β type Kynoar
Drain electrode 6 and insulating protective layer 7, wherein source electrode 5 and drain electrode 6 same layers setting.
Optionally, the first insulating layer 3 of β type Kynoar is doped with SiO2And/or SiNx.In β type Kynoar material
SiO is adulterated in material2Or SiNx, it is the content in order to increase the β type crystal in the first insulating layer 3 of Kynoar, certainly, if
Adulterate SiO simultaneously in β type polyvinylidene fluoride material2And SiNxThe content of β type crystal can be made to further increase.In addition, based on same
The reason of sample, insulating protective layer 7 are also possible to doped with SiO2And/or SiNxβ type Kynoar second insulating layer 7.
Optionally, the thin film transistor (TFT) of the present embodiment is also possible to using described in any one of 1~embodiment of embodiment 6
The thin film transistor (TFT) that the preparation method of thin film transistor (TFT) is produced.
Array substrate provided in this embodiment, due to being equipped with β type Kynoar in the thin film transistor (TFT) that it includes
First insulating layer, thus the voltage endurance capability of film transistor device can not only be improved, it also can be avoided ultraviolet light to indium gallium zinc
It is influenced caused by oxide semiconductor layer, thus the reliability of the array substrate of the present embodiment is higher.
Embodiment seven
Fig. 6 is a kind of structural schematic diagram for liquid crystal display panel that the embodiment of the present invention seven provides.As shown in fig. 6, this reality
The liquid crystal display panel 9 for applying example, pair being oppositely arranged including array substrate 91 described in embodiment six and the array substrate 91
To substrate 92, and the layer of liquid crystal molecule 93 being folded between the array substrate and opposite substrate.Array substrate 91 it is specific
Structure, function and working principle have been described in detail in previous embodiment six, and details are not described herein again.
Liquid crystal display panel provided in this embodiment, due to being equipped with β type polyvinylidene fluoride in the thin film transistor (TFT) that it includes
First insulating layer of alkene, thus the voltage endurance capability of film transistor device can not only be improved, it also can be avoided ultraviolet light to indium
It is influenced caused by gallium zinc oxide semiconductor layer, thus the reliability of the liquid crystal display panel of the present embodiment is higher.
In the description of the present invention, it is to be understood that, term " on ", "lower", "front", "rear", "left", "right", " perpendicular
Directly ", the orientation or positional relationship of the instructions such as "horizontal", "top", "bottom", "inner", "outside" is orientation based on the figure or position
Relationship is set, is merely for convenience of description of the present invention and simplification of the description, rather than the device or element of indication or suggestion meaning are necessary
It with specific orientation, is constructed and operated in a specific orientation, therefore is not considered as limiting the invention.
In addition, in the present invention unless specifically defined or limited otherwise, term " connection ", " connected ", " fixation ", " peace
Dress " etc. shall be understood in a broad sense, such as can be mechanical connection, be also possible to be electrically connected；It can be and be directly connected to, can also pass through
Intermediary is indirectly connected, and can be the connection inside two elements or the interaction relationship of two elements, unless otherwise bright
True restriction, for the ordinary skill in the art, can understand as the case may be above-mentioned term in the present invention
Concrete meaning.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (9)
1. a kind of preparation method of thin film transistor (TFT), which comprises the following steps:
The first insulating layer of β type Kynoar is formed on grid layer；
Indium gallium zinc oxide semiconductor layer is formed on the first insulating layer of the β type Kynoar；
Source electrode and drain electrode is formed on the indium gallium zinc oxide semiconductor layer；
Insulating protective layer is formed in the source electrode and drain electrode；
It is described on grid layer formed β type Kynoar the first insulating layer include:
Use the α type Kynoar, SiO that n,N-Dimethylformamide is 10%~30% as solvent compound concentration2、SiNx?
The blend solution is applied on the grid layer by even blend solution, then 50~150 DEG C of vacuum drying 30min~
60min film forming；
Wherein, α type Kynoar, SiO in the blend solution2、SiNxPercent mass ratio be (60~100): (0~
20): (0~30), the film with a thickness of 150nm-350nm.
2. the preparation method of thin film transistor (TFT) according to claim 1, which is characterized in that
It is described on grid layer formed β type Kynoar the first insulating layer include on the grid layer formed doped with
SiO2And/or SiNxβ type Kynoar the first insulating layer.
3. the preparation method of thin film transistor (TFT) according to claim 1 or 2, which is characterized in that
It is described in source electrode and drain electrode formed insulating protective layer include:
It is formed in the source electrode and drain electrode doped with SiO2And/or SiNxβ type Kynoar second insulating layer.
4. the preparation method of thin film transistor (TFT) according to claim 1 or 2, which is characterized in that
It is described in the source electrode and drain electrode formed insulating protective layer include:
Use the α type Kynoar, SiO that n,N-Dimethylformamide is 10%~30% as solvent compound concentration2、SiNx?
The blend solution is applied in the source electrode and drain electrode by even blend solution, then in 50~150 DEG C of vacuum drying 30min
~60min film forming；
Wherein, α type Kynoar, SiO in the blend solution2、SiNxPercent mass ratio be (60~100): (0~
20): (0~30), the film with a thickness of 150nm-350nm.
5. the preparation method of thin film transistor (TFT) according to claim 1 or 2, which is characterized in that the shape on grid layer
It further include that the grid layer is formed on substrate before the first insulating layer at β type Kynoar.
6. the preparation method of thin film transistor (TFT) according to claim 1 or 2, which is characterized in that
The grid layer, source electrode, drain electrode film thickness be 150nm~300nm, the grid layer, source electrode, drain electrode are by metal shape
At, and the metal that the grid layer, source electrode, drain electrode use is selected from least one of Cu, Al, Mo, Ti, Nb, Ag.
7. a kind of array substrate, including thin film transistor (TFT), which is characterized in that the thin film transistor (TFT) includes being sequentially laminated on substrate
On grid layer, β type Kynoar the first insulating layer, indium gallium zinc oxide semiconductor layer, source electrode and drain electrode and insulation
Protective layer, wherein the source electrode and drain electrode same layer setting；
First insulating layer of the β type Kynoar is made by the following method:
Use the α type Kynoar, SiO that n,N-Dimethylformamide is 10%~30% as solvent compound concentration2、SiNx?
The blend solution is applied on the grid layer by even blend solution, then 50~150 DEG C of vacuum drying 30min~
60min film forming；
Wherein, α type Kynoar, SiO in the blend solution2、SiNxPercent mass ratio be (60~100): (0~
20): (0~30), the film with a thickness of 150nm-350nm.
8. array substrate according to claim 7, which is characterized in that the first insulating layer of the β type Kynoar is mixed
It is miscellaneous to have SiO2And/or SiNx。
9. a kind of liquid crystal display panel, which is characterized in that including array substrate as claimed in claim 7 or 8 and the array
The opposite substrate that substrate is oppositely arranged, and the layer of liquid crystal molecule being folded between the array substrate and opposite substrate.
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