CN109614261A - Hardware watchdog circuit and single-chip computer control system with the monitoring of task timing - Google Patents
Hardware watchdog circuit and single-chip computer control system with the monitoring of task timing Download PDFInfo
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- CN109614261A CN109614261A CN201811514894.0A CN201811514894A CN109614261A CN 109614261 A CN109614261 A CN 109614261A CN 201811514894 A CN201811514894 A CN 201811514894A CN 109614261 A CN109614261 A CN 109614261A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
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Abstract
The invention discloses a kind of hardware watchdog circuits with the monitoring of task timing, it is monitored for the gating signal to multiway analog switch, including watchdog circuit, 7 binary counters, memory, electrification reset RC circuit up/down counter synchronous with the decimal system.Hardware watchdog circuit and single-chip computer control system with the monitoring of task timing of the invention, compared with traditional BIT detection, 7 binary counters and memory are integrated with watchdog circuit, comprehensive design will be carried out to the monitoring of the timing of multiway analog switch gating signal and hardware watchdog circuit, not only solve the real-time detection problem to timesharing Mission Monitor, and reduce software complexity, reduce the complexity of circuit, improve the reliability and safety of system, it can avoid signal caused by due to gating signal does not gate chronologically to misread, it influences the realization of control function or causes to malfunction, solution is provided to the Embedded Applications such as timing monitoring need to be carried out.
Description
Technical field
The present invention relates to technical field of single chip microcomputer, particularly, be related to it is a kind of with task timing monitoring hardware guard the gate
Dog circuit.Moreover, it relates to a kind of single-chip microcontroller control including the above-mentioned hardware watchdog circuit with the monitoring of task timing
System processed.
Background technique
It is using one for raising system reliability and testability, the acquisition of analog quantity in current monolithic machine application system
Converter gates the channel of multiway analog switch by timesharing to select the signal for needing to convert.To ensure to the correct of signal
Sampling, need to be monitored the multiway analog switch gating signal of output, to avoid because believing caused by switching not chronologically gating
It number misreads, influences the realization of control function or cause to malfunction, and realize this functional requirement, take current BIT (Built In
The examination of Test built-in self test) mainstream technology of test need to increase signaling interface, it is realized by additional test circuit to gating signal
Detection, increase the complexity of circuit, meanwhile, software complexity need to be increased by the logic detection of software realization failure,
And software needs periodic duty main task, cannot achieve real-time monitoring.
Summary of the invention
The present invention provides a kind of hardware watchdog circuits with the monitoring of task timing, are used with solving existing single-chip microcontroller
BIT tests the technical problem that existing circuit complexity is high, software complexity is high.
An invention according to the present invention, provides a kind of hardware watchdog circuit with the monitoring of task timing, for more
The gating signal of path analoging switch is monitored,
Including watchdog circuit, 7 binary counters, memory, electrification reset RC circuit plus/minus synchronous with the decimal system
Counter；
Watchdog circuit is resetted for control single chip computer；
Memory is fed dog and is instructed to watchdog circuit for storing timing nested operation logic and output；
7 binary counters, for being counted to timing；
Electrification reset RC circuit, for make in system electrification watchdog circuit reset terminal keep low level and make ten into
Synchronous up/down counter is made to reset；
Be used to carry out adding deduct to the reset pulse counting and carrying out of the synchronous up/down counter of the decimal system counts latch and defeated
Be out of order signal；
Electrification reset RC circuit for connecting to power supply, electrification reset RC circuit also respectively with watchdog circuit and the decimal system
Synchronous up/down counter connection, memory for being connect with multiway analog switch, memory also respectively with 7 binary countings
The synchronous up/down counter of device, watchdog circuit and the decimal system connects, and the synchronous up/down counter of the decimal system and watchdog circuit connect
It connects, the synchronous up/down counter of the decimal system is also used to connect with switch block, and watchdog circuit is also used to connect with single-chip microcontroller.
Further, watchdog circuit includes timing RC circuit, monostable/astable multivibrator, resistance R2, capacitor
C2, the first NAND gate and reset signal postpone RC circuit, and timing RC circuit includes resistance R1 and capacitor C1；
The first end of resistance R1 is connect with the first end of capacitor C1, the second end and monostable/unstable state multi resonant of resistance R1
No. 2 pins of oscillator connect, and the second end of capacitor C1 is connect with No. 1 pin of monostable/astable multivibrator, monostable
No. 3 pins of state/astable multivibrator are connect with the first end of the first end of resistance R1 and capacitor C1, monostable/non-steady
No. 6 pins of state multivibrator are grounded, the output of monostable/astable multivibrator No. 8 pins and the first NAND gate
End connection, the output end connection of the first NAND gate of first end of capacitor C2, the second end and monostable/unstable state multi resonant of capacitor C2
No. 12 pins of oscillator connect, and the first end of resistance R2 is connect with No. 12 pins of monostable/astable multivibrator, electricity
The second end ground connection of R2 is hindered, the input terminal and reset signal of the first NAND gate postpone RC circuit connection, and reset signal postpones RC electricity
Road is also connect with No. 10 pins of monostable/astable multivibrator and memory respectively, monostable/unstable state multi-harmonic-oscillations
No. 10 pins of device are also connect with single-chip microcontroller, monostable/astable multivibrator reset pin and electrification reset RC circuit
Connection.
Further, electrification reset RC circuit includes resistance R6 and capacitor C7, and the first end of capacitor C7 connects to power supply, electricity
The second end for holding C7 is connect with the first end of resistance R6, and the second end of resistance R6 is grounded, the second end of capacitor C7 also respectively with list
The clearing pin of stable state/astable multivibrator reset pin up/down counter synchronous with the decimal system connects.
Further, reset signal delay RC circuit includes resistance R3, resistance R4, capacitor C3 and capacitor C4,
The first end of resistance R3 and the first end of capacitor C3 are connect with No. 1 input terminal of the first NAND gate, resistance R3's
Second end is connect with No. 10 pins of monostable/astable multivibrator, the first end of resistance R4 and the second end of capacitor C4
It is connect with No. 2 input terminals of the first NAND gate, the second end of capacitor C3 and the first end ground connection of capacitor C4, the second end of resistance R4
It is connect with memory.
Further, hardware watchdog circuit further includes resistance R5, capacitor C5, capacitor C6, resistance R7 and capacitor C8,
No. 1 pin of 7 binary counters is connect with the first end of resistance R5, the second end of resistance R5 and memory
No. 10 pin connections, the first end of capacitor C5 are connect with No. 2 pins of 7 binary counters, the second end ground connection of capacitor C5,
The first end of capacitor C6 is grounded, and the second end of capacitor C6 is connect with the first end of resistance R5, No. 5 pins, No. 4 pins of memory
It is connect respectively with multiway analog switch with No. 3 pins, the up/down counter connection synchronous with the decimal system of No. 2 pins of memory is deposited
No. 9 pins of reservoir and reset signal postpone RC circuit connection, and No. 2 of No. 12 pins of memory and 7 binary counters
Pin connection, No. 11 pins of memory are connect with the first end of resistance R7, the second end of resistance R7 plus/minus synchronous with the decimal system
Subtracting for counter counts pin connection, and the first end of capacitor C8 is connect with the second end of resistance R7, the second end ground connection of capacitor C8.
Further, hardware watchdog circuit further includes jumper wire device and the second NAND gate, jumper wire device respectively with second with it is non-
Door up/down counter synchronous with the decimal system connects；
Jumper wire device and the second NAND gate are used to be arranged the counting threshold of the synchronous up/down counter output fault-signal of the decimal system
Value.
Further, No. 3 pins connection of No. 1 pin up/down counter synchronous with the decimal system of jumper wire device, jumper wire device
No. 6 pins of No. 4 pins up/down counter synchronous with the decimal system connect, No. 5 pins plus/minus synchronous with the decimal system of jumper wire device
No. 2 pins of counter connect, No. 15 pins, No. 1 pin, No. 10 pins and No. 9 pins of the synchronous up/down counter of the decimal system
Power supply is connect, No. 7 pins of the synchronous up/down counter of the decimal system and No. 2 pins of memory connect, No. 2 pins of jumper wire device
It is connect with No. 6 pins with the first input end of the second NAND gate, No. 3 pins of jumper wire device and the second input terminal of the second NAND gate
Connection, No. 11 pins connection of the output end of the second NAND gate up/down counter synchronous with the decimal system.
Further, with task timing monitoring hardware watchdog circuit when executing watchdog reset function, monostable/
Astable multivibrator is set as Retargetable compiler monostable oscillator, and output pulse width tw is set by timing RC circuit
It is fixed.
Further, decimal system up/down counter has counter self-correction logic function.
The present invention also provides a kind of single-chip computer control system, including multiway analog switch, single-chip microcontroller, switch block and as above
The hardware watchdog circuit with the monitoring of task timing；
Hardware watchdog circuit with the monitoring of task timing is connect with multiway analog switch, single-chip microcontroller, switch block respectively.
The invention has the following advantages:
The hardware watchdog circuit with the monitoring of task timing of the invention, compared with traditional BIT detection, by 7 two into
Counter and memory processed are integrated with watchdog circuit, will be to the monitoring of the timing of multiway analog switch gating signal and firmly
Part watchdog circuit has carried out comprehensive design, not only solves the real-time detection problem to timesharing Mission Monitor, and reduce
Software complexity reduces the complexity of circuit, improves the reliability and safety of system, can avoid not pressing because of gating signal
Timing strobe and caused by signal misread, influence the realization of control function or cause to malfunction, it is embedding to timing monitoring etc. need to be carried out
Enter formula application and provides solution.
Single-chip computer control system of the invention equally has the above advantages.
Other than objects, features and advantages described above, there are also other objects, features and advantages by the present invention.
Below with reference to figure, the present invention is described in further detail.
Detailed description of the invention
The attached drawing constituted part of this application is used to provide further understanding of the present invention, schematic reality of the invention
It applies example and its explanation is used to explain the present invention, do not constitute improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is that the hardware watchdog circuit with the monitoring of task timing of the preferred embodiment of the present invention is opened with multi-channel analog respectively
It closes, the modular structure schematic diagram that single-chip microcontroller is connected with switch block.
Fig. 2 is the circuit diagram of the hardware watchdog circuit with the monitoring of task timing of the preferred embodiment of the present invention.
Fig. 3 is that the positive logic of reviewing one's lessons by oneself of the synchronous up/down counter of the decimal system in Fig. 2 of the preferred embodiment of the present invention is illustrated
Figure.
Marginal data:
11, watchdog circuit；12,7 binary counters；13, memory；15, electrification reset RC circuit；16, ten into
Make synchronous up/down counter；17, the second NAND gate；18, jumper wire device；111, timing RC circuit；112, the first NAND gate；113,
Reset signal postpones RC circuit；114, monostable/astable multivibrator；20, multiway analog switch；30, single-chip microcontroller；40,
Switch block.
Specific embodiment
The embodiment of the present invention is described in detail below in conjunction with attached drawing, but the present invention can be limited by following and
The multitude of different ways of covering is implemented.
As shown in Figure 1, the preferred embodiment of the present invention provides a kind of hardware watchdog circuit with the monitoring of task timing,
It is monitored for the gating signal to multiway analog switch 20, caused by not gated chronologically because of multiway analog switch 20
Signal misread, and then influence single-chip microcontroller control function realize or cause to malfunction.It is described with task timing monitoring it is hard
Part watchdog circuit includes 15,7 watchdog circuit 11, memory 13, electrification reset RC circuit binary counters 12 and ten
System synchronizes up/down counter 16, and the electrification reset RC circuit 15 is for connecting to power supply, the electrification reset RC circuit 15
Also up/down counter 16 synchronous with watchdog circuit 11 and the decimal system connects respectively, and memory 13 is used for and multiway analog switch
20 connection be monitored with the three tunnel gating signals to multiway analog switch 20, memory 13 respectively with 7 binary counters
12, the up/down counter 16 synchronous with the decimal system of watchdog circuit 11 connects, the synchronous up/down counter 16 of the decimal system and house dog
Circuit 11 connects, and for connecting with switch block 40, watchdog circuit 11 is also used to and list the synchronous up/down counter 16 of the decimal system
Piece machine 30 connects.The memory 13 be used for store three tunnel gating signals timing nested operation logic and output hello dog instruct to
Watchdog circuit 11,7 binary counters 12 for being counted to the nested timing of three tunnel gating signals, it is described on
Reset RC circuit 15 is used to make in system electrification the low level of the reset terminal holding certain time of watchdog circuit 11, thus
11 output reset signal of watchdog circuit is set to be transmitted to single-chip microcontroller 30, and for resetting the synchronous up/down counter 16 of the decimal system,
The watchdog circuit 11 is resetted for control single chip computer 30, and the synchronous up/down counter 16 of the decimal system is used for reset arteries and veins
The capable counting that adds deduct is rushed in, when counting down to preset value, realizes to count and latch.It is appreciated that the multiway analog switch 20 is 8 choosings
1 analog switch, it is of the invention with task timing monitoring hardware watchdog circuit to 8 select 3 tunnel gating signals of 1 analog switch into
Row monitoring, the switch block 40 are used to control the signal output on-off of whole single-chip computer control system.The memory 13 is
EEPROM (read and write by Electrically Erasable Programmable read only memory band electric erazable programmable
Memory).
As shown in Fig. 2, the watchdog circuit 11 includes timing RC circuit 111, monostable/astable multivibrator
114, resistance R2, capacitor C2, the first NAND gate 112 and reset signal postpone RC circuit 113, and the timing RC circuit 111 is used for
The pulse width that monostable/astable multivibrator 114 exports is set, the reset signal delay RC circuit 113 is used for will
The low level reset signal that monostable/astable multivibrator 114 exports is transmitted to the after postponing at least one machine cycle
One NAND gate 112, the first NAND gate 112 are used for the low level reset signal for exporting monostable/astable multivibrator 114
It is changed into high level signal and feeds back to monostable/astable multivibrator 114.Specifically, the timing RC circuit 111 wraps
Resistance R1 and capacitor C1 are included, it includes resistance R3, resistance R4, capacitor C3 and capacitor C4, the electricity that reset signal, which postpones RC circuit 113,
The first end of resistance R1 is connect with the first end of capacitor C1, second end and the monostable/astable multivibrator 114 of resistance R1
No. 2 pin connections, the second end of capacitor C1 are connect with No. 1 pin of monostable/astable multivibrator 114, monostable/non-
No. 3 pins of steady state multivibrator 114 are connect with the first end of the first end of resistance R1 and capacitor C1.Monostable/unstable state
No. 6 pins of multivibrator 114 are grounded, and No. 8 pins are connect with the output end of the first NAND gate 112, i.e., connect with its No. 3 pins
It connects.The output end of the first NAND gate of first end 112 of capacitor C2 connects, the second end and monostable/unstable state multi resonant of capacitor C2
No. 12 pins of oscillator 114 connect.The first end of resistance R2 and No. 12 pins of monostable/astable multivibrator 114
Connection, the second end ground connection of resistance R2.No. 1 input terminal of the first NAND gate 112, i.e. No. 1 pin, with the first end of resistance R3 and
The first end of capacitor C3 connects, and the second end of resistance R3 is connect with No. 10 pins of monostable/astable multivibrator 114.
No. 2 input terminals of the first NAND gate 112, i.e. No. 2 pins, connect, capacitor with the second end of the first end of resistance R4 and capacitor C4
The second end of C3 and the first end ground connection of capacitor C4, the second end of resistance R4 are connect with memory 13.Monostable/unstable state multi resonant
No. 10 pins of oscillator 114 are also connect with single-chip microcontroller 30, the reset pin of monostable/astable multivibrator 114, i.e. MR
Pin is connect with electrification reset RC circuit 15.The resistance value of the resistance R1 is 3.16K Ω, and the capacity of capacitor C1 is 0.033 μ F, electricity
The capacity for holding C2 is 1500pF, and the resistance value of resistance R4 is 10K Ω, and the resistance value of resistance R3 is 5.11K Ω, and the resistance value of resistance R4 is 1K
The capacity of Ω, capacitor C3 are 1500pF, and the capacity of capacitor C4 is 220pF.It is appreciated that the timing RC circuit 111 can save
Slightly.
It is described with task timing monitoring hardware watchdog circuit further include resistance R5, capacitor C5, capacitor C6, resistance R7 and
Capacitor C8, No. 1 pin of 7 binary counters 12 are connect with the first end of resistance R5, the second end of resistance R5 with deposit
No. 10 pins of reservoir 13 connect, and the first end of capacitor C5 is connect with No. 2 pins of 7 binary counters 12, capacitor C5's
Second end ground connection, the first end ground connection of capacitor C6, the second end of capacitor C6 are connect with the first end of resistance R5.The 5 of memory 13
Number pin, No. 4 pins and No. 3 pins are connect with multiway analog switch 20 respectively, are respectively supervised respectively to gating signal all the way
It surveys, No. 6 pins of memory 13 connect with No. 9 pins of 7 binary counters 12, No. 7 pins of memory 13 and 7 two
No. 4 pins of system Counter 12 connect, and No. 1 pin of memory 13 is connect with No. 12 pins of 7 binary counters 12,
No. 15 pins of memory 13 are connect with No. 11 pins of 7 binary counters 12, No. 13 pins of memory 13 and No. 14
Pin is grounded, and synchronous with the decimal system up/down counter 16 of No. 2 pins of memory 13 connects, No. 9 pins of memory 13 with
The second end of resistance R4 connects, and No. 12 pins of memory 13 are connect with No. 2 pins of 7 binary counters 12, memory
13 No. 11 pins are connect with the first end of resistance R7, and No. 4 of the second end of resistance R7 up/down counter 16 synchronous with the decimal system
Pin connection subtracts counting pin with it and connect, the first end of capacitor C8 is connect with the second end of resistance R7, and the second of capacitor C8
End ground connection.The resistance value of the resistance R5 and resistance R7 is 1K Ω, and the capacity of capacitor C5 is 6800pF, and the capacity of capacitor C6 is 0.1 μ
The capacity of F, capacitor C8 are 220pF.
The electrification reset RC circuit 15 includes resistance R6 and capacitor C7, and the first end of capacitor C7 connects to power supply, capacitor
The second end of C7 is connect with the first end of resistance R6, the second end of resistance R6 ground connection, the second end of capacitor C7 also respectively with it is monostable
No. 14 pins of the reset pin of state/astable multivibrator 114 up/down counter 16 synchronous with the decimal system connect.It is described
The resistance value of resistance R6 is 5.11K Ω, and the capacity of capacitor C7 is 10 μ F.
No. 14 pins of the synchronous up/down counter 16 of the decimal system, i.e. clearing pin are connect with the second end of capacitor C7,
No. 11 pins of the synchronous up/down counter 16 of the decimal system are connect with switch block 40.Preferably, the band task timing prison
The hardware watchdog circuit of control further includes jumper wire device 18 and the second NAND gate 17, the jumper wire device 18 respectively with the second NAND gate 17
Up/down counter 16 synchronous with the decimal system connects.Specifically, No. 1 pin plus/minus meter synchronous with the decimal system of the jumper wire device 18
No. 3 pins connection of number device 16, No. 6 pins connection of No. 4 pins up/down counter 16 synchronous with the decimal system of jumper wire device 18,
No. 2 pins of No. 5 pins up/down counter 16 synchronous with the decimal system of jumper wire device 18 connect, the synchronous up/down counter of the decimal system
16 No. 15 pins, No. 1 pin, No. 10 pins and No. 9 pins connect power supply, and No. 7 of the synchronous up/down counter 16 of the decimal system are drawn
Foot is connect with No. 2 pins of memory 13.No. 2 pins and No. 6 pins of jumper wire device 18 and the first input of the second NAND gate 17
End connection, i.e., connect with its No. 4 pins, No. 3 pins of jumper wire device 18 are connect with the second input terminal of the second NAND gate 17, i.e., with
Its No. 5 pin connections, the output end of the second NAND gate 17, i.e. No. 6 pins, No. 11 of up/down counter 16 synchronous with the decimal system
Pin connection.The jumper wire device 18 and the second NAND gate 17 export failure for the synchronous up/down counter 16 of the decimal system to be arranged and believe
Number count threshold.
Hardware watchdog circuit with the monitoring of task timing of the invention is when executing power-on reset function, electrification reset RC
Circuit makes the reset terminal of monostable/astable multivibrator 114, i.e. MR pin, keeps the low level of certain time, to make
114 output reset signal of monostable/astable multivibrator is simultaneously transmitted to single-chip microcontroller 30, so that control single chip computer 30 is realized
Reply bit function by cable.Meanwhile electrification reset RC circuit can output signal be transmitted to No. 14 of the synchronous up/down counter 16 of the decimal system and draw
Foot, i.e. clear terminal make the clear terminal of the synchronous up/down counter 16 of the decimal system keep the low level of certain time, thus make ten into
It makes synchronous up/down counter 16 and counts clearing.
Hardware watchdog circuit with the monitoring of task timing of the invention is described monostable when executing watchdog reset function
State/astable multivibrator 114 is set as Retargetable compiler monostable oscillator, and output pulse width tw passes through timing RC electricity
Road 111 determines, when single-chip microcontroller 30 works normally, feeds dog instruction being less than in the tw time if received, monostable/non-steady
State multivibrator 114 can maintain high level in continuous weight trigger process, reset pin.7 binary system meters
Number device 12 and memory 13 and peripheral component realize the detection of the output and reset pulse of feeding dog instruction, in software, each
Cycle period timesharing task timing is from 0 to 8, i.e., the output of corresponding 3 tunnel gating signals is from 0 to 8, the logic in memory 13
Triggering nested operation is carried out to the timing in each period with 7 realizations of binary counter 12, only when task timing sequentially carries out
When, memory 13 just exports a feeding-dog signal to watchdog circuit 11, and monostable/astable multivibrator 114 is triggered,
Output pin high level is kept, output pin is No. 10 pins.If task timing does not carry out sequentially, the nesting in memory 13
Operation cannot issue feeding-dog signal to watchdog circuit 11, wherein the output pin meeting of monostable/astable multivibrator 114
Become low level, so that control single chip computer 30 is resetted.Meanwhile the low level reset signal can also postpone RC by reset signal
Circuit 113 through the first NAND gate 112 becomes high level signal after postponing about 5 machine cycles, and to be then transmit to monostable/non-steady
State multivibrator 114 makes the output pin of monostable/astable multivibrator 114 restore high electricity to trigger to it
It is flat.Hardware watchdog circuit with the monitoring of task timing of the invention postpones RC circuit 113 and first by setting reset signal
The fast quick-recovery function of system may be implemented in NAND gate 112, it is ensured that system fast quick-recovery of energy after exceptional reset solves now main
Single-chip microcontroller is out of control there are the long period when unexpected reset caused by the reset chip reset signal duration of stream long (such as 200ms)
The security risk of state.
In addition, the hardware watchdog circuit of the invention with the monitoring of task timing also has fault latch and self- recoverage function
Energy.Specifically, the decimal system up/down counter 16 can count reset pulse, and electrification reset RC circuit 15 makes ten
System up/down counter is reset, and the output of simultaneous memory 13 subtracts counting controling signal and is transmitted to decimal system up/down counter 16
No. 4 pins make decimal system up/down counter 16 carry out subtracting counting to reset pulse, i.e., decimal system plus/minus counts after electrification reset
Device 16 enters stable state, output valve 9.Into after stable state, the output of memory 13 plus counting controling signal make decimal system plus/minus meter
Number device 16 is carried out plus is counted to reset pulse.As shown in figure 3, when task timing persistent errors, such as reset signal continuously goes out
6 times existing, the synchronous up/down counter 16 of the decimal system can be by fault latch, and issues system failure signal and be transmitted to switch block
40 with the output of 40 cut-off signal of control switch component, forbids controlling signal output；When task timing it is accidental mistake when, described ten into
Up/down counter 16 processed devises counter and reviews one's lessons by oneself positive logic, can be to the value counted when reset signal does not occur continuously
It carries out subtracting operation, until restoring stable state, i.e., output valve is 9.Furthermore it is also possible to be set by jumper wire device 18 and the second NAND gate 17
The count threshold that decimal system up/down counter 16 exports fault-signal is set, which refers to that reset signal persistently occurs
Number, i.e., the number that reset signal persistently occurs reaches the threshold value, then decimal system up/down counter 16 export fault-signal to
Switch block 40 carries out fault latch.
Hardware watchdog circuit with the monitoring of task timing of the invention passes through failure mould compared with traditional BIT detection
Formula and impact analysis are set synthesis has been carried out to the monitoring of the timing of multiway analog switch gating signal and hardware watchdog circuit
Meter, not only solves the real-time detection problem to timesharing Mission Monitor, and reduce software complexity, reduces answering for circuit
Miscellaneous degree improves the reliability and safety of system, can avoid signal caused by due to gating signal does not gate chronologically and misreads,
It influences the realization of control function or causes to malfunction, the hardware watchdog circuit of the invention with the monitoring of task timing, to need to be into
The Embedded Applications such as row timing monitoring provide solution.
It is appreciated that another embodiment of the present invention also provides a kind of single-chip computer control system, including multiway analog switch
20, single-chip microcontroller 30, switch block 40 and the hardware watchdog circuit as described above with the monitoring of task timing, band task timing are supervised
The hardware watchdog circuit of control is connect with multiway analog switch 20, single-chip microcontroller 30, switch block 40 respectively.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of hardware watchdog circuit with the monitoring of task timing, carries out for the gating signal to multiway analog switch (20)
Monitoring, which is characterized in that
Including watchdog circuit (11), 7 binary counters (12), memory (13), electrification reset RC circuit (15) and ten
System is synchronous up/down counter (16)；
Watchdog circuit (11) is resetted for control single chip computer (30)；
Memory (13) instructs for storing timing nested operation logic and output hello dog and gives watchdog circuit (11)；
7 binary counters (12), for being counted to timing；
Electrification reset RC circuit (15), for making the reset terminal of watchdog circuit (11) keep low level in system electrification and making
The decimal system synchronous up/down counter (16) is reset；
The decimal system synchronous up/down counter (16) be used to carry out adding deduct to reset pulse counting and carrying out counts latch and defeated
Be out of order signal；
Electrification reset RC circuit (15) for connecting to power supply, electrification reset RC circuit (15) also respectively with watchdog circuit (11)
Up/down counter (16) connection synchronous with the decimal system, memory (13) with multiway analog switch (20) for connecting, memory
(13) also up/down counter (16) synchronous with 7 binary counters (12), watchdog circuit (11) and the decimal system connects respectively
It connects, the decimal system synchronous up/down counter (16) is connect with watchdog circuit (11), and the decimal system synchronous up/down counter (16) is also
For connecting with switch block (40), watchdog circuit (11) is also used to connect with single-chip microcontroller (30).
2. hardware watchdog circuit as described in claim 1, which is characterized in that
Watchdog circuit (11) includes timing RC circuit (111), monostable/astable multivibrator (114), resistance R2, electricity
Hold C2, the first NAND gate (112) and reset signal delay RC circuit (113), timing RC circuit (111) includes resistance R1 and capacitor
C1；
The first end of resistance R1 is connect with the first end of capacitor C1, the second end and monostable/unstable state multi-harmonic-oscillations of resistance R1
No. 2 pins of device (114) connect, and the second end of capacitor C1 and No. 1 pin of monostable/astable multivibrator (114) connect
It connecing, No. 3 pins of monostable/astable multivibrator (114) are connect with the first end of the first end of resistance R1 and capacitor C1,
No. 6 pins of monostable/astable multivibrator (114) are grounded, and No. 8 of monostable/astable multivibrator (114) are drawn
Foot is connect with the output end of the first NAND gate (112), the output end connection of the first NAND gate of first end (112) of capacitor C2, electricity
Hold C2 second end connect with No. 12 pins of monostable/astable multivibrator (114), the first end of resistance R2 with it is monostable
No. 12 pins of state/astable multivibrator (114) connect, the second end ground connection of resistance R2, the first NAND gate (112) it is defeated
Enter end and reset signal delay RC circuit (113) connect, reset signal postpone RC circuit (113) also respectively with monostable/non-surely
No. 10 pins and memory (13) of state multivibrator (114) connect, and the 10 of monostable/astable multivibrator (114)
Number pin is also connect with single-chip microcontroller (30), reset pin and electrification reset the RC electricity of monostable/astable multivibrator (114)
Road (15) connection.
3. hardware watchdog circuit as claimed in claim 2, which is characterized in that
Electrification reset RC circuit (15) includes resistance R6 and capacitor C7, and the first end of capacitor C7 connects to power supply, and the of capacitor C7
Two ends are connect with the first end of resistance R6, the second end of resistance R6 ground connection, the second end of capacitor C7 also respectively with monostable/non-steady
The reset pin of state multivibrator (114) is connected with the clearing pin of the decimal system synchronous up/down counter (16).
4. hardware watchdog circuit as claimed in claim 2, which is characterized in that
Reset signal delay RC circuit (113) includes resistance R3, resistance R4, capacitor C3 and capacitor C4,
The first end of resistance R3 and the first end of capacitor C3 are connect with No. 1 input terminal of the first NAND gate (112), resistance R3's
Second end is connect with No. 10 pins of monostable/astable multivibrator (114), and the of the first end of resistance R4 and capacitor C4
Two ends are connect with No. 2 input terminals of the first NAND gate (112), the second end of capacitor C3 and the first end ground connection of capacitor C4, resistance
The second end of R4 is connect with memory (13).
5. hardware watchdog circuit as claimed in claim 2, which is characterized in that
Hardware watchdog circuit further includes resistance R5, capacitor C5, capacitor C6, resistance R7 and capacitor C8,
No. 1 pin of 7 binary counters (12) is connect with the first end of resistance R5, the second end and memory of resistance R5
(13) No. 10 pins connection, the first end of capacitor C5 are connect with No. 2 pins of 7 binary counters (12), capacitor C5's
Second end ground connection, the first end ground connection of capacitor C6, the second end of capacitor C6 are connect with the first end of resistance R5, memory (13)
No. 5 pins, No. 4 pins and No. 3 pins are connect with multiway analog switch (20) respectively, No. 2 pins of memory (13) and ten into
Synchronous up/down counter (16) connection is made, No. 9 pins of memory (13) connect with reset signal delay RC circuit (113), deposit
No. 12 pins of reservoir (13) are connect with No. 2 pins of 7 binary counters (12), No. 11 pins and electricity of memory (13)
The first end connection of R7 is hindered, subtracting for the second end of resistance R7 up/down counter (16) synchronous with the decimal system counts pin connection, electricity
The first end for holding C8 is connect with the second end of resistance R7, the second end ground connection of capacitor C8.
6. hardware watchdog circuit as described in claim 1, which is characterized in that
Hardware watchdog circuit further includes jumper wire device (18) and the second NAND gate (17), jumper wire device (18) respectively with the second NAND gate
(17) up/down counter (16) connection synchronous with the decimal system；
Jumper wire device (18) and the second NAND gate (17) are used to be arranged the synchronous up/down counter (16) of the decimal system and export fault-signal
Count threshold.
7. hardware watchdog circuit as claimed in claim 6, which is characterized in that
No. 3 pins of No. 1 pin of jumper wire device (18) up/down counter (16) synchronous with the decimal system connect, and the 4 of jumper wire device (18)
No. 6 pins connection of number pin up/down counter (16) synchronous with the decimal system, No. 5 pins and the decimal system of jumper wire device (18) are same
Walk No. 2 pins connection of up/down counter (16), No. 15 pins of the decimal system synchronous up/down counter (16), No. 1 pin, 10
Number pin and No. 9 pins connect power supply, and No. 7 pins of the decimal system synchronous up/down counter (16) draw with No. 2 of memory (13)
Foot connection, No. 2 pins and No. 6 pins of jumper wire device (18) are connect with the first input end of the second NAND gate (17), jumper wire device
(18) No. 3 pins are connect with the second input terminal of the second NAND gate (17), the output end and the decimal system of the second NAND gate (17)
No. 11 pins connection of synchronous up/down counter (16).
8. hardware watchdog circuit as claimed in claim 2, which is characterized in that
Hardware watchdog circuit with the monitoring of task timing is when executing watchdog reset function, monostable/unstable state multi-resonant
It swings device (114) and is set as Retargetable compiler monostable oscillator, output pulse width tw is set by timing RC circuit (111).
9. hardware watchdog circuit as described in claim 1, which is characterized in that
Decimal system up/down counter (16) has counter self-correction logic function.
10. a kind of single-chip computer control system, which is characterized in that including multiway analog switch (20), single-chip microcontroller (30), switch block
(40) and it is as described in any one of claims 1 to 9 with task timing monitoring hardware watchdog circuit；
With task timing monitoring hardware watchdog circuit respectively with multiway analog switch (20), single-chip microcontroller (30), switch block
(40) it connects.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811514894.0A CN109614261B (en) | 2018-12-12 | 2018-12-12 | Hardware watchdog circuit with task time sequence monitoring function and single chip microcomputer control system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811514894.0A CN109614261B (en) | 2018-12-12 | 2018-12-12 | Hardware watchdog circuit with task time sequence monitoring function and single chip microcomputer control system |
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| CN109614261B CN109614261B (en) | 2022-04-05 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113590374A (en) * | 2021-09-28 | 2021-11-02 | 广州果冻智能科技有限公司 | Watchdog monitoring system and monitoring method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104636215A (en) * | 2015-03-13 | 2015-05-20 | 北京经纬恒润科技有限公司 | Hardware watchdog and application circuit thereof |
| CN112506694A (en) * | 2020-12-24 | 2021-03-16 | 杭州塔石物联网科技有限公司 | Watchdog circuit capable of configuring reset time and timing time |
| CN214202355U (en) * | 2020-12-24 | 2021-09-14 | 杭州塔石物联网科技有限公司 | Watchdog circuit capable of configuring reset time and timing time |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104636215A (en) * | 2015-03-13 | 2015-05-20 | 北京经纬恒润科技有限公司 | Hardware watchdog and application circuit thereof |
| CN112506694A (en) * | 2020-12-24 | 2021-03-16 | 杭州塔石物联网科技有限公司 | Watchdog circuit capable of configuring reset time and timing time |
| CN214202355U (en) * | 2020-12-24 | 2021-09-14 | 杭州塔石物联网科技有限公司 | Watchdog circuit capable of configuring reset time and timing time |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113590374A (en) * | 2021-09-28 | 2021-11-02 | 广州果冻智能科技有限公司 | Watchdog monitoring system and monitoring method thereof |
| CN113590374B (en) * | 2021-09-28 | 2021-11-30 | 广州果冻智能科技有限公司 | Watchdog monitoring system and monitoring method thereof |
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