CN109614124A - Signal processing framework transplantation method based on ZYNQ platform - Google Patents
Signal processing framework transplantation method based on ZYNQ platform Download PDFInfo
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Abstract
The present invention relates to a kind of, and the signal processing framework transplantation method based on ZYNQ platform includes for the original signal processing framework of 2DSP+FPGA: the interactive interfacing between two S1, summary DSP summarizes two DSP interactive interfacing between FPGA respectively；S2, the code of two DSP is transplanted to respectively in the double-core at the end PS of ZYNQ platform, by the end PL of the code migrating of FPGA to ZYNQ platform；S3, using the shared memory between the end the PS double-core of ZYNQ platform, complete the interactive interfacing between two DSP；S4, using the GP bus between the end PS and the end PL of ZYNQ platform, complete two DSP interactive interfacing between FPGA respectively；S5, using ZYNQ platform the end PL directmemoryaccess device and fourier transformation module IP kernel, complete to the hardware-accelerated of fourier transformation module.The present invention realizes the equivalent substitution of signal processing framework, solves the problems, such as platform transplantation；Universality is high, is suitble to Project Realization.
Description
Technical field
The present invention relates to a kind of based on ZYNQ platform (first expansible processing platform of industry that Xilinx company releases)
Signal processing framework transplantation method, in particular to a kind of by DSP+FPGA (Digital Signal Processing+field programmable gate array)
ZYNQ platform from signal processing framework to low-power consumption transplantation method, belong to signal processing technology field.
Background technique
7000 family chip of ZYNQ is that Xilinx (match Sentos) company is based on Artix-7 (Z-7010, Z-7015, Z-
7020) a kind of, entirely programmable SoC core that the FPGA of Kintex-7 (Z-7030, Z-7035, Z-7045, Z-7100) series is released
Piece (system level chip) embeds double-core ARM Cortex-A9MPcore hard nucleus management device, supports highest dominant frequency 1GHz.In FPGA
Middle Embeded CPU (central processing unit) is current solution software and hardware programmable main path entirely, another FPGA leading provider
Altera is also embedded in ARM series CPU in the FPGA of newest release.Software and hardware may be programmed entirely and represent current programmable logic
The developing direction of device.
ZYNQ chip is a piece of FPGA first, has been internally embedded the stone of ARM in FPGA, and interconnect inside by high speed
Bus combines efficient developing instrument, so that ARM core and FPGA resource seamless link, make the signal having a style of one's own
Processing system.So the use of ZYNQ chip, is equivalent to the signal processing framework that original DSP+FPGA is substituted, has simplified one
Piece dsp chip, also simplifies periphery circuit design accordingly, reduces the need to device user pin, high speed interconnecting interface etc.
It asks, while power consumption is also effectively reduced.
Currently, what the framework of majority signal processing platform was all made of is DSP+FPGA mode.Due to originals such as import DSP halt productions
Cause, original signal processing framework face the transplanting work of signal processing platform.Based on this, find out a kind of by original DSP+
ZYNQ platform transplantation from the signal processing framework of FPGA to low-power consumption method, be current urgent need to resolve and have higher-value
Technical problem.
Number of patent application 201610270543.4 " is handled the embedded code of MicroBlaze platform to Cortex-A9
Device transplanting method " in, disclose by analyze MicroBlaze platform processor and Cortex-A9 processor architecture not
Same place realizes the transplantation method of embedded code.Number of patent application 201710085729.7 is " a kind of based on ZYNQ framework
GNSS receiver board " in, the problem that power consumption for existing GNSS board is big, volume is big, at high cost is disclosed, proposes to utilize
ZYNQ framework realizes GNSS board function.A kind of " the remote update system based on ZYNQ of number of patent application 201711328653.2
And its implementation " a kind of base provided for interface and memory space requirements needed for the multiple FPGA of remote upgrade is provided
In the remote update system and its implementation of ZYNQ.But in above patent document, without reference to DSP+FPGA signal at
Manage the Transplanting Problem of framework.
" programmable SoC is based on wirelessly and in mobile communication science conference collection of thesis in the whole nation that in September, 2013 is held
The design and realization of Zynq-7000 intelligent encryption communication system ", describe the intelligence based on newest programmable SoC Zynq-7000
The design method and software and hardware of energy cryptographic communication system realize process, propose the Hybrid Encryption strategy of more Encryption Algorithm, but the party
Method is not directed to new legacy platform replacement and proposes feasible scheme.The national signal of the 7th held in October, 2013 and intelligent information
Processing and " FPGA realizes intelligent embedded system " in application academic conference proceedings, describe ZYNQ-7000 Series FPGA
The various performances of chip, realize more intelligent embedded system, but ask in text without reference to the correlation of new legacy platform replacement
Topic.
In conclusion the present invention proposes a kind of transplantation method of DSP+FPGA signal processing framework based on ZYNQ platform,
To solve problems of the prior art and limitation.
Summary of the invention
The object of the present invention is to provide a kind of signal processing framework transplantation method based on ZYNQ platform realizes signal processing
The equivalent substitution of framework, solves the problems, such as platform transplantation；Universality is high, is suitble to Project Realization.
To achieve the above object, the present invention provides a kind of signal processing framework transplantation method based on ZYNQ platform, for
The original signal processing framework of 2DSP+FPGA comprising the steps of:
Interactive interfacing between two S1, summary DSP, summarizes two DSP interactive interfacing between FPGA respectively；
S2, the code of two DSP is transplanted to respectively in the double-core at the end PS of ZYNQ platform, the code migrating of FPGA is arrived
The end PL of ZYNQ platform；
S3, using the shared memory between the end the PS double-core of ZYNQ platform, complete the interactive interfacing between two DSP；
S4, using the GP bus between the end PS and the end PL of ZYNQ platform, complete two DSP interface between FPGA respectively
Interaction；
S5, using ZYNQ platform the end PL directmemoryaccess device and fourier transformation module IP kernel, complete pair
Fourier transformation module it is hardware-accelerated.
In the S1, the interactive interfacing between two DSP includes data interaction and control signal interaction；Two DSP points
Interactive interfacing not between FPGA include data interaction, control signal interaction interacted with interrupt signal.
In the S2, the step of by the code migrating of two original DSP to the end PS of ZYNQ platform in, further includes: according to
ARM in the end PS verifies the turnover of materials stored function, modifies the part of library function involved in corresponding DSP code.
In the S3, comprising the following steps:
It is arranged in S31, shared memory OCM:
First mark bit register, indicates the enabler flags position for the first core that second core at the end PS is read；
First address field, first core at the storage end PS write the address field of the data of the second core；
Second mark bit register, indicates the enabler flags position for the second core that first core at the end PS is read；
Second address field, second core at the storage end PS write the address field of the data of the first core；
S32, the first core read the value of the first mark bit register, when the value read is the first value of statistical indicant, first
Core writes data into the first address field, and the value of the first mark bit register is set to the second value of statistical indicant；
S33, the second core read the value of the first mark bit register, when the value read is the second value of statistical indicant, second
Core reads the data in the first address field, and the value of the first mark bit register is set to the first value of statistical indicant；
S34, the second core read the value of the second mark bit register, when the value read is the first value of statistical indicant, second
Core writes data into the second address field, and the value of the second mark bit register is set to the second value of statistical indicant；
S35, the first core read the value of the second mark bit register, when the value read is the second value of statistical indicant, first
Core reads the data in the second address field, and the value of the second mark bit register is set to the first value of statistical indicant.
In the S4, comprising the following steps:
S41, PL are arranged in end: the first random access memory, and the data and interactive information at the end PL are write in the storage end PS；Second with
The data and interactive information at the end PS are write in machine memory, the storage end PL；
S42, the first random access memory and the second random access memory are connected in GP bus；
The end S43, PS writes data into the first random access memory by GP bus, and notifies the end PL to read number by GPIO
According to；The end PL updates the data of the second random access memory, and notifies the end PS to read data by GPIO.
In the S5, comprising the following steps:
The end S51, PS configures directmemoryaccess device by GP bus, and starts the IP of directmemoryaccess device
Core；
The input data of fourier transformation module is transferred to Fourier by HP bus and become by S52, directmemoryaccess device
The IP kernel of block is changed the mold, and the output data of fourier transformation module is transferred to by the end PS by HP bus.
In conclusion the signal processing framework transplantation method provided by the present invention based on ZYNQ platform, by by former DSP
The PS that is transplanted to ZYNQ platform corresponding with the code of FPGA and the end PL, realize the equivalent substitution of signal processing framework, solve
Determined platform transplantation the problem of.This method universality is higher, is suitble to Project Realization.
Detailed description of the invention
Fig. 1 is the flow chart of the signal processing framework transplantation method based on ZYNQ platform in the present invention；
Fig. 2 is the specific form and function module map of the ZYNQ platform of the specific embodiment in the present invention.
Specific embodiment
Below in conjunction with FIG. 1 to FIG. 2, by preferred embodiment to technology contents of the invention, construction feature, reached purpose
And effect is described in detail.According to following the description, advantages and features of the invention will be become apparent from.And it should be noted that
Attached drawing is all made of very simplified form and using non-accurate ratio, only to convenient, lucidly aid illustration is of the invention
The purpose of embodiment.
As shown in Figure 1, being the signal processing framework transplantation method provided by the present invention based on ZYNQ platform；Such as Fig. 2 institute
Show, by taking ZYNQ 7045 as an example, the method for transplanting the signal processing framework of 2DSP+FPGA to ZYNQ 7045 is discussed in detail, wraps
Containing following steps:
S1, under the original signal processing framework of 2DSP+FPGA, summarize the interactive interfacing between two DSP, and summarize two
A DSP interactive interfacing between FPGA respectively；
S2, the code of two DSP is transplanted to respectively in the double-core at the end PS (processing system) of ZYNQ platform, by FPGA's
The PL (programmable logic) of code migrating to ZYNQ platform is held；
S3, using the shared memory OCM between the end the PS double-core of ZYNQ platform, complete the interactive interfacing between two DSP；
S4, using GP (universal port) bus between the end PS and the end PL of ZYNQ platform, complete two DSP respectively with FPGA
Between interactive interfacing；
S5, using ZYNQ platform the end PL directmemoryaccess device AXI-DMA and fourier transformation module FFT IP
Core is completed to the hardware-accelerated of fourier transformation module FFT.
As shown in Fig. 2, being counted between two ARM cores at the end PS by shared memory OCM for ZYNQ 7045
According to interaction, data interaction is carried out by GP bus and the random access memory ram being arranged on the end PL between the end PS and the end PL.
In the S1, the interactive interfacing between two DSP includes data interaction and control signal interaction；Two DSP points
Interactive interfacing not between FPGA include data interaction, control signal interaction interacted with interrupt signal.
In the S2, the step of by the code migrating of two original DSP to the end PS of ZYNQ platform in, further includes: according to
ARM in the end PS verifies the turnover of materials stored function, modifies the part of library function involved in corresponding DSP code, including math function.
In the S3, comprising the following steps:
4 address fields are set in S31, shared memory OCM, are respectively as follows:
First mark bit register A_Flag indicates that the first core ARM0's that the second core ARM1 at the end PS is read is enabled
Flag bit；
First address field A, the first core ARM0 at the storage end PS write the address field of the data of the second core ARM1；
Second mark bit register B_Flag indicates that the second core ARM1's that the first core ARM0 at the end PS is read is enabled
Flag bit；
Second address field B, the second core ARM1 at the storage end PS write the address field of the data of the first core ARM0；
S32, the first core ARM0 read the value of the first mark bit register A_Flag, when the value of the A_Flag read is
When 0x12341234 (this is a preset value of statistical indicant), the first core ARM0 is write data into the first address field A, and
The value of first mark bit register A_Flag is set to 0x43214321 (this is also a preset value of statistical indicant)；
S33, the second core ARM1 read the value of the first mark bit register A_Flag, when the value of the A_Flag read is
When 0x43214321, the second core ARM1 reads the data in the first address field A, and by the first mark bit register A_Flag's
Value is set to 0x12341234；
S34, the second core ARM1 read the value of the second mark bit register B_Flag, when the value of the B_Flag read is
When 0x12341234, the second core ARM1 is write data into the second address field B, and by the second mark bit register B_Flag's
Value is set to 0x43214321；
S35, the first core ARM0 read the value of the second mark bit register B_Flag, when the value of the B_Flag read is
When 0x43214321, the first core ARM0 reads the data in the second address field B, and by the second mark bit register B_Flag's
Value is set to 0x12341234.
In the S4, comprising the following steps:
Two random access memory are set in the end S41, PL, and the number at the end PL is write at the first random access memory ram _ A storage end PS
According to interactive information, the data and interactive information at the end PS are write in the second random access memory ram _ B storage end PL；
S42, the first random access memory ram _ A and the second random access memory ram _ B are connected in GP bus；
The end S43, PS writes data into the first random access memory ram _ A by GP bus, and by GPIO (universal input/
Output) the notice end PL reading data；The end PL updates the second random access memory ram _ B data, and notifies the end PS to read by GPIO
Access evidence.
As shown in Fig. 2, in the S5, comprising the following steps:
The end S51, PS configures directmemoryaccess device AXI-DMA by GP bus, and starts the IP of AXI-DMA
Core；
S52, directmemoryaccess device AXI-DMA are by HP (high-performance port) bus by fourier transformation module FFT's
Input data is transferred to the IP kernel of FFT, and the output data of fourier transformation module FFT is transferred to the end PS by HP bus.
In a preferred embodiment of the invention, the signal processing framework transplantation method quilt based on ZYNQ platform
Successful tests Mr. Yu plate platform at the signal processor letter for grinding emphasis model replaces with, and in Hardware-in-loop Simulation Experimentation and outfield
It is verified in flying test.It is consistent with the function of signal processing framework after transplanting before transplanting from test result, it is real
Effective substitution of signal processing machine platform is showed.By applying the signal processing framework transplanting side of the invention based on ZYNQ platform
Method solves the problems, such as that signal processing framework caused by chip halt production or other reasons needs replacing.
In conclusion the signal processing framework transplantation method provided by the present invention based on ZYNQ platform, by by former DSP
The PS that is transplanted to ZYNQ platform corresponding with the code of FPGA and the end PL, realize the equivalent substitution of signal processing framework, solve
Determined platform transplantation the problem of.This method universality is higher, is suitble to Project Realization.
It is discussed in detail although the contents of the present invention have passed through above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read above content, for of the invention
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (6)
1. a kind of signal processing framework transplantation method based on ZYNQ platform, which is characterized in that for the original signal of 2DSP+FPGA
Processing framework comprising the steps of:
Interactive interfacing between two S1, summary DSP, summarizes two DSP interactive interfacing between FPGA respectively；
S2, the code of two DSP is transplanted to respectively in the double-core at the end PS of ZYNQ platform, by the code migrating of FPGA to ZYNQ
The end PL of platform；
S3, using the shared memory between the end the PS double-core of ZYNQ platform, complete the interactive interfacing between two DSP；
S4, using the GP bus between the end PS and the end PL of ZYNQ platform, complete interface of two DSP respectively between FPGA and hand over
Mutually；
S5, using ZYNQ platform the end PL directmemoryaccess device and fourier transformation module IP kernel, complete in Fu
Leaf transformation module it is hardware-accelerated.
2. the signal processing framework transplantation method based on ZYNQ platform as described in claim 1, which is characterized in that the S1
In, the interactive interfacing between two DSP includes data interaction and control signal interaction；Two DSP connecing between FPGA respectively
Oral sex mutually include data interaction, control signal interaction interacted with interrupt signal.
3. the signal processing framework transplantation method based on ZYNQ platform as described in claim 1, which is characterized in that the S2
In, the step of by the code migrating of two original DSP to the end PS of ZYNQ platform in, further includes: verified the turnover of materials stored letter according to the ARM in the end PS
Number, modifies the part of library function involved in corresponding DSP code.
4. the signal processing framework transplantation method based on ZYNQ platform as claimed in claim 2, which is characterized in that the S3
In, comprising the following steps:
It is arranged in S31, shared memory OCM:
First mark bit register, indicates the enabler flags position for the first core that second core at the end PS is read；
First address field, first core at the storage end PS write the address field of the data of the second core；
Second mark bit register, indicates the enabler flags position for the second core that first core at the end PS is read；
Second address field, second core at the storage end PS write the address field of the data of the first core；
S32, the first core read the value of the first mark bit register, when the value read is the first value of statistical indicant, the first core
It writes data into the first address field, and the value of the first mark bit register is set to the second value of statistical indicant；
S33, the second core read the value of the first mark bit register, when the value read is the second value of statistical indicant, the second core
The data in the first address field are read, and the value of the first mark bit register is set to the first value of statistical indicant；
S34, the second core read the value of the second mark bit register, when the value read is the first value of statistical indicant, the second core
It writes data into the second address field, and the value of the second mark bit register is set to the second value of statistical indicant；
S35, the first core read the value of the second mark bit register, when the value read is the second value of statistical indicant, the first core
The data in the second address field are read, and the value of the second mark bit register is set to the first value of statistical indicant.
5. the signal processing framework transplantation method based on ZYNQ platform as claimed in claim 2, which is characterized in that the S4
In, comprising the following steps:
S41, PL are arranged in end: the first random access memory, and the data and interactive information at the end PL are write in the storage end PS；Second deposits at random
The data and interactive information at the end PS are write in reservoir, the storage end PL；
S42, the first random access memory and the second random access memory are connected in GP bus；
The end S43, PS writes data into the first random access memory by GP bus, and notifies the end PL to read data by GPIO；PL
End updates the data of the second random access memory, and notifies the end PS to read data by GPIO.
6. the signal processing framework transplantation method based on ZYNQ platform as described in claim 1, which is characterized in that the S5
In, comprising the following steps:
The end S51, PS configures directmemoryaccess device by GP bus, and starts the IP kernel of directmemoryaccess device；
The input data of fourier transformation module is transferred to Fourier transformation mould by HP bus by S52, directmemoryaccess device
The IP kernel of block, and the output data of fourier transformation module is transferred to by the end PS by HP bus.
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Application publication date: 20190412 |