CN109599389A - A kind of integrated circuit encapsulating structure - Google Patents
A kind of integrated circuit encapsulating structure Download PDFInfo
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- CN109599389A CN109599389A CN201811555036.0A CN201811555036A CN109599389A CN 109599389 A CN109599389 A CN 109599389A CN 201811555036 A CN201811555036 A CN 201811555036A CN 109599389 A CN109599389 A CN 109599389A
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 150000001875 compounds Chemical class 0.000 claims abstract description 18
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 17
- 238000005538 encapsulation Methods 0.000 claims description 26
- 239000004642 Polyimide Substances 0.000 claims description 22
- 229920001721 polyimide Polymers 0.000 claims description 22
- 239000003990 capacitor Substances 0.000 claims description 17
- 239000004952 Polyamide Substances 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- 229920002647 polyamide Polymers 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 150000002466 imines Chemical class 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 14
- 230000008901 benefit Effects 0.000 abstract description 7
- 238000011161 development Methods 0.000 abstract description 6
- 230000010354 integration Effects 0.000 abstract description 6
- 238000004891 communication Methods 0.000 abstract description 4
- 229910002601 GaN Inorganic materials 0.000 abstract description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 abstract description 3
- 239000002253 acid Substances 0.000 abstract 1
- 150000003949 imides Chemical class 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 14
- 238000000034 method Methods 0.000 description 13
- 239000000758 substrate Substances 0.000 description 10
- 238000004806 packaging method and process Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 102100034112 Alkyldihydroxyacetonephosphate synthase, peroxisomal Human genes 0.000 description 1
- 101000799143 Homo sapiens Alkyldihydroxyacetonephosphate synthase, peroxisomal Proteins 0.000 description 1
- 238000012356 Product development Methods 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000000848 angular dependent Auger electron spectroscopy Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- -1 figure label 109.3 Chemical class 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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- 229920005989 resin Polymers 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
The present invention relates to radar communication fields, it is particularly used for the integrated circuit encapsulating structure of multi-chip package, including first kind bare chip, the second class bare chip, metal layer and artificial dielectric's layer, the metal layer includes the first redistributing layer and the second redistributing layer；The metal layer and artificial dielectric's strata acid imide are staggeredly stacked, and the bare chip is wrapped in artificial dielectric capsulation material mold compound, and first redistributing layer is connect with the bare chip.The application integrates the chip and discrete device of a variety of variety classes unlike materials, it is made into a mini system, the huge advantage in volume can be obtained, the compounds bare chips such as traditional metal-oxide semiconductor (MOS) (CMOS) bare chip and GaAs, gallium nitride are integrated in the same package interior, the performances such as the high-power low-noise of the low cost of CMOS chip, high integration and compound chip can be taken into account, the performance of product can be promoted on the whole, reduce cost, promote integrated level, development difficulty is reduced, the development cycle is shortened.
Description
Technical field
The present invention relates to radar communication fields, are particularly used for the integrated circuit package knot of multi-chip package
Structure.
Background technique
For such as 5G millimetre-wave attenuator, satellite communication, trailer-mounted radar application RF device may include be integrated with more it is naked
The chip of chip or discrete device, the integrated antenna package technology are referred to as system in package (SIP).Under millimeter wave frequency band,
The beam scanning of antenna array depends on the multifunction chip for being integrated with phase shifter, amplifier, attenuator.And in millimeter wave frequency band
Under, the space attenuation of electromagnetic wave increases, and Signal-to-Noise reduces, and needs to be promoted the signal gain and signal power of chip, and drop
Low-noise factor, the multifunction chip for different poliarizing antennas also need to have polarization switching function, the RF dress of transceiver
Chip while integrated transceiver channel are also needed in setting.There is low cost, the advantage of high integration using the chip of CMOS technology, but
It is that gain, power and noise coefficient will be inferior to gallium arsenide chips, correspondingly, gallium arsenide chips are at high cost, and integrated level is low, because
This is by CMOS bare chip and GaAs bare chip by that can bring cost inside integrative packaging Integration ofTechnology to same encapsulation
With the advantage in performance, the advantages of being provided simultaneously with CMOS chip and gallium arsenide chips.Compared to single bare chip, using one
The advantages that changing the integrated chip of encapsulation technology has the development cycle short, at low cost, and technical risk is small.EWLB encapsulation has ball bar battle array
Arrange (BGA) and and redistributing layer of the BGA in same main surface, and can have two layers or more of redistributing layer, by photoetching,
Electrically connecting between first layer RDL and second layer RDL may be implemented in the via hole that the methods of development, magnetron sputtering and plating are formed
It connects.The opposite major surfaces of eWLB encapsulation may also be referred to as the front and back sides of encapsulation, be artificial dielectric mold compound material
Material is covered.
It can integrate the chip of more different process unlike materials in encapsulation using eWLB encapsulation concept, CMOS chip mentions
For functions such as multichannel phase shift, gain, decaying, gallium arsenide chips provide additional gain, polarization switching, transmitting-receiving switching, reduce
The functions such as chip overall noise coefficient, realize electrical connection by the first RDL between each chip, and electrical connections RDL needs are done
Impedance matching, to guarantee reasonable Insertion Loss and return loss.And the thickness of artificial dielectric's polyimide layer and the size of BGA and
Away from the final electrical property that can influence chip.Redistributing layer (RDL) metal routing size of eWLB encapsulation simultaneously is shorter, and encapsulation is brought into
Parasitic parameter influence it is smaller compared to conventional package, be based on this reason, eWLB encapsulation can be used for the vehicle-mounted thunder of 76-81GHz
Up to device, package dimension and bare crystalline chip size ratio can control 1.2:1 hereinafter, simultaneously as eWLB encapsulation does not include in itself
Package substrate, and reduction processing can be done to encapsulation back side artificial dielectric mold compound material, therefore eWLB encapsulation tool
There is lesser thickness, the heat-transfer path at the encapsulation back side can be shortened, promote the integral heat sink performance of chip.To sum up, eWLB is one
Kind can be used for a kind of high performance packing forms of small size of millimeter wave frequency band.
Generally chip cooling performance is influenced by the thermal coefficient and package thickness of material, using the silicon substrate of doping
It is supported as encapsulation, the huge improvement of heat dissipation performance can be brought, while reducing silicon substrate or artificial dielectric mold
The thickness of compound can also bring the improvement of heat dissipation performance.
The patent of existing related application such as Publication No. CN107785358A, CN103383923A, CN108538781A and
Although the patent of invention of CN107265389A, above-mentioned patent also belong to integrated circuit package structure, but its there are encapsulating structures
Complicated, the higher problem of technology difficulty, and above-mentioned patent is not to stress integrating for unlike material bare chip.
Summary of the invention
For achieving the above object, the application realizes by the following technical solutions:
A kind of integrated circuit encapsulating structure, it is characterised in that: including first kind bare chip, the second class bare chip, metal
Layer and artificial dielectric's polyimide layer, the metal layer include the first redistributing layer and the second redistributing layer；The metal layer
It being staggeredly stacked with artificial dielectric's polyimide layer, bare chip is wrapped in artificial dielectric mold compound, and described first
Redistributing layer is connect with the bare chip.
Artificial dielectric's polyimide layer includes at least the first artificial dielectric layer and the second artificial dielectric layer, the
It is the first redistributing layer on one artificial dielectric's layer, is the second artificial dielectric layer on first redistributing layer, described second
It is the second redistributing layer on artificial dielectric's layer.That is the relationship of artificial dielectric's layer and metal layer can simply be interpreted as polyamides Asia
Amine-metal-polyimide-metal is staggeredly stacked structure.
The first kind bare chip is CMOS bare chip, and quantity is 1, and the second class bare chip is GaAs bare crystalline
Piece, quantity are 4.
Artificial dielectric's polyimide layer includes the multiple form of metal being arranged in grid.The grid refers to
Ball grid array can do some metallic patterns, such as antenna element, microstrip filter etc among ball grid array.
Artificial dielectric's polyimide layer is to be filled between the first redistributing layer and the second redistributing layer, while also filling out
It fills among the metallic pattern of the first redistributing layer and the second redistributing layer.Namely the first redistributing layer and the second redistributing layer
In the space that is not occupied by a metal have artificial dielectric layer.Artificial dielectric layer can have two layers, three layers it is even more.
Discrete device can be integrated in encapsulation.
The deviding device includes discrete capacitor, discrete inductance, discrete resistors, filter, SAW device, bulk acoustic wave device
It is a variety of in part and MEMS sensor.It can need to be placed in addition to other positions with sufficient space where chip according to project
It sets, is usually located at bare chip surrounding.
Using BGA Package.
The artificial dielectric mold compound of package bare chip can be substituted for silicon substrate, with improving heat radiation efficiency.
Beneficial effects of the present invention:
1. the chip and discrete device that can integrate a variety of variety classes unlike materials are made into a small system inside same encapsulation
System, can obtain the huge advantage in volume, by the compounds bare chip collection such as traditional CMOS bare chip and GaAs, gallium nitride
At in the same package interior, can take into account CMOS chip low cost, high integration and compound chip (such as gallium nitride and
Gallium arsenide chips) the performances such as high-power low-noise, the performance of product can be promoted on the whole, reduce cost, promoted integrated
Degree reduces development difficulty, shortens the development cycle.
2. the encapsulation of this type is since encapsulation cabling is very short, applying frequency is very high, and electrical property is outstanding and property in high frequency
Can be very stable, it is that it is currently known to the highest encapsulated types of the applying frequency of volume production.
3. this type, which encapsulates no package substrate, can be effectively reduced envelope compared to conventional substrate class system in package
Body volume and weight is filled, the miniaturization and portability of device are facilitated.The process-cycle of not no package substrate simultaneously, product development
Period is shorter, is conducive to quickly emerging for product.
4. device can be substantially improved after being thinned by artificial dielectric's mold compound material or change silicon substrate into
The heat dissipation performance of part can be applied to the encapsulation of high power device.
5. this type belongs to a kind of novel forms of system in package (SIP), eWLB encapsulation and tradition SIP encapsulation are had both
The advantages of.
Detailed description of the invention
Fig. 1-Fig. 2 is this integrated packaging method primary structure side view and top view.
Fig. 3 is the structure top view that this integrated circuit package method includes the discrete original parts such as resistance capacitance.
Fig. 4 is the structural side view that this integrated circuit package method includes capacitor.
Fig. 5-Fig. 6 is the topology view that this integrated circuit methods uses capacitor.
In attached drawing:
The pad of 101- bare chip chip, the first redistributing layer of 102-, 103- ball grid array, 104- multilayer printed circuit board,
105- via hole, 106- GaAs bare chip, the second redistributing layer of 107-, 108-CMOS bare chip, 109- artificial dielectric mold
Compound, 110- artificial dielectric's polyimide layer, 111- metalized pads, 201- capacitor bottom land, 202- capacitance electrode
Pad, 211- high dielectric constant artificial dielectric.
Specific embodiment
This integrated circuit package method is described in detail below with reference to view.
Embodiment 1
A kind of integrated circuit encapsulating structure, it is characterised in that: including first kind bare chip, the second class bare chip, metal
Layer and artificial dielectric's polyimide layer, the metal layer include the first redistributing layer 102 and the second redistributing layer 107；It is described
Metal layer and artificial dielectric's polyimide layer are staggeredly stacked, and bare chip is wrapped in artificial dielectric mold compound 109
In, first redistributing layer 102 is connect with the bare chip.
Artificial dielectric's polyimide layer 110 includes at least the first artificial dielectric layer and the second artificial dielectric
Layer, it is the first redistributing layer 102 on the first artificial dielectric layer, is the second artificial dielectric on first redistributing layer 102
Layer, it is the second redistributing layer 107 on the second artificial dielectric layer.I.e. artificial dielectric's layer can letter with the relationship of metal layer
Polyimide-metal-polyimide-metal is singly interpreted as to be staggeredly stacked structure.
The first kind bare chip is CMOS bare chip 108, and quantity is 1, and the second class bare chip is that GaAs is naked
Chip 106, quantity are 4.
Artificial dielectric's polyimide layer 110 includes the multiple form of metal being arranged in grid.The grid refers to
Be ball grid array 103, can do some metallic patterns among ball grid array 103, for example, antenna element, microstrip filter it
Class.
Artificial dielectric's polyimide layer 110 is it for being filled in the first redistributing layer 102 and the second redistributing layer 107
Between, while being also filled among the metallic pattern of the first redistributing layer 102 and the second redistributing layer 107.Namely first divides again
There is artificial dielectric layer polyimides in the space not being occupied by a metal in layer of cloth 102 and the second redistributing layer 107.Polyamides is sub-
Amine layer can have two layers, three layers it is even more.
Discrete device can be integrated in encapsulation.
The deviding device includes discrete capacitor, discrete inductance, discrete resistors, filter, SAW device, bulk acoustic wave device
It is a variety of in part and MEMS sensor.It can be needed to be placed in the position with sufficient space according to project, be usually located at bare chip
Surrounding.
Using BGA Package.
The artificial dielectric mold compound 109 of package bare chip can be substituted for silicon substrate, be imitated with heat radiation
Rate.
Embodiment 2
It as shown in Figs. 1-2, include a CMOS bare chip 108 and four GaAs bare chips inside this integrative packaging method
106, artificial dielectric mold compound109 are wrapped in bare chip back, play support and protective effect, bare chip to chip
The pad 101 of chip, CMOS bare chip and GaAs bare chip pass through via hole 105 and first layer redistribution layer 107(RDL) it realizes
Connection, bare chip surface are covered with two layers of redistribution layer the-the first redistributing layer 102 and the second redistributing layer 107, two layers of redistribution
Polyimides 110 is filled between layer, the first redistributing layer realizes electrical connection by via hole and the second redistributing layer.This integration
Packaging method second layer redistribution layer is the under-bump metallization pad (UBM) 111 of ball grid array 103.Ball grid array passes through welding
It is connected to multilayer printed circuit board (PCB) 104.The radiofrequency signal cabling RDL107 needs that CMOS chip is connected with gallium arsenide chips
Circuit Matching is done, to realize the maximum power transfer of radiofrequency signal.The artificial dielectric mold of chip back covering
Compound109 can control thickness by reduction process, which needs comprehensive mechanical intensity, surface warp and radiating requirements
Comprehensively consider decision.The artificial dielectric can be substituted for silicon substrate simultaneously, with heat radiation performance.Two layers of artificial dielectric
The thickness of layer-polyimides needs generally to require thickness in 10um or more according to the decision of Electromagnetic Simulation result.CMOS in figure
Bare chip 108 and GaAs bare chip 106 can be substituted for the bare chip of other materials or other function, encapsulating structure and this
Unanimously.It should be noted that the size and spacing of BGA ball grid array 103 are to radio-frequency performance when chip is applied to millimeter wave frequency band
Influence it is huge, need by Electromagnetic Simulation determine, the BGA radio-frequency performance of the small spacing of small size is more excellent, RDL cabling Insertion Loss and return loss
It can accomplish via hole 105 and the first redistributing layer smaller, between metalized pads 111 correspondingly and two layers of redistribution layer
102 are also required to determine optimal size by Electromagnetic Simulation.
As shown in figure 3, this packaging method can be internally integrated discrete device in encapsulation, it is outer to provide power filter etc. for chip
Circuit is enclosed, discrete device includes being not limited to capacitor, resistance, inductance, filter, sensor etc..Can according to actual chips area and
Cost makes trade-offs.201 be chip capacity back electrode, power filter effect is provided for the power supply of GaAs bare chip, to filter out spy
Determine the power supply noise of frequency range, guarantees power supply ripple in the reasonable scope.
Fig. 4 illustrates the structure of bare chip and discrete device integrative packaging by taking capacitor as an example, as shown, two of capacitor
Electrode pad 202 is electrically connected in same principal plane, the electrode of capacitor and the pad of chip by the realization of the first redistributing layer, and first
Redistributing layer is realized by via hole 105 and the electrical connection of bare chip pad 101 and capacitance electrode pad 202, and 201 be chip electricity
Two electrodes of the back electrode of appearance, capacitor are connected respectively to above different BGA 205 by via hole and redistribution layer, same
There can be multiple via holes above capacitance electrode pad.Two layers of redistribution layer is filled with artificial dielectric's layer-polyimides.Same bare crystalline
Piece and capacitor are wrapped in artificial dielectric mold compound 109, to protect and support bare chip.
As shown in Fig. 5-6, the structure chart of capacitor is used for integration encapsulation, capacitance electrode pad 202 is in same main table
Face, 201 be capacitor bottom land, and high dielectric constant artificial dielectric 211, this Shen are filled between bottom land and capacitance electrode
Capacitance ceramic dielectric material please be use, such capacitor has strict demand to electrode pad surface smoothness, and material is generally gold.Electricity
Hold height to need to keep lesser difference with bare chip height (within < 0.2mm).Similar with capacitor, remaining discrete device needs
It asks electrode pad in the same side, electrical connection is realized by via hole and first layer redistribution layer.
In this application, there are three types of the main artificial dielectrics mentioned: 1, metal and the staggered lamination knot of artificial dielectric
Structure, the artificial dielectric in lamination are polyimides organic resin, are known as artificial dielectric's polyimide layer in the application, that is, scheme
Middle label 110；2, the artificial dielectric for wrapping up chip periphery is mold compound material, and concrete model is a variety of, in the application
Referred to as artificial dielectric mold compound, i.e. figure label 109.3, the medium between two electrodes of capacitor is usually ceramics
Material, it is also possible to it is other dielectric materials, also belongs to artificial dielectric, the application is known as high dielectric constant artificial dielectric,
I.e. 211 in figure.
The embodiment of integrated circuit package can be used in mm wave RF device, for example, can be used in and defend
In star communication antenna battle array, the functions such as amplitude modulation, phase shift, amplification, decaying are provided for radiofrequency signal, are the core component of antenna array.
In other examples, integrative packaging method can be used for for more range applications in 76-81GHz vehicle radar system, such as
Senior Officer's auxiliary system applies (ADAS).In other examples, integrative packaging method can be used for 5G millimetre-wave attenuator and set
In standby, the functions such as beam forming and beam scanning are provided.
Claims (8)
1. a kind of integrated circuit encapsulating structure, it is characterised in that: including first kind bare chip, the second class bare chip, gold
Belong to layer and artificial dielectric's polyimide layer (110), the metal layer includes the first redistributing layer (102) and the second redistributing layer
(107)；The metal layer and artificial dielectric's polyimide layer (110) are staggeredly stacked, and bare chip is wrapped in artificial dielectric
Mold compound(109) in, first redistributing layer (102) connect with the bare chip.
2. a kind of integrated circuit encapsulating structure according to claim 1, it is characterised in that: the artificial dielectric
Polyimide layer (110) includes at least the first artificial dielectric layer and the second artificial dielectric layer, on the first artificial dielectric layer
It is the second artificial dielectric layer, the second artificial electricity on first redistributing layer (102) for the first redistributing layer (102)
It is on dielectric layer the second redistributing layer (107).
3. a kind of integrated circuit encapsulating structure according to claim 1, it is characterised in that: the first kind bare crystalline
Piece is CMOS bare chip (108), and quantity is 1, and the second class bare chip is GaAs bare chip (106), and quantity is 4.
4. a kind of integrated circuit encapsulating structure according to claim 1, it is characterised in that: the artificial dielectric
Polyimide layer (110) includes the multiple form of metal being arranged in grid.
5. a kind of integrated circuit encapsulating structure according to claim 2, it is characterised in that: artificial dielectric's polyamides
Imine layer (110) is filled between the first redistributing layer (102) and the second redistributing layer (107), while being also filled in first
Among the metallic pattern of redistributing layer (102) and the second redistributing layer (107).
6. a kind of integrated circuit encapsulating structure according to claim 1, it is characterised in that: this encapsulating structure can collect
At discrete device in encapsulation.
7. a kind of integrated circuit encapsulating structure according to claim 6, it is characterised in that: the deviding device includes
It is more in discrete capacitor, discrete inductance, discrete resistors, filter, SAW device, bulk acoustic wave device and MEMS sensor
Kind.
8. a kind of integrated circuit encapsulating structure according to claim 1, it is characterised in that: sealed using ball grid array
Dress.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811555036.0A CN109599389A (en) | 2018-12-19 | 2018-12-19 | A kind of integrated circuit encapsulating structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811555036.0A CN109599389A (en) | 2018-12-19 | 2018-12-19 | A kind of integrated circuit encapsulating structure |
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| CN109599389A true CN109599389A (en) | 2019-04-09 |
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| CN201811555036.0A Pending CN109599389A (en) | 2018-12-19 | 2018-12-19 | A kind of integrated circuit encapsulating structure |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080136002A1 (en) * | 2006-12-07 | 2008-06-12 | Advanced Chip Engineering Technology Inc. | Multi-chips package and method of forming the same |
| CN105810647A (en) * | 2016-04-22 | 2016-07-27 | 宜确半导体（苏州）有限公司 | Radio-frequency switch integration module and integration method thereof, and radio-frequency front-end integrated circuit |
| CN107799483A (en) * | 2016-08-31 | 2018-03-13 | 日月光半导体制造股份有限公司 | Semiconductor package and its manufacture method |
| CN209471961U (en) * | 2018-12-19 | 2019-10-08 | 成都瑞迪威科技有限公司 | A kind of integrated circuit encapsulating structure |
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2018
- 2018-12-19 CN CN201811555036.0A patent/CN109599389A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080136002A1 (en) * | 2006-12-07 | 2008-06-12 | Advanced Chip Engineering Technology Inc. | Multi-chips package and method of forming the same |
| CN105810647A (en) * | 2016-04-22 | 2016-07-27 | 宜确半导体（苏州）有限公司 | Radio-frequency switch integration module and integration method thereof, and radio-frequency front-end integrated circuit |
| CN107799483A (en) * | 2016-08-31 | 2018-03-13 | 日月光半导体制造股份有限公司 | Semiconductor package and its manufacture method |
| CN209471961U (en) * | 2018-12-19 | 2019-10-08 | 成都瑞迪威科技有限公司 | A kind of integrated circuit encapsulating structure |
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