CN109586678B - Channel amplifier and method applied to channel amplifier - Google Patents
Channel amplifier and method applied to channel amplifier Download PDFInfo
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- CN109586678B CN109586678B CN201710898001.6A CN201710898001A CN109586678B CN 109586678 B CN109586678 B CN 109586678B CN 201710898001 A CN201710898001 A CN 201710898001A CN 109586678 B CN109586678 B CN 109586678B
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- amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
Abstract
The channel amplifier comprises an amplifier, a multiplexer and a switching circuit, wherein the channel amplifier selectively operates in a buffering stage or a comparison stage; when the channel amplifier is operated in a buffer stage, the switching circuit couples the output end of the amplifier to a first input end of the amplifier, so that a first input signal received by a second input end of the amplifier is transmitted to the first output end of the channel amplifier; when the channel amplifier operates in a comparison stage, the switching circuit transmits the first input signal at the first output terminal of the channel amplifier to the first input terminal of the amplifier for comparison with a second input signal received at the second input terminal of the amplifier, and outputs a comparison result to the output terminal of the amplifier.
Description
Technical Field
The invention relates to a channel amplifier applied to a liquid crystal panel and a method applied to the channel amplifier.
Background
In the conventional application of the liquid crystal panel, the driving circuit includes a channel amplifier (channel amplifier) at the rear end of the driving circuit, which is used as a buffer to continuously output the front end signal to the rear end, however, the channel amplifiers in the general driving circuit all have the disadvantages of insufficient buffering capability, resulting in signal distortion, noise enhancement, etc., and if the buffering capability of the channel amplifier is enhanced, the cost such as power consumption or circuit area increase may be caused.
Disclosure of Invention
It is an object of the present invention to provide a channel amplifier and a method applied to the channel amplifier to solve the above problems.
According to an embodiment of the present invention, a channel amplifier is disclosed, comprising: an amplifier, a multiplexer and a switching circuit, wherein the multiplexer is coupled between an output terminal of the amplifier and a first output terminal of the channel amplifier, and the switching circuit is coupled to the amplifier and the multiplexer, wherein the channel amplifier selectively operates in a buffering stage or a comparing stage; when the channel amplifier operates in a buffering stage, the switching circuit couples the output terminal of the amplifier to a first input terminal of the amplifier, so that a first input signal received by a second input terminal of the amplifier is transmitted to the first output terminal of the channel amplifier through the multiplexer; when the channel amplifier operates in a comparison stage, the switching circuit transmits the first input signal at the first input terminal of the channel amplifier to the first input terminal of the amplifier for comparison with a second input signal received at the second input terminal of the amplifier, and outputs a comparison result to the output terminal of the amplifier.
According to an embodiment of the present invention, a method applied to a channel amplifier is disclosed, comprising: selectively operating the channel amplifier in a buffering stage and a comparing stage; when the channel amplifier operates in the buffering stage, coupling an output terminal of an amplifier in the channel amplifier to a first input terminal of the amplifier, so that a first input signal received by a second input terminal of the amplifier is transmitted to a first output terminal of the channel amplifier through a multiplexer in the channel amplifier; and when the channel amplifier is operated in the comparison stage, transmitting the first input signal on the first input end of the channel amplifier to the first input end of the amplifier to be compared with a second input signal received by the second input end of the amplifier, and outputting a comparison result to the output end of the amplifier.
Drawings
FIG. 1 is a schematic diagram of a channel amplifier according to an embodiment of the invention.
FIG. 2 is a schematic diagram of the channel amplifier of FIG. 1 operating in a buffering phase.
Fig. 3 is a schematic diagram of the channel amplifier according to fig. 1 operating in a comparison phase.
FIG. 4 is a timing diagram of a channel amplifier according to an embodiment of the invention.
FIG. 5 is a diagram illustrating the channel amplifier of FIG. 1 operating in a buffering phase when the polarity is switched.
FIG. 6 is a schematic diagram of the channel amplifier of FIG. 1 operating in a comparison phase when inverting polarity.
[ notation ] to show
100. Channel amplifier
110. 210 digital-to-analog converter
120. 220 amplifier
130. Control circuit
140. 240 switching circuit
150. Multiplexer
OUT, OUT1, OUT2 output terminals
Vp, vout, vp ', vout' output signals
IP, IP' input signal
SW1-SW3 switch
IN1, IN2 input terminals
CTRL control signal
Detailed Description
Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This description and the appended claims do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Furthermore, the term "coupled" is used herein to encompass any direct or indirect electrical connection, such that if a first device is coupled to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
Fig. 1 is a schematic diagram of a channel amplifier 100 according to an embodiment of the invention, as shown in fig. 1, the channel amplifier 100 includes Digital-to-Analog converters (DACs) 110 and 210, amplifiers 120 and 220, a control circuit 130, switching circuits 140 and 240, a multiplexer 150, and output terminals OUT1 and OUT2, wherein the Digital-to-Analog Converter 110, the amplifier 120, and the switching circuit 140 form a positive polarity portion of a differential circuit in the channel amplifier 100 of fig. 1, and the Digital-to-Analog Converter 210, the amplifier 220, and the switching circuit 240 form a negative polarity portion of the differential circuit in the channel amplifier 100 of fig. 1, respectively. The channel amplifier 100 can selectively operate IN a buffering stage and a comparing stage, the amplifier 120 includes input terminals IN1, IN2 and an output terminal OUT, wherein the input terminal IN1 is respectively coupled to the output terminal OUT, the output terminal OUT1 of the channel amplifier 100 and the channel amplifier 100 through switches SW1, SW2 and SW3 included IN the switching circuit 140 according to the operation of the channel amplifier IN the buffering stage, the comparing stage or during the polarity switching, wherein the switching states of the switches SW1 to SW3 are controlled by the control circuit 130 according to the operation stage of the channel amplifier 100 through a control signal CTRL, the input terminal IN2 of the amplifier 120 is coupled to the digital-to-analog converter 110 for receiving the input signal IP from the digital-to-analog converter 110 when the channel amplifier 100 operates IN each stage, and the multiplexer 150 is also controlled by the control signal CTRL sent by the control circuit 130 to be coupled to the channel amplifier 100 with the operation IN different stages, and the switching states of the switches SW1 to SW3 included IN the switching circuit 140 and the multiplexer 150 will be discussed IN detail IN the following paragraphs. The present invention is not limited to the embodiments of the digital-to- analog converters 110 and 210, and similarly, the present invention is not limited to the embodiments of the amplifiers 120 and 220, the switches SW1 to SW3, and the multiplexer 150.
Fig. 2 is a schematic diagram of the channel amplifier 100 of fig. 1 operating IN a buffering phase, as shown IN fig. 2, when the channel amplifier 100 operates IN the buffering phase, the control circuit 130 controls the switch SW1 IN the switching circuit 140 to be turned off and the switches SW2 and SW3 to be turned on through the control signal CTRL, at this time, the input terminal IN1 of the amplifier 120 is coupled to the output terminal OUT of the amplifier 120 through the switch SW1, the amplifier 120 forms a buffer and transmits the input signal IP received from the digital-to-analog converter 110 to the output terminal OUT of the amplifier 120, and an output signal Vp is formed at the output terminal OUT of the amplifier 120, as shown IN fig. 2, the control circuit 130 also controls the multiplexer 150 through the control signal CTRL, so that the multiplexer 150 couples the output terminal OUT of the amplifier 120 to the output terminal OUT1 of the channel amplifier 100 and generates an output signal Vout at the output terminal OUT1, IN other words, when the channel amplifier 100 operates IN the buffering phase, the switching circuit 140 and the multiplexer 150 are controlled through the control signal CTRL to transmit the input signal IP generated by the digital-to the output terminal OUT of the channel amplifier 110 to form the output signal Vout 1.
FIG. 3 is a schematic diagram illustrating the channel amplifier of FIG. 1 operating IN a comparison phase, as shown IN FIG. 3, when the channel amplifier 100 operates IN the comparison phase, the control circuit 130 controls the switch SW2 of the switching circuit 140 to be turned off and the switches SW1 and SW3 to be turned on by the control signal CTRL, at this time, the input terminal IN1 of the amplifier 120 is coupled to the output terminal OUT1 of the channel amplifier 100 by the switch SW2 and the output signal Vout at the output terminal OUT1 IN the previous buffering phase is transmitted to the input terminal IN1 of the amplifier 120, the amplifier 120 forms a comparator for comparing the output signal Vout with the input signal IP received by the input terminal IN2 from the DAC 110 at the time, and transmits the comparison result to the output terminal OUT of the amplifier 120 to form the output signal Vp; in addition, the control circuit 130 controls the multiplexer 150 to open the multiplexer 150 through the control signal CTRL, that is, the multiplexer 150 is no longer coupled between the output terminal OUT of the amplifier 120 and the output terminal OUT1 of the channel amplifier 100, in this embodiment, the control circuit 130 can turn off the power supply of the multiplexer 150 through the control signal CTRL, however, this is not a limitation of the present invention, and in other embodiments, the control signal CTRL can control a switch (not shown) in a path between the output terminal OUT of the amplifier 120 and the output terminal OUT1 of the channel amplifier 100, so that the output signal Vp is not coupled to the output terminal OUT1 through the multiplexer 150 at this time, and those skilled in the art can easily understand an embodiment of opening the multiplexer 150, and the detailed details are omitted here. IN other words, when the channel amplifier 100 operates IN the comparison stage, the control signal CTRL controls the switching circuit 140 and the multiplexer 150 to transmit the output signal Vout generated at the output terminal OUT1 IN the previous buffering stage to the input terminal IN1 of the amplifier 120 for comparison with the input signal IP received at the input terminal IN2 of the amplifier 120, and generate the comparison result at the output terminal OUT of the amplifier 120.
Fig. 4 is a timing diagram of the channel amplifier 100 according to an embodiment of the invention, and it can be seen from fig. 2 that when the channel amplifier 100 operates in the buffering stage, the control signal CTRL controls the switch SW1 in the switching circuit 140 to be turned off, the switches SW2-SW3 are turned on, and the output terminal OUT of the amplifier 120 is coupled to the output terminal OUT1 of the channel amplifier 100 through the multiplexer 150, at this time, the amplifier 120 forms a buffer, so that the input signal IP of the digital-to-analog converter 110 is transmitted to the output terminal OUT1 of the channel amplifier 100 to form the output signal Vout, for example, as shown in fig. 4, if the input signal IP is a voltage signal of 9.2 volts, the output signal Vp and the output signal Vout are both voltage signals of 9.2 volts through the amplifier 120 and the multiplexer 150 forming the buffer; as can be seen from fig. 3, when the channel amplifier 100 operates IN the comparison stage, the control signal CTRL controls the switch SW2 IN the switching circuit 140 to be turned off, the switches SW1 and SW3 are turned on, and the multiplexer 150 is turned off, so that the output signal Vout of the voltage signal of 9.2 volts originally generated at the output terminal OUT1 is coupled to the input terminal IN1 of the amplifier 120, and the amplifier 120 forms a comparator at this time, for example, if the input signal IP of the digital-to-analog converter 110 is the voltage signal of 17.8 volts at this time, the amplifier 120 compares the input signal IP with the output signal Vout of the previous buffering stage, and since the input signal IP voltage (17.8 volts) is greater than the output signal Vout (9.2 volts), the amplifier 120 outputs the comparison result of 18 volts at the output terminal OUT with the logic value of 1 at this time, so as to form the output signal Vp; then, when the channel amplifier 100 operates in the buffering phase again, the control signal CTRL controls the switch SW1 in the switching circuit 140 to be closed, the switches SW2-SW3 are opened, and the output terminal OUT of the amplifier 120 is coupled to the output terminal OUT1 of the channel amplifier 100 through the multiplexer 150, at this time, the amplifier 120 forms a buffer, so that the input signal IP with the amplitude of 17.8 volts is transmitted to the output terminal OUT1 of the channel amplifier 100 to form the output signal Vout, and since the output signal Vp is a voltage signal with the amplitude of 18 volts in the previous comparison phase, when the channel amplifier 100 operates in the buffering phase again, the output signal Vp can be rapidly decreased from the voltage signal with the amplitude of 18 volts to the voltage signal with the amplitude of 17.8 volts, and the time for the output signal Vout at the output terminal OUT1 to be increased from 9.2 volts to 17.8 volts can be increased, so that the output terminal OUT of the amplifier 120 can be charged to 18 volts in advance, thereby solving the problem of insufficient buffering capability of the channel amplifier in the prior art. It should be noted that the time periods of the buffering phase and the comparing phase, the signal strengths of the output signal Vp and the output signal Vout in the embodiment of fig. 4 are only exemplary and not a limitation of the present invention.
IN practical applications of the liquid crystal panel, the voltage signal of the positive polarity portion circuit, i.e. the circuit portion formed by the digital-to-analog converter 110, the amplifier 120 and the switching circuit 140 IN the channel amplifier 100, is between 9 volts and 18 volts, and the voltage signal of the negative polarity portion circuit, i.e. the circuit portion formed by the digital-to-analog converter 210, the amplifier 220 and the switching circuit 240 IN the channel amplifier 100, is between 0 volts and 9 volts, and the operation of the negative polarity portion circuit is easily understood by those skilled IN the art, as follows, referring to fig. 2 and 3 again, when the channel amplifier 100 is IN the buffering stage, the operation of the negative polarity portion circuit also causes the input signal IP ' of the digital-to-analog converter 210 to generate the output signal Vp ' through the amplifier 220 at the output terminal OUT of the amplifier 220, and further, the output signal Vp ' is coupled to the output terminal 2 of the channel amplifier 100 through the multiplexer 150, and the output signal Vout ' is generated at the output terminal OUT2, and when the channel amplifier 100 is IN the comparing stage, the output signal Vout ' at the output terminal OUT2 is coupled to the output terminal OUT2 of the amplifier 220, and when the amplitude of the amplifier 100 is increased from the input terminal 220 to the analog signal, the amplifier 100 is increased from 0 voltage signal, and the amplitude of the amplifier 220 is increased from the positive polarity signal output terminal.
IN practical applications of the liquid crystal panel, IN order to avoid the liquid crystal polarization from being switched IN time, fig. 5 is a schematic diagram of the channel amplifier 100 IN fig. 1 operating IN a buffer phase when the polarity is switched, as shown IN fig. 5, when the channel amplifier 100 operates IN the buffer phase, the control circuit 130 controls the switch SW1 IN the switching circuit 140 to be closed and the switches SW2 and SW3 to be opened, at this time, the input terminal IN1 of the amplifier 120 is coupled to the output terminal OUT of the amplifier 120 through the switch SW1, the amplifier 120 forms a buffer, and transmits the input signal IP received from the digital-to-analog converter 110 to the output terminal OUT of the amplifier 120, and forms an output signal Vp at the output terminal OUT of the amplifier 120, and as shown IN fig. 5, the control circuit 130 also controls the multiplexer 150 through the control signal CTRL, so that the multiplexer 150 couples the output terminal of the amplifier 120 to the output terminal OUT2 of the channel amplifier 100, and generates an output signal Vout on the output terminal OUT2, IN other words, when the channel amplifier 100 operates IN the buffer phase, the multiplexer 150 controls the multiplexer 150 and the switching circuit 140 and the output signal CTRL 2 of the channel amplifier 110 to generate the output signal Vout.
FIG. 6 is a schematic diagram illustrating the channel amplifier of FIG. 1 operating IN a comparison stage when the polarity is switched, as shown IN FIG. 6, when the channel amplifier 100 operates IN the comparison stage, the control circuit 130 controls the switch SW3 of the switching circuit 140 to be turned off by the control signal CTRL and turns on the switches SW1 and SW2, at this time, the input terminal IN1 of the amplifier 120 is coupled to the output terminal OUT2 of the channel amplifier 100 by the switch SW3 and transmits the output signal Vout at the output terminal OUT2 IN the previous buffering stage to the input terminal IN1 of the amplifier 120, the amplifier 120 forms a comparator for comparing the output signal Vout with the input signal IP received by the input terminal IN2 from the DAC 110 at the time, and transmits the comparison result to the output terminal OUT of the amplifier 120 to form the output signal Vp; in addition, the control circuit 130 controls the multiplexer 150 to open the multiplexer 150 according to the control signal CTRL, i.e., the multiplexer 150 is no longer coupled between the output terminal OUT of the amplifier 120 and the output terminal OUT2 of the channel amplifier 100. IN other words, when the channel amplifier 100 operates IN the comparison stage, the switching circuit 140 and the multiplexer 150 are controlled by the control signal CTRL to transmit the output signal Vout generated at the output terminal OUT2 IN the previous buffering stage to the input terminal IN1 of the amplifier 120 and compare the input signal IP received at the input terminal IN2 of the amplifier 120, and generate the comparison result at the output terminal OUT of the amplifier 120, so as to achieve the effect of polarity inversion, and the detailed circuit operation of the channel amplifier 100 during polarity inversion is the same as the embodiment of fig. 2 and 3, and after reading the above paragraphs, a person skilled IN the art should easily understand the implementation of polarity inversion.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.
Claims (8)
1. A channel amplifier, comprising:
an amplifier;
a multiplexer coupled between the output of the amplifier and the first output of the channel amplifier;
a switching circuit coupled to the amplifier and the multiplexer; and
a control circuit;
wherein the channel amplifier selectively operates in a buffer phase or a compare phase; when the channel amplifier operates in the buffering stage, the switching circuit couples the output terminal of the amplifier to the first input terminal of the amplifier, so that the first input signal received by the second input terminal of the amplifier is transmitted to the first output terminal of the channel amplifier through the multiplexer; when the channel amplifier operates in the comparison stage, the switching circuit transmits the first input signal at the first output terminal of the channel amplifier to the first input terminal of the amplifier for comparison with a second input signal received at the second input terminal of the amplifier, and outputs a comparison result to the output terminal of the amplifier; and is
The control circuit is configured to transmit a control signal to the multiplexer when the channel amplifier operates in the comparison stage, so that the output terminal of the amplifier is not coupled to the first output terminal of the channel amplifier through the multiplexer, and transmit a control signal to the switching circuit, so that the output terminal of the amplifier is not coupled to the first input terminal of the amplifier.
2. The channel amplifier of claim 1, further comprising:
the digital-to-analog converter is used for generating the first input signal and the second input signal to the second input end of the amplifier.
3. A channel amplifier, comprising:
an amplifier;
a multiplexer coupled between the output of the amplifier and the first output of the channel amplifier;
a switching circuit coupled to the amplifier and the multiplexer; and
a control circuit;
when the multiplexer and the switching circuit receive the control signal and the channel amplifier operates in the buffering stage, the switching circuit couples the output end of the amplifier to the first input end of the amplifier, so that the first input signal received by the second input end of the amplifier is transmitted to the second output end of the channel amplifier through the multiplexer; and is provided with
The control circuit is configured to transmit a control signal to the multiplexer when the channel amplifier operates in the comparison stage, so that the output terminal of the amplifier is not coupled to the first output terminal of the channel amplifier through the multiplexer, and transmit a control signal to the switching circuit, so that the output terminal of the amplifier is not coupled to the first input terminal of the amplifier.
4. The channel amplifier of claim 3, wherein the switching circuit transmits the first input signal received by the second output of the channel amplifier in the buffering stage to the first input of the amplifier for comparison with the second input signal received by the second input of the amplifier and outputs the comparison result to the output of the amplifier when the multiplexer and the switching circuit receive the control signal and when the channel amplifier operates in the comparing stage.
5. A method applied to a channel amplifier, comprising:
selectively operating the channel amplifier in a buffer phase and a compare phase;
transmitting a control signal to the multiplexer; and
coupling an output terminal of an amplifier in the channel amplifier to a first input terminal of the amplifier when the channel amplifier operates in the buffering stage, so that a first input signal received by a second input terminal of the amplifier is transmitted to a first output terminal of the channel amplifier through the multiplexer in the channel amplifier; and
when the channel amplifier is operated in the comparison stage, transmitting the first input signal at the first input terminal of the channel amplifier to the first input terminal of the amplifier for comparison with a second input signal received at the second input terminal of the amplifier, and outputting a comparison result to the output terminal of the amplifier;
when the channel amplifier is operated in the comparison stage, the output end of the amplifier is controlled not to be coupled to the first output end of the channel amplifier through the multiplexer, and the output end of the amplifier is controlled not to be coupled to the first input end of the amplifier.
6. The method of claim 5, further comprising:
performing digital-to-analog conversion to generate the first input signal and the second input signal to the second input terminal of the amplifier.
7. A method applied to a channel amplifier, comprising:
selectively operating the channel amplifier in a buffer phase and a compare phase;
transmitting a control signal to the multiplexer; and
when the multiplexer receives the control signal and the channel amplifier operates in the buffering stage, the output end of the amplifier is coupled to the first input end of the amplifier, so that the first input signal received by the second input end of the amplifier is transmitted to the second output end of the channel amplifier through the multiplexer;
when the channel amplifier is operated in the comparison stage, the output end of the amplifier is controlled not to be coupled to the first output end of the channel amplifier through the multiplexer, and the output end of the amplifier is controlled not to be coupled to the first input end of the amplifier.
8. The method of claim 7, further comprising:
when the multiplexer receives the control signal and the channel amplifier operates in the comparison stage, the switching circuit transmits the first input signal received by the second output terminal of the channel amplifier in the buffering stage to the first input terminal of the amplifier for comparison with the second input signal received by the second input terminal of the amplifier, and outputs the comparison result to the output terminal of the amplifier.
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| CN201710898001.6A CN109586678B (en) | 2017-09-28 | 2017-09-28 | Channel amplifier and method applied to channel amplifier |
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| CN201710898001.6A CN109586678B (en) | 2017-09-28 | 2017-09-28 | Channel amplifier and method applied to channel amplifier |
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| CN109586678B true CN109586678B (en) | 2023-02-28 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101645247A (en) * | 2008-08-05 | 2010-02-10 | 奇景光电股份有限公司 | Source driver with plural-feedback-loop output buffer |
| CN101834596A (en) * | 2009-03-12 | 2010-09-15 | 奇景光电股份有限公司 | Output buffer and source driver |
| CN102487266A (en) * | 2010-12-02 | 2012-06-06 | 联咏科技股份有限公司 | Operational amplifier and display driving circuit applying same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8686759B2 (en) * | 2009-08-07 | 2014-04-01 | Synaptics Incorporated | Bi-directional channel amplifier |
| TWI398098B (en) * | 2010-02-04 | 2013-06-01 | Novatek Microelectronics Corp | Output buffer circuit capable of enhancing stability |
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2017
- 2017-09-28 CN CN201710898001.6A patent/CN109586678B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101645247A (en) * | 2008-08-05 | 2010-02-10 | 奇景光电股份有限公司 | Source driver with plural-feedback-loop output buffer |
| CN101834596A (en) * | 2009-03-12 | 2010-09-15 | 奇景光电股份有限公司 | Output buffer and source driver |
| CN102487266A (en) * | 2010-12-02 | 2012-06-06 | 联咏科技股份有限公司 | Operational amplifier and display driving circuit applying same |
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