CN109585547A - Groove type power semiconductor component and its manufacturing method - Google Patents
Groove type power semiconductor component and its manufacturing method Download PDFInfo
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- CN109585547A CN109585547A CN201710908789.4A CN201710908789A CN109585547A CN 109585547 A CN109585547 A CN 109585547A CN 201710908789 A CN201710908789 A CN 201710908789A CN 109585547 A CN109585547 A CN 109585547A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 188
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 94
- 238000010276 construction Methods 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 289
- 238000009413 insulation Methods 0.000 claims description 68
- 239000011229 interlayer Substances 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 18
- 238000002955 isolation Methods 0.000 claims description 17
- 230000000873 masking effect Effects 0.000 claims description 15
- 238000003475 lamination Methods 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 239000011159 matrix material Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 3
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- 150000004706 metal oxides Chemical class 0.000 description 8
- 230000005669 field effect Effects 0.000 description 7
- 230000000994 depressogenic effect Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
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- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
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- 230000005684 electric field Effects 0.000 description 1
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention discloses a kind of groove type power semiconductor component and its manufacturing method.The trench gate structure of groove type power semiconductor component includes a cover electrode (maskingelectrode), the grid and an interpolar dielectric layer between cover electrode (maskingelectrode) and grid above cover electrode (maskingelectrode).Before forming interpolar dielectric layer, formed trench gate structure the step of include at least: formed a laminated construction cladding element groove inner wall, wherein laminated construction include at least semiconductor material layer and one covering semiconductor material layer initial inner-dielectric-ayer；A heavily-doped semiconductor material is formed in the lower half of element groove；And removal a part is located at the initial inner-dielectric-ayer of the upper half of element groove, to expose a upper half of semiconductor material layer and the top of heavily-doped semiconductor material.In this way, can have wedge angle to avoid the bottom of the grid formed in subsequent fabrication process.
Description
Technical field
The present invention is to be related to a kind of power semiconductor and its manufacturing method, and have masking electricity more particularly to one kind
The groove type power semiconductor component and its manufacturing method of pole.
Background technique
Existing trench power metal-oxide semiconductor field-effect transistor (Power Metal Oxide Semiconductor
Field Transistor, Power MOSFET) work-loss costs can be divided into switch cost (switching loss) and conducting
(conducting loss) two major classes are lost, wherein the capacitance (Cgd) of gate/drain is to influence the important ginseng of switch cost
Number.If gate/drain capacitance is too high to will cause switch cost increase, and then limits cutting for power MOSFET transistor
Throw-over degree is unfavorable for using in high-frequency circuit.
Accordingly, there can be a screening for being located at gate trench lower half in existing trench power metal-oxide semiconductor field-effect transistor
Electrode (shielding electrode) is covered, to reduce gate/drain capacitance, not sacrifice conducting resistance (on-
Resistance increase breakdown voltage in the case where).And can in the state of maintaining identical breakdown voltage, using concentration compared with
High epitaxial layer can be obtained by lower conducting resistance in this way.
However, please referring to Fig. 1, the part section signal of existing trench power metal-oxide semiconductor field-effect transistor is shown
Figure.As shown in Figure 1, in trench power metal-oxide semiconductor field-effect transistor T, due to by thermal oxidation formed grid 10 with
When interpolar dielectric layer 12 between cover electrode (maskingelectrode) 11, the top surface of interpolar dielectric layer 12 can have there are two depressed area, the two recess
Two side walls s1, s2 of the area respectively close to groove h1.Therefore, after forming grid 10, the bottom of grid 10 can have to be filled out respectively
Enter two wedge angles 101,102 of two depressed areas.Two wedge angles 101,102 of 10 bottom of grid will lead to electric field and increase and reduce
The pressure resistance of trench power metal-oxide semiconductor field-effect transistor, to reduce the reliability of element.
Summary of the invention
Technical problem to be solved by the present invention lies in provide a kind of groove type power semiconductor component and its manufacturer
Method is initially formed layer of semiconductor material layer before forming interpolar dielectric layer, recessed to avoid the top surface generation of interpolar dielectric layer
It falls into.
In order to solve the above technical problems, a wherein technical solution of the present invention is to provide a kind of plough groove type
Power semiconductor comprising substrate, epitaxial layer and trench gate structure.Epitaxial layer is set on substrate and has at least
One is formed in the element groove in epitaxial layer.Trench gate structure is located in an at least element groove, and including outer insulation,
Cover electrode (maskingelectrode), grid and masking lamination.The inner wall of outer insulation cladding element groove.Cover electrode (maskingelectrode) is set at least one
The lower half of element groove.Grid is set in cover electrode (maskingelectrode), and is electrically insulated from cover electrode (maskingelectrode).It is outer to cover lamination covering
The inner wall once of side insulation layer, masking lamination include at least a semiconductor layer being separated from each other with cover electrode (maskingelectrode), and semiconductor
Layer is between lower inner wall and cover electrode (maskingelectrode).
Further, semiconductor layer be an extrinsic semiconductor layer or once doping semiconductor layer.
Further, masking lamination further includes an interlayer, and interlayer is between outer insulation and semiconductor layer.
Further, two opposite end faces of semiconductor layer form two segment differences between two opposite end faces of interlayer respectively
Structure.
Further, trench gate structure further includes an interpolar dielectric layer, and interpolar dielectric layer is located at cover electrode (maskingelectrode) and grid
Between pole, interpolar dielectric layer and isolation of semiconductor layer and grid, and two opposite side surfaces of interpolar dielectric layer are separately connected two
Segment difference structure.
Further, trench gate structure still further comprises side insulation layer in one, covers on the one of outer insulation
Inner wall, interior side insulation layer connection interlayer, and grid are by interior side insulation layer and outer insulation to be isolated with epitaxial layer.
Further, the material of interior side insulation layer is different from interlayer, and a part covering interpolar of interior side insulation layer is situated between
Electric layer.
Further, trench gate structure still further comprises the top of inner wall on the one of a covering outer insulation
The material of dielectric layer, upper dielectric layer is identical with interlayer, and upper dielectric layer connection interlayer is to form an intermediate dielectric layer.
Further, masking lamination further includes an inner-dielectric-ayer, and inner-dielectric-ayer is located at cover electrode (maskingelectrode) and semiconductor layer
Between.
In order to solve the above technical problems, an other technical solution of the present invention is to provide a kind of plough groove type
The manufacturing method of power semiconductor comprising form an epitaxial layer on a substrate；An element groove is formed in epitaxial layer
It is interior；A trench gate structure is formed in element groove, there is trench gate structure a cover electrode (maskingelectrode), one to be located in cover electrode (maskingelectrode)
The grid and an interpolar dielectric layer between cover electrode (maskingelectrode) and grid of side.Before forming interpolar dielectric layer, ditch is formed
The step of slot gate structure, includes at least: forming the inner wall of a laminated construction cladding element groove, wherein laminated construction is at least
Initial inner-dielectric-ayer including semiconductor material layer and a covering semiconductor material layer；Form a heavily-doped semiconductor material
In the lower half of element groove；And removal a part is located at the initial inner-dielectric-ayer of the upper half of element groove, to expose
One upper half of semiconductor material layer and the top of heavily-doped semiconductor material.
Further, the step of forming ditch slot number structure, which may further comprise:, aoxidizes heavy doping with a thermal oxidation
The top of semiconductor material and the upper half of semiconductor material layer, to form a thermal oxide layer, wherein not oxidized partly leads
Body material layer forms semi-conductor layer, and not oxidized heavily-doped semiconductor material forms cover electrode (maskingelectrode), and thermal oxide layer includes one
Sidewall portion and an isolation part in cover electrode (maskingelectrode), and the thickness of isolation part is greater than the thickness of sidewall portion；Remove sidewall portion
And partial isolation part, to form interpolar dielectric layer；And grid is formed in the upper half of element groove.
Further, laminated construction further includes an outer insulation and an intermediate dielectric layer, intermediate dielectric layer and half
Conductor material layer is between outer insulation and initial inner-dielectric-ayer.
Further, after the step of forming grid, two opposite sides of grid connect intermediate dielectric layer.
Further, before the step of forming grid, formed trench gate structure the step of may further comprise:
After removing sidewall portion and partial isolation part, the intermediate dielectric layer of a part is removed, and retains intermediate dielectric layer and is located at member
One interlayer of part lower half part of groove, wherein two opposite end faces of semiconductor layer are formed between two opposite end faces of interlayer respectively
Two segment difference structures；And form in one that side insulation layer is in element groove, to cover outer insulation.
Further, in the step of forming laminated construction, semiconductor material layer is extrinsic semiconductor layer or one
Doped semiconductor layer.
Further, the manufacturing method of groove type power semiconductor component, which may further comprise:, is forming trench-gate
After the step of structure, a matrix area and source region are formed in epitaxial layer.
One of beneficial effect of the invention is, groove type power semiconductor component and its system provided by the present invention
Make method, can by " before forming interpolar dielectric layer, formed a laminated construction cladding element groove inner wall " and " fold
Layer structure include at least semiconductor material layer and one covering semiconductor material layer initial inner-dielectric-ayer " technical solution,
The top surface of interpolar dielectric layer can be avoided to generate depressed area in the next steps, to avoid gate bottom that there is wedge angle.In this way, this
Groove type power semiconductor component manufactured by the manufacturing method of groove type power semiconductor component provided by inventive embodiments
It can grid pressure resistance with higher and higher reliability (reliability).
Be further understood that feature and technology contents of the invention to be enabled, please refer to below in connection with it is of the invention specifically
Bright and schema, however provided schema is merely provided for reference and description, is not intended to limit the present invention.
Detailed description of the invention
Fig. 1 is the partial cutaway schematic of existing trench power metal-oxide semiconductor field-effect transistor.
Fig. 2 is the flow chart of the wherein manufacturing method of the groove type power semiconductor component of an embodiment of the invention.
Fig. 3 A is part of the groove type power semiconductor component of a wherein embodiment of the invention in the step S301 of Fig. 2
Diagrammatic cross-section.
Fig. 3 B is part of the groove type power semiconductor component of a wherein embodiment of the invention in the step S302 of Fig. 2
Diagrammatic cross-section.
Fig. 3 C is part of the groove type power semiconductor component of a wherein embodiment of the invention in the step S303 of Fig. 2
Diagrammatic cross-section.
Fig. 3 D is part of the groove type power semiconductor component of a wherein embodiment of the invention in the step S304 of Fig. 2
Diagrammatic cross-section.
Fig. 3 E is part of the groove type power semiconductor component of a wherein embodiment of the invention in the step S305 of Fig. 2
Diagrammatic cross-section.
Fig. 3 F is part of the groove type power semiconductor component of a wherein embodiment of the invention in the step S308 of Fig. 2
Diagrammatic cross-section.
Fig. 3 G is the partial cutaway schematic of the wherein groove type power semiconductor component of an embodiment of the invention.
Fig. 4 A is partial cutaway of the groove type power semiconductor component of another embodiment of the present invention in the step S306 of Fig. 2
Face schematic diagram.
Fig. 4 B is partial cutaway of the groove type power semiconductor component of another embodiment of the present invention in the step S307 of Fig. 2
Face schematic diagram.
Fig. 4 C is partial cutaway of the groove type power semiconductor component of another embodiment of the present invention in the step S308 of Fig. 2
Face schematic diagram.
Fig. 4 D is the partial cutaway schematic of the groove type power semiconductor component of another embodiment of the present invention.
Accompanying drawings symbol description:
Existing trench power metal-oxide semiconductor field-effect transistor T
Grid 10
Cover electrode (maskingelectrode) 11
Interpolar dielectric layer 12
Groove h1
Side wall surface s1, s2
Wedge angle 101,102
Groove type power semiconductor component T1, T2
Trench gate structure G1, G2
Substrate 20
Epitaxial layer 21
Drift region 210
Matrix area 211
Source area 212
Element groove 21h
Laminated construction 22
Outer insulation 220
Upper inner wall 220a
Lower inner wall 220b
Intermediate dielectric layer 221
Upper dielectric layer 221b
Interlayer 221a
Semiconductor material layer 222 '
Initial inner-dielectric-ayer 223 '
Heavily-doped semiconductor material 23 '
Inner-dielectric-ayer 223
Semiconductor material layer upper half 222a
Thermal oxide layer 24
Sidewall portion 240
Isolation part 241
Semiconductor layer 222
Cover electrode (maskingelectrode) 23
Interpolar dielectric layer 25
Grid 26
Cover lamination M1, M2
First segment difference structure S1
Second segment difference structure S2
Interior side insulation layer 27
Accommodating space H1
Process step S100~S400, S301~S308
Specific embodiment
It is to illustrate presently disclosed related " groove type power semiconductor component by particular specific embodiment below
And its manufacturing method " embodiment, those skilled in the art can be understood of the invention excellent by content disclosed in this specification
Point and effect.The present invention can be implemented or be applied by other different specific embodiments, the various details in this specification
It may be based on different viewpoints and application, carry out various modifications and change in the case where not departing from design of the invention.In addition, of the invention
Attached drawing is only simple schematically illustrate, not according to the description of actual size, states in advance.The following embodiments and the accompanying drawings will be further detailed
Illustrate the relevant technologies content of the invention, but the protection scope that disclosure of that is not intended to limit the invention.
It should be understood that although various elements or signal may be described using term first, second, third, etc. herein,
But these elements or signal should not be limited by these terms.These terms are mainly to distinguish an element and another member
Part or a signal and another signal.In addition, term "or" used herein, should may include correlation depending on actual conditions
Connection lists any of project or multiple combinations.
Firstly, the manufacturing method of groove type power semiconductor component provided by the present invention will be described in detail embodiment.It please join
Read Fig. 2, Fig. 3 A to Fig. 3 F.Fig. 2 is the stream of the wherein manufacturing method of the groove type power semiconductor component of an embodiment of the invention
Cheng Tu.Fig. 3 A to Fig. 3 F shows each step of the groove type power semiconductor component in Fig. 2 of a wherein embodiment of the invention respectively
In partial cutaway schematic.
Referring to figure 2., in the step s 100, an epitaxial layer is formed on a substrate.Then, in step s 200, formed
One element groove is in epitaxial layer.Then, in step S300, a trench gate structure is formed in element groove.
Please also refer to the step S301 to S306 and Fig. 3 A to Fig. 3 F in Fig. 2, further explanation forms trench-gate knot
The detailed step of structure.
In step S301, the inner wall of a laminated construction cladding element groove is formed, wherein laminated construction includes at least
The initial inner-dielectric-ayer of semiconductor material layer and a covering semiconductor material layer.In figure 3 a, the step of Fig. 2 is first completed
Rapid S100, S200 and S301.As shown in Figure 3A, epitaxial layer 21 is located on a substrate 20, has been initially formed one in epitaxial layer 21
Element groove 21h, and the inner wall of 22 cladding element groove 21h of laminated construction.
Specifically, substrate 20 have high concentration the first type conductive impurities, using as groove power semiconductor member
The drain region (drain) of part.First type conductive impurities above-mentioned can be N-type or P-type conductivity impurity.Assuming that substrate 20 is
Silicon substrate, N-type conductivity impurity is pentad ion, such as phosphonium ion or arsenic ion, and P-type conductivity impurity is trivalent member
Plain ion, such as boron ion, aluminium ion or gallium ion.
Epitaxial layer 21 (epitaxial layer) has and the identical conductivity type of substrate 20, but the doping of epitaxial layer 21 is dense
Degree is lower than the doping concentration of substrate 20.By taking NMOS transistor as an example, substrate 20 has the n-type doping (N of high concentration+), and epitaxy
N-type doping (N of the layer 21 with low concentration-).By taking PMOS transistor as an example, substrate 20 and epitaxial layer 21 are then respectively provided with high concentration
P-type adulterate (P+Doping) and the p-type of low concentration adulterates (P-doping)。
In addition, the step of forming element groove 21h can apply any of technological means.For example, it is initially formed
It patterns photoresist (non-icon), to define the position of element groove 21h, however the present invention is not illustrated with this and is limited.Then,
Opening is formed by patterning photoresist, further by etching process, such as: dry ecthing or wet etching, in epitaxial layer 21
Form element groove 21h.
In embodiments of the present invention, laminated construction 22 includes outer insulation 220, intermediate dielectric layer 221, semiconductor material
Layer 222 ' and initial inner-dielectric-ayer 223 '.Specifically, outer insulation 220, intermediate dielectric layer 221, semiconductor material layer
222 ' and initial inner-dielectric-ayer 223 ' can be sequentially formed on the inner wall of element groove 21h and cover the table of epitaxial layer 21
Face.That is, intermediate dielectric layer 221 and semiconductor material layer 222 ' are located at outer insulation 220 and initial inner-dielectric-ayer
Between 223 ', and semiconductor material layer 222 ' is between intermediate dielectric layer 221 and initial inner-dielectric-ayer 223 '.
In the present embodiment, the material of outer insulation 220 is different with the material of intermediate dielectric layer 221.In an embodiment
In, outer insulation 220 is oxide skin(coating), such as: silica, and intermediate dielectric layer 221 is nitride layer, such as: silicon nitride.It is intermediate
The material of dielectric layer 221 is different from the material of outer insulation 220, can protect outer insulation in subsequent etching process
220 are not etched.
It should be noted that can be initially formed semiconductor material layer 222 ' after forming intermediate dielectric layer 221 and be covered in centre
On dielectric layer 221, initial inner-dielectric-ayer 223 ' is re-formed.In one embodiment, semiconductor material layer 222 ' can be an essence
Semiconductor layer, that is, an insulating layer.But in another embodiment, it is doped that semiconductor material layer 222 ' is also possible to one
Semiconductor layer.For example, semiconductor material layer 222 ' can be the polysilicon material for being doped N-type impurity or p type impurity
The bed of material, and it is conductive, however the present invention is not illustrated with this and is limited.In addition, the thickness of semiconductor material layer 222 ' can be with
More Bao Yuehao.
The material of initial inner-dielectric-ayer 223 ' is identical as the material of outer insulation 220, and can all be oxide skin(coating).At this
In embodiment, the thickness of initial inner-dielectric-ayer 223 ' can be thicker than the thickness of semiconductor material layer 222 ', but initial inner-dielectric-ayer
223 ' can still define a space in element groove 21h, without filling up element groove 21h.
Please continue to refer to Fig. 2 and Fig. 3 B.Fig. 3 B is the groove type power semiconductor component of a wherein embodiment of the invention
Partial cutaway schematic in the step S302 of Fig. 2.In step s 302, a heavily-doped semiconductor material is formed in element ditch
The lower half of slot.As shown in Figure 3B, heavily-doped semiconductor material 23 ' is formed in space defined in initial inner-dielectric-ayer 223 '
It is interior, and it is located at the lower half of element groove 21h.
In one embodiment, be first code-pattern (blanketly) form a heavily doped semiconductor layer on epitaxial layer 21,
And it inserts in element groove 21h.Then, the heavy doping covered on eatch-back (etch back) removal 21 surface of epitaxial layer is partly led
Body layer, and leave the heavily-doped semiconductor material 23 ' positioned at the lower half element groove 21h.Heavily-doped semiconductor material 23 ' is for example
It is the polysilicon structure (doped poly-Si) containing conductive impurities.It in one embodiment, is by adulterating chemical gaseous phase inside
Deposition manufacture process (in-situ doping CVD process) forms heavily doped semiconductor layer.
Please continue to refer to Fig. 2.In step S303, removal a part is located at the initial interior dielectric of the upper half of element groove
Layer, to expose a upper half of semiconductor material layer and the top of heavily-doped semiconductor material.
Cooperation is referring to Fig. 3 C.Fig. 3 C is step of the groove type power semiconductor component in Fig. 2 of a wherein embodiment of the invention
Partial cutaway schematic in rapid S303.It is located at the initial inner-dielectric-ayer 223 ' of the upper half element groove 21h in removal a part
Later, the inner-dielectric-ayer 223 for being located at the lower half element groove 21h, and a upper half 222a of semiconductor material layer 222 ' are formed
And the top of heavily-doped semiconductor material 23 ' can be exposed.In other words, the top meeting of heavily-doped semiconductor material 23 '
Protrude from the top surface of inner-dielectric-ayer 223.
Then, in the step S304 of Fig. 2, with the top and half of thermal oxidation oxidation heavily-doped semiconductor material
The upper half of conductor material layer, to form a thermal oxide layer.Please cooperate referring to Fig. 3 D, Fig. 3 D is a present invention wherein embodiment
Partial cutaway schematic of the groove type power semiconductor component in the step S304 of Fig. 2.
As shown in Figure 3D, after executing thermal oxidation, the upper half 222a of semiconductor material layer 222 ' and heavily doped
The top of miscellaneous semiconductor material 23 ' is all oxidized, and forms thermal oxide layer 24.It should be noted that being located at element groove 21h lower half
The semiconductor material layer 222 ' in portion is covered and not oxidized by inner-dielectric-ayer 223.That is, not oxidized semiconductor material
Layer 222 ' forms semi-conductor layer 222.In addition, not oxidized heavily-doped semiconductor material 23 ' forms cover electrode (maskingelectrode) 23.According to
This, semiconductor layer 222 can be between intermediate dielectric layer 221 and cover electrode (maskingelectrode) 23.
As shown in Figure 3D, thermal oxide layer 24 include two opposite sidewall portions 240 and one be connected to two side walls portion 240 it
Between isolation part 241.The depth direction that two side walls portion 240 is generally parallel to element groove 21h is covered on intermediate dielectric layer
221 upper half, and isolation part 241 is then formed on cover electrode (maskingelectrode) 23 and semiconductor layer 222.In the present embodiment, completely cut off
The thickness in portion 241 is greater than the thickness of sidewall portion 240.
It should be noted that in the present embodiment, when executing thermal oxidation process, if being the absence of the guarantor of intermediate dielectric layer 221
Shield, may make the silicon in epitaxial layer 21 diffuse out and continue to be oxidized, and keep 240 thickness of sidewall portion of thermal oxide layer 24 big
In isolation part 241.Therefore, in the present embodiment, intermediate dielectric layer 221 is covered on outer insulation 220 and epitaxial layer 21,
Can be further oxided to avoid epitaxial layer 21, and control thermal oxide layer 24 sidewall portion 240 thickness within a preset range.
Then, in the step S305 in Fig. 2, sidewall portion and partial isolation part are removed, to form interpolar dielectric layer.
E referring to figure 3., Fig. 3 E are the groove type power semiconductor component of a wherein embodiment of the invention in the step S305 of Fig. 2
Partial cutaway schematic.
As shown in FIGURE 3 E, the sidewall portion 240 of thermal oxide layer 24 can be completely removed.Since the thickness of isolation part 241 is greater than
The thickness of sidewall portion 240, therefore when removing sidewall portion 240, isolation part 241 will not be completely removed.In the present embodiment, exist
Remove sidewall portion 240 after, the thickness of isolation part 241 still can be greater than 70nm, using as be used to completely cut off cover electrode (maskingelectrode) 23 and grid
26 interpolar dielectric layer 25.
In addition, if semiconductor material layer 222 ' with a thickness of 10nm, the thickness of sidewall portion 240 can be about 22.7nm,
However the present invention is not illustrated with this and is limited.It therefore, can be by the thickness of control semiconductor material layer 222 ', to limit thermal oxide
The thickness of sidewall portion 240 is formed by after processing.
In addition, interpolar dielectric layer 25 and intermediate dielectric layer 221 exist after the sidewall portion 240 of removal thermal oxide layer 24
The upper half of element groove 21h defines an accommodating space H1.
Then, referring to figure 2., in one embodiment, after executing step S305, step can directly be executed
S308.In another embodiment, step S306, step S307 first can also sequentially be executed and then execute step S308.
In the present embodiment, after executing step S305, directly execution step S308.In step S308, grid are formed
Pole is in the upper half of element groove.
F referring to figure 3., Fig. 3 F are the groove type power semiconductor component of a present invention wherein embodiment Fig. 2 the step of
Partial cutaway schematic in S308.As illustrated in Figure 3 F, grid 26 is formed in accommodating space H1, and grid 26 is situated between by interpolar
Electric layer 25 and cover electrode (maskingelectrode) 23 insulate.In one embodiment, the material of grid 26 is the polysilicon of heavy doping.
In the step of forming grid 26, can first it be inserted on epitaxial layer 21 and in accommodating space H1 blanket-like
Heavily doped polysilicon material, then it is etched back the heavily doped polysilicon material that removal is located on epitaxial layer 21, and form grid 26.Via
Above-mentioned steps S301~S305, S308 can form trench gate structure G1 in element groove 21h.
It is worth noting that, being to make heavy doping half in the step of forming interpolar dielectric layer 25 in embodiments of the present invention
The top of conductor material 23 ' and the upper half 222a oxidation of semiconductor material layer 222 ', to form thermal oxide layer 24.Later,
Interpolar dielectric layer 25 is formed by etching the sidewall portion 240 of thermal oxide layer 24 again.That is, in the embodiment of the present invention, it can
To define the top surface profile of interpolar dielectric layer 25 in the step of etching thermal oxide layer 24, and avoid the top of interpolar dielectric layer 25
Face has depressed area.
Different from the interpolar dielectric layer 12 (such as Fig. 1) of the prior art, the top surface of the interpolar dielectric layer 25 of the embodiment of the present invention
There will not be depressed area.Accordingly, it after forming grid 26, also can avoid forming wedge angle in the bottom of grid 26, and reduce member
The pressure resistance and reliability of part.
In addition, in the present embodiment, intermediate dielectric layer 221 covers the entire inner wall of outer insulation 220.Accordingly, exist
It is formed after grid 26, grid 26 can be by intermediate dielectric layer 221 and outer insulation 220 to be isolated with epitaxial layer 21.Specifically
For, two opposite sides of grid 26 can be connected to intermediate dielectric layer 221.
Furthermore, intermediate dielectric layer 221 can substantially be divided into top Jie positioned at the upper half element groove 21h
Electric layer 221b and interlayer 221a positioned at the lower half element groove 21h.
In the present embodiment, upper dielectric layer 221b and a part of outer insulation 220 can be collectively as gate insulation layers.Separately
Outside, a masking lamination M1 is collectively formed in interlayer 221a, semiconductor layer 222 and inner-dielectric-ayer 223.
Then, referring again to Fig. 2, in step S400, a matrix area and source region are formed in epitaxial layer.It please join
According to Fig. 3 G, the part section that the manufacturing method of a display embodiment through the invention is formed by trench semiconductor element shows
It is intended to.
Specifically, it is that a body dopant processing procedure first is executed to epitaxial layer 21, is lightly doped with forming one in epitaxial layer 21
Area, and lightly doped district has and the opposite conductivity type of epitaxial layer 21.Then, a source dopant processing procedure is executed to lightly doped district, with
A heavily doped region is formed in the upper half of lightly doped district, and the conductivity type of heavily doped region is opposite with the conductivity type of lightly doped district.It connects
, it executes a heat and becomes into (drive-in) processing procedure, so that the impurity diffusion in lightly doped district and heavily doped region, and form matrix
Area 211 and source area 212, wherein source area 212 is positioned at the top of matrix area 211.Forming matrix area 211 and source area
After 212, a drift region 210 (drift region) can be defined in epitaxial layer 21.
Then, route redistribution layer can be continuously formed on epitaxial layer 21, so that source area 212, grid 26 and masking electricity
Pole 23 can be electrically connected to external control circuit.Any of technology can be used in the technological means for forming route redistribution layer
Means realize that this will not be repeated here.
As shown in Figure 3 G, being formed by groove type power semiconductor component T1 via the step of Fig. 2 includes substrate 20, epitaxy
21 and trench gate structure G1 of layer, wherein epitaxial layer 21 is set on substrate 20, and has an at least element groove 21h, ditch
Slot gate structure G1 is located in element groove 21h.Specifically, trench gate structure G1 includes outer insulation 220, masking electricity
Pole 23, grid 26, interpolar dielectric layer 25 and masking lamination M1.
The inner wall of 220 cladding element groove 21h of outer insulation, and have with the inner wall of element groove 21h substantially
The profile being consistent.In embodiments of the present invention, it is the horizontal plane shown greatly where the lower edge of matrix area 211, outside is insulated
The inner wall of layer 220 divides on one inner wall 220a and once inner wall 220b.
Cover electrode (maskingelectrode) 23 and masking lamination M1 are co-located at the lower half of element groove 21h.In the present embodiment, masking is folded
The lower inner wall 220b of layer M1 covering outer insulation 220, and surround cover electrode (maskingelectrode) 23.In the present embodiment, lamination M1 is covered
Including at least interlayer 221a, semiconductor layer 222 and inner-dielectric-ayer 223.
It should be noted that semiconductor layer 222 is separated from each other by inner-dielectric-ayer 223 and cover electrode (maskingelectrode) 23, and semiconductor layer
222 between inner-dielectric-ayer 223 and interlayer 221a.When semiconductor layer 222 is extrinsic semiconductor's layer, an insulation can be done
Layer.In addition, in the present embodiment, semiconductor layer 222 is suspension joint.Even if semiconductor layer 222 is doped semiconductor layer, whether
Heavily doped semiconductor layer or semiconductor layer is lightly doped, the electrical performance of groove type power semiconductor component T1 will not be influenced.
Please continue to refer to Fig. 2.In an alternative embodiment of the invention, after executing step S305, step also can be performed
S306.In step S306, the intermediate dielectric layer of a part is removed, and retains intermediate dielectric layer and is located at element groove lower half
One interlayer.
A referring to figure 4., Fig. 4 A are the groove type power semiconductor component of another embodiment of the present invention Fig. 2 the step of
Partial cutaway schematic in S306.Fig. 4 A can connect Fig. 3 E in previous embodiment.
As shown in Figure 4 A, the upper dielectric layer 221b of intermediate dielectric layer 221 can be removed, and be left positioned at element groove
The interlayer 221a of the lower half 21h.In the present embodiment, the material of intermediate dielectric layer 221 is different with the material of interpolar dielectric layer 25,
Also different with the material of outer insulation 220.Therefore, the upper dielectric layer 221b of intermediate dielectric layer 221 can pass through selectivity
Etching is to remove.
It is that cover power is used as by interpolar dielectric layer 25 and outer insulation 220, to remove in selective etch processing procedure
The upper dielectric layer 221b of intermediate dielectric layer 221, but interlayer 221a is by interpolar dielectric layer 25 and outer insulation 220
It blocks and can be retained.
Please continue to refer to Fig. 4 A, after completing the aforementioned steps, two opposite end faces of semiconductor layer 222 can be corresponded respectively to
Two opposite end faces of interlayer 221a and form two segment difference structures.Furthermore, a wherein end face for semiconductor layer 222 and folder
One first segment difference structure S1, and the other end face of semiconductor layer 222 and interlayer are formed between a wherein end face of layer 221a
One second segment difference structure S2 is formed between the other end face of 221a.In addition, interpolar dielectric layer 25 can be from it can be seen from Fig. 4 A
First segment difference structure S1 extends to the second segment difference structure S2.That is, two opposite side surfaces of interpolar dielectric layer 25 can be distinguished
Connect the first segment difference structure S1 and the second segment difference structure S2.
Then, referring to figure 2., in step S307, form in one that side insulation layer is in element groove, absolutely with covering outside
Edge layer.It please cooperate referring to Fig. 4 B, Fig. 4 B is the groove type power semiconductor component of another embodiment of the present invention Fig. 2 the step of
Partial cutaway schematic in S308.
As shown in Figure 4 B, another interior side insulation layer 27 is formed in element groove 21h, and covers outer insulation 220
Upper inner wall, the top surface of interlayer 221a and interpolar dielectric layer 25.The material of interior side insulation layer 27 and the material of outer insulation 220
Material is not necessarily identical, and can be formed by any of film forming processing procedure, such as: the either chemical gas of physical vapour deposition (PVD)
Mutually deposit.For example, the material of interior side insulation layer 27 and the material of outer insulation 220 are all oxide (such as: silica),
And interior side insulation layer 27 can be formed by another thermal oxidation, however the present invention is not illustrated with this and is limited.
Please continue to refer to Fig. 4 C and Fig. 4 D.As shown in Figure 4 C, it after executing step S306 to step S308, is formed another
The channel grid structure G2 of one embodiment.Then, as shown in Figure 4 D, after executing the step S400 in Fig. 2, this hair is formed
The groove type power semiconductor component T2 of bright another embodiment.
In the groove type power semiconductor component T2 of the present embodiment, grid 26 is by outer insulation 220 and inside
Insulating layer 27 with epitaxial layer 21 to be isolated.That is, the outer insulation 220 and interior side insulation layer 27 of the present embodiment can be common
As gate insulation layer.The interior meeting of side insulation layer 27 connection interlayer 221a, and a part of interior side insulation layer 27 can cover interpolar dielectric
Layer 25.
A to Fig. 4 C referring to figure 4..Significantly, since after removing upper dielectric layer 221b, interlayer 221a's
Difference in height is generated between the top surface meeting of being possible to and the top surface of interpolar dielectric layer 25, to form two recesses, as shown in Figure 4 A.Such as
This, the bottom that may result in grid 26 has wedge angle.Therefore, in figure 4b, interior side insulation layer 27 can insert interlayer 221a
Top surface and interpolar dielectric layer 25 top surface between recess in.In this way, can avoid making 26 bottom of grid after forming grid 26
Portion has wedge angle, and reduces the reliability of groove type power semiconductor component T2.
It should be noted that in other embodiments, if the thickness of outer insulation 220 is thicker, and can avoid in interlayer
Recess is formed between the top surface of 221a and the top surface of interpolar dielectric layer 25, can also directly be executed after executing step S306
Step S308.Accordingly, step S307 can also be omitted.
A wherein beneficial effect of the invention is, groove type power semiconductor component provided by the present invention and its production
Method, can by " before forming interpolar dielectric layer, formed 22 cladding element groove 21h of a laminated construction inner wall ", "
Laminated construction 22 includes at least the initial inner-dielectric-ayer of semiconductor material layer 222 ' and a covering semiconductor material layer 222 '
223 ' ", " formed a heavily-doped semiconductor material 23 ' in the lower half of element groove 21h " and " removal a part is located at element
The initial inner-dielectric-ayer 223 ' of the upper half of groove 21h, with expose semiconductor material layer 222 ' a upper half 222a and
The technical solution at the top of heavily-doped semiconductor material 23 ' " can avoid pole in the step of being subsequently formed interpolar dielectric layer 25
Between dielectric layer 25 top surface generate depressed area, thus avoid 26 bottom of grid have wedge angle.In this way, the embodiment of the present invention is provided
Groove type power semiconductor component manufacturing method manufactured by groove type power semiconductor component T1, T2 can be with higher
Grid pressure resistance and higher reliability (reliability).
In addition, groove type power semiconductor component T1, T2 manufactured by manufacturing method through the embodiment of the present invention, can exist
The lower half of trench gate structure G1, G2 form the semiconductor layer 222 for surrounding cover electrode (maskingelectrode) 23.
Content disclosed above is only preferable possible embodiments of the invention, not thereby limits to right of the invention and wants
The protection scope asked, so all equivalence techniques variations done with description of the invention and schema content, are both contained in this
In the scope of protection of the claims of invention.
Claims (16)
1. a kind of groove type power semiconductor component, which is characterized in that the groove type power semiconductor component includes:
One substrate；
One epitaxial layer is set on the substrate, and there is an at least element groove to be formed in the epitaxial layer；
One trench gate structure is located at least one element groove, and the trench gate structure includes:
One outer insulation covers an inner wall of the element groove；
One cover electrode (maskingelectrode) is set to the lower half of at least one element groove；
One grid is set in the cover electrode (maskingelectrode), and is electrically insulated from the cover electrode (maskingelectrode)；And
One masking lamination, covers the inner wall once of the outer insulation, the masking lamination including at least one with it is described
The semiconductor layer that cover electrode (maskingelectrode) is separated from each other, and the semiconductor layer is between the lower inner wall and the cover electrode (maskingelectrode).
2. groove type power semiconductor component as described in claim 1, which is characterized in that the semiconductor layer is an essence half
Conductor layer or once doping semiconductor layer.
3. groove type power semiconductor component as described in claim 1, which is characterized in that the masking lamination further includes a folder
Layer, and the interlayer is between the outer insulation and the semiconductor layer.
4. groove type power semiconductor component as claimed in claim 3, which is characterized in that two opposite ends of the semiconductor layer
Face forms two segment difference structures between two opposite end faces of the interlayer respectively.
5. groove type power semiconductor component as claimed in claim 4, which is characterized in that the trench gate structure further includes
One interpolar dielectric layer, the interpolar dielectric layer between the cover electrode (maskingelectrode) and the grid, the interpolar dielectric layer and every
Two opposite side surfaces from the semiconductor layer and the grid, and the interpolar dielectric layer are separately connected two segment difference knots
Structure.
6. groove type power semiconductor component as claimed in claim 3, which is characterized in that the trench gate structure is also into one
Step includes side insulation layer in one, covers inner wall on the one of the outer insulation, and the interior side insulation layer connects the interlayer,
And the grid by the interior side insulation layer and the outer insulation to be isolated with the epitaxial layer.
7. groove type power semiconductor component as claimed in claim 6, which is characterized in that the material of the interior side insulation layer with
The interlayer is different, and a part of the interior side insulation layer covers the interpolar dielectric layer.
8. groove type power semiconductor component as claimed in claim 3, which is characterized in that the trench gate structure is also into one
Step includes the upper dielectric layer of inner wall on the one of a covering outer insulation, the material of the upper dielectric layer and described
Interlayer is identical, and the upper dielectric layer connects the interlayer to form an intermediate dielectric layer.
9. groove type power semiconductor component as described in claim 1, which is characterized in that the masking lamination further includes in one
Dielectric layer, and the inner-dielectric-ayer is between the cover electrode (maskingelectrode) and the semiconductor layer.
10. a kind of manufacturing method of groove type power semiconductor component, which is characterized in that the groove type power semiconductor component
Manufacturing method include:
An epitaxial layer is formed on a substrate；
An element groove is formed in the epitaxial layer；And
A trench gate structure is formed in the element groove, there is the trench gate structure cover electrode (maskingelectrode), one to be located at
Grid and an interpolar dielectric layer between the cover electrode (maskingelectrode) and the grid above the cover electrode (maskingelectrode), wherein
Before forming the interpolar dielectric layer, the step of forming the trench gate structure, is included at least:
Form the inner wall that a laminated construction covers the element groove, wherein the laminated construction is led including at least half
The initial inner-dielectric-ayer of body material layer and a covering semiconductor material layer；
A heavily-doped semiconductor material is formed in the lower half of the element groove；And
Removal a part is located at the initial inner-dielectric-ayer of the upper half of the element groove, to expose the semiconductor material
One upper half of the bed of material and the top of the heavily-doped semiconductor material.
11. the manufacturing method of groove type power semiconductor component as claimed in claim 10, which is characterized in that form the ditch
The step of slot gate structure, may further comprise:
With a thermal oxidation aoxidize the heavily-doped semiconductor material top and the semiconductor material layer it is described on
Half portion, to form a thermal oxide layer, wherein the not oxidized semiconductor material layer forms semi-conductor layer, not oxidized
The heavily-doped semiconductor material form the cover electrode (maskingelectrode), the thermal oxide layer include side wall portion and one be located at it is described
Isolation part in cover electrode (maskingelectrode), and the thickness of the isolation part is greater than the thickness of the sidewall portion；
The sidewall portion and the partial isolation part are removed, to form the interpolar dielectric layer；And form the grid
In the upper half of the element groove.
12. the manufacturing method of groove type power semiconductor component as claimed in claim 11, which is characterized in that laminated construction is also
Including an outer insulation and an intermediate dielectric layer, the intermediate dielectric layer and the semiconductor material layer are located at the outside
Between insulating layer and the initial inner-dielectric-ayer.
13. the manufacturing method of groove type power semiconductor component as claimed in claim 12, which is characterized in that described in formation
After the step of grid, two opposite sides of the grid connect the intermediate dielectric layer.
14. the manufacturing method of groove type power semiconductor component as claimed in claim 12, which is characterized in that described in formation
Before the step of grid, the step of forming the trench gate structure, be may further comprise:
After removing the sidewall portion and the partial isolation part, the intermediate dielectric layer of a part is removed, and is protected
The intermediate dielectric layer is stayed to be located at an interlayer of element groove lower half, wherein two opposite end faces of the semiconductor layer are distinguished
Two segment difference structures are formed between two opposite end faces of the interlayer；And
Form in one that side insulation layer is in the element groove, to cover the outer insulation.
15. the manufacturing method of groove type power semiconductor component as claimed in claim 10, which is characterized in that described in formation
In the step of laminated construction, the semiconductor material layer be an extrinsic semiconductor layer or once doping semiconductor layer.
16. the manufacturing method of groove type power semiconductor component as claimed in claim 10, which is characterized in that the groove
The manufacturing method of formula power semiconductor may further comprise: after the step of forming the trench gate structure, be formed
One matrix area and source region are in the epitaxial layer.
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| CN112802895A (en) * | 2021-01-06 | 2021-05-14 | 江苏东海半导体科技有限公司 | Manufacturing method of low-capacitance split-gate trench IGBT device intermediate isolation oxide layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100117144A1 (en) * | 2008-11-10 | 2010-05-13 | Infineon Technologies Austria Ag | Semiconductor device and method for the production of a semiconductor device |
| US20150263166A1 (en) * | 2012-02-24 | 2015-09-17 | Semiconductor Components Industries, Llc | Electronic device including a trench and a conductive structure therein |
| CN106856665A (en) * | 2015-02-20 | 2017-06-16 | 新电元工业株式会社 | Semiconductor device |
-
2017
- 2017-09-29 CN CN201710908789.4A patent/CN109585547B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100117144A1 (en) * | 2008-11-10 | 2010-05-13 | Infineon Technologies Austria Ag | Semiconductor device and method for the production of a semiconductor device |
| US20150263166A1 (en) * | 2012-02-24 | 2015-09-17 | Semiconductor Components Industries, Llc | Electronic device including a trench and a conductive structure therein |
| CN106856665A (en) * | 2015-02-20 | 2017-06-16 | 新电元工业株式会社 | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112802895A (en) * | 2021-01-06 | 2021-05-14 | 江苏东海半导体科技有限公司 | Manufacturing method of low-capacitance split-gate trench IGBT device intermediate isolation oxide layer |
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