CN109585299B - Method for reducing fin loss in FinFET side wall etching - Google Patents
Method for reducing fin loss in FinFET side wall etching Download PDFInfo
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- CN109585299B CN109585299B CN201811374804.2A CN201811374804A CN109585299B CN 109585299 B CN109585299 B CN 109585299B CN 201811374804 A CN201811374804 A CN 201811374804A CN 109585299 B CN109585299 B CN 109585299B
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 238000005530 etching Methods 0.000 title claims abstract description 40
- 239000000463 material Substances 0.000 claims abstract description 57
- 239000011241 protective layer Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 238000001312 dry etching Methods 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 239000007789 gas Substances 0.000 claims description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000005049 silicon tetrachloride Substances 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 5
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
Abstract
The invention discloses a method for reducing fin loss in FinFET side wall etching, which comprises the following steps: step S01: providing a semiconductor substrate, and forming a fin part and a grid electrode of a FinFET on the semiconductor substrate; step S02: depositing a side wall material, and covering the fin part and the grid electrode; step S03: performing first dry etching on the side wall material for depositing a protective layer, and forming a protective layer at least on the top surface of the fin part; step S04: continuing to perform second dry etching on the side wall material for the purpose of etching removal, and removing the side wall material on the side wall of the fin part; step S05: and circularly repeating the step S03 and the step S04 until the side wall materials on the side walls of the fin parts are completely removed. The invention is compatible with the conventional silicon-based ultra-large scale integrated circuit manufacturing technology, has the characteristics of simplicity, convenience and short period, and reduces the process cost.
Description
Technical Field
The invention relates to the technical field of integrated circuit process manufacturing, in particular to a method for reducing fin loss in FinFET side wall etching.
Background
With the continuous development of semiconductor technology, it is difficult for conventional planar devices to meet the requirements of people for high-performance devices.
Referring to fig. 1, fig. 1 is a schematic perspective view of a conventional finfet. As shown in fig. 1, the fin field effect transistor (FinFET) structure includes: the semiconductor substrate 10 is positioned at the bottom layer, a raised fin part 14 is formed on the semiconductor substrate 10, and the fin part 14 is generally obtained by etching the semiconductor substrate 10; the dielectric layer 11 covers the surface of the semiconductor 10 and a part of the side wall of the fin portion 14; the gate structure 12 crosses the top and the side wall of the fin portion 14, and the gate structure 12 includes a gate dielectric layer and a gate electrode on the gate dielectric layer. For more description of finfet, refer to US patent publication No. US7868380B 2.
When the sidewall etching is performed on the existing Fin field effect transistor, the sidewall material on the side surface of the Fin (Fin) needs to be removed while the sidewall of the gate is kept. However, for such etching with aspect ratio exceeding 10, over-etching of more than 500% is required, and such a process will result in silicon loss (loss greater than 5nm) from the Fin surface.
In the prior art, the sidewall is etched by applying a bias voltage to the low-energy ion etching. The process can remove the side wall of the clean Fin side surface while reducing the loss of silicon on the Fin surface; however, this process also has significant loss of gate sidewalls and also introduces some other problems.
Therefore, it is desirable to find a new method for reducing fin loss in etching of FinFET sidewalls to eliminate the disadvantages of the prior art.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a method for reducing fin loss in etching of FinFET side walls.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a method for reducing fin loss in etching of FinFET side walls comprises the following steps:
step S01: providing a semiconductor substrate, and forming a fin part and a grid electrode of a FinFET on the semiconductor substrate;
step S02: depositing a side wall material, and covering the fin part and the grid electrode;
step S03: performing first dry etching on the side wall material for depositing a protective layer, and forming a protective layer at least on the top surface of the fin part;
step S04: continuing to perform second dry etching on the side wall material for the purpose of etching removal, and removing the side wall material on the side wall of the fin part;
step S05: and repeating the steps S03 and S04 in a circulating manner until the side wall materials on the side walls of the fins are removed completely.
Further, the protective layer is used as a sacrificial layer when the side wall material is removed through etching.
Further, the material of the protective layer is the same as that of the side wall.
Further, in step S02, a layer of sidewall material with uniform thickness is formed on the fin and the gate by chemical vapor deposition.
Further, in step S03, when the first dry etching is performed, the protective layer is formed by using a product of the reaction of the etching gas to be deposited on the top surface of the fin portion and the top surface of the gate.
And further, the side wall is made of silicon dioxide, when the first dry etching is carried out, silicon tetrachloride and oxygen are used as etching gases, the bias voltage is closed, and silicon dioxide generated by the reaction of the silicon tetrachloride and the oxygen is accumulated on the top surfaces of the fin part and the grid to form the protective layer.
Further, in step S04, when the second dry etching is performed, the protective layer is used as a sacrificial layer, and the sidewall materials on the gate sidewall and the fin sidewall are removed while the protective layer on the top surface is consumed.
Furthermore, the material of the protective layer is the same as that of the side wall, when the second dry etching is performed, the gas containing F and the inert gas are used as etching gases, bias voltage is started, and the generated bombardment effect is utilized to synchronously remove the side wall materials of the fin part side wall and the grid electrode side wall while consuming the protective layer.
Further, the semiconductor substrate material is monocrystalline silicon, polycrystalline silicon or amorphous silicon; or the semiconductor substrate material is silicon, germanium, gallium arsenide or a silicon-germanium compound; or, the semiconductor substrate has an epitaxial layer; or, the semiconductor substrate is a silicon-on-insulator substrate.
Furthermore, the fin portion is monocrystalline silicon doped with N-type or P-type impurities.
The invention is compatible with the conventional silicon-based ultra-large scale integrated circuit manufacturing technology, has the characteristics of simplicity, convenience and short period, and reduces the process cost.
Drawings
Fig. 1 is a schematic perspective view of a conventional finfet.
Fig. 2 is a flow chart illustrating a method for reducing fin loss during etching of a FinFET sidewall according to a preferred embodiment of the present invention.
Fig. 3-7 are schematic diagrams of process steps for implementing the method of fig. 2 in a preferred embodiment of the invention.
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following description of the present invention, please refer to fig. 2, fig. 2 is a flow chart illustrating a method for reducing fin loss in etching a FinFET sidewall spacer according to a preferred embodiment of the present invention; referring to fig. 3-7, fig. 3-7 are schematic process steps of a method for reducing fin silicon loss during etching of a FinFET sidewall according to the method of fig. 2. As shown in fig. 2, a method for reducing fin loss in etching of a FinFET sidewall spacer according to the present invention may include the following steps:
step S01: a semiconductor substrate is provided, and a fin portion and a gate of a FinFET are formed on the semiconductor substrate.
Please refer to fig. 3. The semiconductor substrate used in the present invention may be single crystalline silicon, polycrystalline silicon, or amorphous silicon; the semiconductor substrate may also be silicon, germanium, gallium arsenide, or a silicon germanium compound; the semiconductor substrate may also have an epitaxial layer or a silicon-on-insulator substrate (SOI substrate); the semiconductor substrate may also be other semiconductor materials, and is not described in detail herein.
In this embodiment, a silicon substrate 100 is used as an example. The Fin (Fin)200 and Gate (Gate)300 of the FinFET may be formed on the silicon substrate 100 using standard process steps for forming FinFET devices. The formed fin portion 200 may be a monocrystalline silicon doped with N-type or P-type impurities; the gate material may be a metal material or polysilicon, or other suitable gate material.
Step S02: and depositing a side wall material to cover the fin part and the grid electrode.
Please refer to fig. 4. Specifically, a sidewall material 400 is deposited globally over the silicon substrate 100. In this embodiment, a layer of sidewall material 400 with uniform thickness may be formed by chemical vapor deposition or the like; the material of the side wall may preferably be silicon nitride or silicon dioxide. The thickness of the sidewall material 400 is preferably selected
Step S03: and performing first dry etching on the side wall material for depositing the protective layer to form the protective layer at least on the top surface of the fin part.
Please refer to fig. 5. The protective layer is formed to be used as a sacrificial layer when the side wall material is removed through etching. Therefore, the protective layer can be formed by adopting the same material as the material of the side wall. This step may include:
when the first dry etching is performed, the protective layer 500 may be formed by depositing a product of the reaction of the etching gas on the top surface of the fin 200 and the top surface of the gate 300. Taking silicon dioxide as a side wall material as an example, the following may be specifically mentioned: when the first dry etching is performed, silicon tetrachloride and oxygen may be used as etching gases, and the bias voltage is turned off, and silicon dioxide generated by the reaction of silicon tetrachloride and oxygen is deposited on the top surfaces of the fin portion 200 and the gate 300 to form the protective layer 500.
Step S04: and continuously performing second dry etching for the purpose of etching removal on the side wall material, and removing the side wall material on the side wall of the fin part.
Please refer to fig. 6. The second dry etching may use a conventional sidewall etching process to etch and remove the sidewall material on the sidewalls of the gate 300 and the fin 200. At this time, the protective layer 500 is used as a sacrificeThe layer, while consuming the protective layer 500 on the top surface, removes the sidewall material on the sidewalls of the gate 300 and the fin 200. The method specifically comprises the following steps: when the second dry etching is performed, a gas containing F (e.g., CF) may be used4) And inert gas (e.g., Ar) as an etching gas, and the bias voltage is turned on, and the generated bombardment effect is utilized to achieve that the sidewall materials 400 on the side surfaces of the fin 200 and the gate 300 are etched more intensely while the protective layer 500 is consumed, so that the sidewall materials 400 on the side walls of the fin 200 and the gate 300 are removed step by step.
Step S05, repeating step S03 and step S04 until the sidewall material on the fin sidewalls is removed.
In this step, the first dry etching and the second dry etching are continuously and cyclically performed, and the etching process and the etching amount can be accurately controlled by continuously depositing the protective layer 500 and etching the sidewall material 400 until the sidewall material 400 on the sidewall of the fin portion 200 is completely removed. At this time, the gate sidewall spacers 400' are finally formed, as shown in fig. 7.
Compared with the prior art, the method for reducing the fin loss in the etching of the FinFET side wall, disclosed by the invention, has the advantages that in the etching process, the bias voltage is firstly closed, and SiCl is used4And O2As an etching gas, since this step is deposition-based, SiO is formed2Mainly accumulating on the surface of Fin to form a protective layer; the deposition amount of the protective layer on the side surface of the Fin part (Fin) is less; then, the bias voltage is turned on, and the gas containing F and Ar are used for bombardment, so that SiO on the surface of the consumed Fin part (Fin)2And when the protective layer is used, the side wall of the Fin side surface is etched more intensely. Repeating the steps until the side walls of the Fin portion (Fin) side walls are removed completely.
Meanwhile, the process of the invention is compatible with the conventional silicon-based ultra-large scale integrated circuit manufacturing technology, has the characteristics of simplicity, convenience and short period, and reduces the process cost.
In addition, after the above steps are completed, other processes for forming the CMOS device may be performed, and these process steps may be formed by methods familiar to those skilled in the art, and will not be described herein again.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method for reducing fin loss in etching of FinFET side walls is characterized by comprising the following steps:
step S01: providing a semiconductor substrate, and forming a fin part and a grid electrode of a FinFET on the semiconductor substrate;
step S02: depositing a side wall material, and covering the fin part and the grid electrode;
step S03: performing first dry etching on the side wall material for depositing a protective layer, and forming a protective layer at least on the top surface of the fin part;
step S04: continuing to perform second dry etching on the side wall material for the purpose of etching removal, and removing the side wall material on the side wall of the fin part;
step S05: and circularly repeating the step S03 and the step S04 until the side wall materials on the side walls of the fin parts are completely removed.
2. The method of claim 1, wherein the protective layer is used as a sacrificial layer during removal of the spacer material during etching.
3. The method of claim 1, wherein a material of the protective layer is the same as a material of a sidewall.
4. The method of claim 1, wherein in step S02, a layer of spacer material with uniform thickness is formed by chemical vapor deposition covering the fin and the gate.
5. The method of claim 1, wherein in step S03, when performing the first dry etching, the protective layer is formed by using a product of a reaction of an etching gas to deposit on the top surface of the fin and the top surface of the gate。
6. The method for reducing fin loss in etching of the FinFET sidewall, according to claim 5, wherein the material of the sidewall is silicon dioxide, silicon tetrachloride and oxygen are used as etching gases during the first dry etching, bias voltage is closed, and silicon dioxide generated by reaction of the silicon tetrachloride and the oxygen is accumulated on the top surface of the fin and the top surface of the gate to form the protective layer.
7. The method of claim 1, wherein in step S04, when performing the second dry etching, the protective layer is used as a sacrificial layer to remove sidewall material on the gate sidewall and the fin sidewall while consuming the protective layer on the top surface。
8. The method of claim 7, wherein a protective layer material and a side wall material are the same, and during the second dry etching, an F-containing gas and an inert gas are used as etching gases, bias voltage is turned on, and the generated bombardment effect is utilized to synchronously remove the side wall materials of the fin portion side wall and the gate side wall while consuming the protective layer.
9. The method of claim 1, wherein the semiconductor substrate material is monocrystalline silicon, polycrystalline silicon, or amorphous silicon; or the semiconductor substrate material is silicon, germanium, gallium arsenide or a silicon-germanium compound; or, the semiconductor substrate has an epitaxial layer; or, the semiconductor substrate is a silicon-on-insulator substrate.
10. The method of claim 1, wherein the fin is single crystal silicon doped with N-type or P-type impurities.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104078349A (en) * | 2013-03-29 | 2014-10-01 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
| CN104183500A (en) * | 2014-08-15 | 2014-12-03 | 上海华力微电子有限公司 | Method for forming ion-implantation side wall protection layer on FinFET device |
| CN104217938A (en) * | 2014-08-26 | 2014-12-17 | 上海华虹宏力半导体制造有限公司 | Forming method of semiconductor structure |
| CN106206284A (en) * | 2014-10-02 | 2016-12-07 | 台湾积体电路制造股份有限公司 | Modified model etch process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9627245B2 (en) * | 2014-03-05 | 2017-04-18 | Globalfoundries Inc. | Methods of forming alternative channel materials on a non-planar semiconductor device and the resulting device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104078349A (en) * | 2013-03-29 | 2014-10-01 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
| CN104183500A (en) * | 2014-08-15 | 2014-12-03 | 上海华力微电子有限公司 | Method for forming ion-implantation side wall protection layer on FinFET device |
| CN104217938A (en) * | 2014-08-26 | 2014-12-17 | 上海华虹宏力半导体制造有限公司 | Forming method of semiconductor structure |
| CN106206284A (en) * | 2014-10-02 | 2016-12-07 | 台湾积体电路制造股份有限公司 | Modified model etch process |
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