CN109560817A - A kind of analog-digital converter - Google Patents
A kind of analog-digital converter Download PDFInfo
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- CN109560817A CN109560817A CN201811455314.5A CN201811455314A CN109560817A CN 109560817 A CN109560817 A CN 109560817A CN 201811455314 A CN201811455314 A CN 201811455314A CN 109560817 A CN109560817 A CN 109560817A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/358—Continuously compensating for, or preventing, undesired influence of physical parameters of non-linear distortion, e.g. instability
Abstract
The embodiment of the invention provides a kind of analog-digital converter, the first output end of multi-bit quantizer is successively connect through the first delay circuit, the second D/A conversion unit with the second input terminal of third integral device, forms the first negative-feedback circuit；Successively the second input terminal connection through nonlinear dynamical elements matching logic device, the first D/A conversion unit and first integrator of the second output terminal of first multi-bit quantizer, forms the second negative-feedback circuit.The input of the quantized result divided reset of quantizer to integrator, the input that least significant bit segmentation is fed back to digital analog converter can be realized second-order noise shaping by the present invention.The present invention can make the output voltage swing of integrator be substantially reduced, and relax the bandwidth and gain requirement of Design of Amplifiers significantly.Analog-digital converter provided in an embodiment of the present invention can meet the requirement of high-precision and low-power consumption simultaneously.
Description
Technical field
The present invention relates to field of signal processing, in particular to a kind of analog-digital converter.
Background technique
Analog-digital converter (Analog-to-Digital Converter, ADC) is a kind of to convert number for analog signal
The electronic device of signal, Δ ∑ (also known as Delta-Sigma) ADC use the strategy that precision is changed with speed, in conjunction with over-sampling and
Noise shaping techniques substantially reduce in-band noise energy, therefore have very high precision, or even do not need at low voltage tight
The matching or correction of lattice can be achieved with high-resolution.
But the power consumption of Δ ∑ ADC is larger, high-precision and low-power consumption requirement can be met simultaneously by being currently badly in need of one kind
ADC。
Summary of the invention
In view of this, the present invention provides a kind of analog-digital converter, to meet high-precision and low-power consumption requirement simultaneously.
In order to achieve the above-mentioned object of the invention, the present invention the following technical schemes are provided:
A kind of analog-digital converter, comprising: the first filter circuit 002, first integrator 001, second integral device 003, third
Integrator 004, the 4th integrator 007, the first multi-bit quantizer 005, the first D/A conversion unit 011, the second digital-to-analogue conversion
Unit 009, the first delay circuit 008, the second filter circuit 006 and nonlinear dynamical elements matching logic device 010,
The first input end of the first integrator 001 is input end of analog signal, the output of the first integrator 001
End is connect through first filter circuit 002 with the second input terminal of the second integral device 003, the second integral device 003
First input end be input end of analog signal, the of the output end of the second integral device 003 and the third integral device 004
The connection of one input terminal, the output end of the third integral device 004 are connect with the input terminal of first multi-bit quantizer 005,
First output end of first multi-bit quantizer 005 is through second filter circuit 006 and the 4th integrator 007
First input end connection, the second of the second output terminal of first multi-bit quantizer 005 and the 4th integrator 007 are defeated
Enter end connection, the output end of the 4th integrator 007 is digital signal output end；
First output end of first multi-bit quantizer 005 is successively through first delay circuit 008, described second
D/A conversion unit 009 is connect with the second input terminal of the third integral device 004, forms the first negative-feedback circuit；
The second output terminal of first multi-bit quantizer 005 is successively through the nonlinear dynamical elements matching logic device
010, first D/A conversion unit 011 is connect with the second input terminal of the first integrator 001, forms the second negative-feedback
Circuit.
Optionally, second filter circuit is third-order filter.
A kind of analog-digital converter, comprising: first filter 102, the 5th integrator 101, the 6th integrator the 103, the 7th product
Divide device 104, the 8th integrator 106, the 9th integrator 109, the second multi-bit quantizer 107, second filter 105, third number
Mould converting unit 111, the 4th D/A conversion unit 113, the 5th D/A conversion unit 114, the second delay circuit 108, third are prolonged
When circuit 110 and the 4th delay circuit 112, the first input end of the 5th integrator 101 is input end of analog signal, described
The output end of 5th integrator 101 is connect through the first filter 102 with the second input terminal of the 6th integrator 103,
The first input end of 6th integrator 103 be input end of analog signal, the output end of the 6th integrator 103 with it is described
The first input end of 7th integrator 104 connects, the output end of the 7th integrator 104 through the second filter 105 with
The first input end of 8th integrator 106 connects, the output end of the 8th integrator 106 and more than second bit quantity
Change the input terminal connection of device 107, the first output end of second multi-bit quantizer 107 is through second delay circuit 108
Connect with the first input end of the 9th integrator 109, the second output terminal of second multi-bit quantizer 107 with it is described
Second input terminal of the 9th integrator 109 connects, and the output end of the 9th integrator 109 is digital signal output end；
First output end of second multi-bit quantizer 107 is successively through the third delay circuit 110, the third
D/A conversion unit 111 is connect with the second input terminal of the 8th integrator 106, forms third negative-feedback circuit；
First output end of second multi-bit quantizer 107 is also successively through the 4th delay circuit 112, described
Four D/A conversion units 113 are connect with the second input terminal of the 7th integrator 104, form the 4th negative-feedback circuit；
The second output terminal of second multi-bit quantizer 107 through the 5th D/A conversion unit 114 respectively with institute
State the second input terminal of the 5th integrator 101, the third input terminal of the 6th integrator 102, the 8th integrator 105
The connection of third input terminal, forms the 5th negative-feedback circuit.
First output end of a kind of analog-digital converter provided in an embodiment of the present invention, multi-bit quantizer successively prolongs through first
When circuit, the second D/A conversion unit connect with the second input terminal of third integral device, form the first negative-feedback circuit；More than first
The second output terminal of multi-bit quantizer is successively through nonlinear dynamical elements matching logic device, the first D/A conversion unit and the first product
The the second input terminal connection for dividing device, forms the second negative-feedback circuit.The present invention can be by the quantized result divided reset of quantizer
To the input of integrator, the input that least significant bit segmentation is fed back to digital analog converter realizes second-order noise shaping.This hair
The bright output voltage swing that can make integrator is substantially reduced, and relaxes the bandwidth and gain requirement of Design of Amplifiers significantly.
Analog-digital converter provided in an embodiment of the present invention can meet the requirement of high-precision and low-power consumption simultaneously.The present invention is to more bit quantities
The output for changing device carries out segment processing, effectively reduces the output step-length and feedback DAC nonlinearity of integrator in this way.The present invention
Digital noise coupling is also carried out by the first negative-feedback circuit, is greatly reduced due between MSBs DAC and LSBs DAC coefficient
Mismatch and lead to the noise leakage of quantizer.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described.
Fig. 1 is a kind of system architecture diagram of analog-digital converter provided in an embodiment of the present invention；
Fig. 2 is the system architecture diagram of another analog-digital converter provided in an embodiment of the present invention；
Fig. 3 is second order continuous-time Delta-Sigma ADC ideal system model provided in an embodiment of the present invention signal
Figure；
Fig. 4 is continuous time integrator schematic diagram；
Fig. 5 is the Delta-Sigma ADC system model schematic that loop is added and is delayed later；
Fig. 6 is two kinds of analog-digital converters provided by the invention and traditional analog-to-digital conversion based on Leslie-Singh framework
The performance comparison schematic diagram of device.
Specific embodiment
The invention discloses a kind of analog-digital converter, those skilled in the art can use for reference present disclosure, be suitably modified work
Skill parameter is realized.In particular, it should be pointed out that all similar substitutions and modifications are aobvious and easy for a person skilled in the art
See, they are considered as being included in the present invention.Method and application of the invention is described by preferred embodiment,
Related personnel obviously can not depart from the content of present invention, method described herein and application are modified in spirit and scope or
Appropriate changes and combinations carry out implementation and application the technology of the present invention.
The process that present inventor studies acquisition analog-digital converter provided by the invention first below is illustrated:
Establish the model of two order ideal continuous time Delta-Sigma ADC:
Comprehensively consider the factors such as power consumption, design difficulty, speed, present inventor selects second order continuous-time Delta-
Sigma ADC ideal system as shown in figure 3, modeling factors matching in order to make the system and subsequent non-zero loop be delayed,
Need to indicate the continuous system of two ranks using discrete transfer function, wherein the transformational relation of discrete domain to continuous domain is such as
Under:
Wherein, α, β are the proportionality coefficient for feeding back rectangular pulse relative to sampling clock, and β-α is normalization pulsewidth, fsTo adopt
Sample frequency；ω0、ω1For angular frequency corresponding to different rank integrator；
In order to reduce the output voltage swing of first order integrator 301, before the input terminal of second level integrator 302 introduces all the way
Feedback, we feed back DAC using non-return-to-zero (NRZ, Non-Return to Zero), so have α=0, β=1.Discrete transfer function
The second order continuous-time system of expression is as follows:
The illustratively non-ideal influence to system shown in Figure 3 of loop delay and amplifier below:
The error introduced to the non-ideal characteristic of amplifier to system shown in Figure 3 is analyzed, consecutive hours as shown in Figure 4
Between integrator, which has n item to input branch, the transmission function int (s) of integrator in available Fig. 3 are as follows:
Wherein, kjThe feedback factor of branch is corresponded to for integrator, GBW is the gain bandwidth product of integrator, AdcFor integrator
DC current gain, GE is gain error, and ω is angular frequency.
If guaranteeing that amp DC gain is sufficiently large and the GBW of integrator is limited, the transmission function of integrator can
With simplification are as follows:
GBW:ADC→∞
When DC current gain is sufficiently large, its influence to transmission function be can be ignored, but when integrator
When GBW is limited, then gain bandwidth product can introduce a pole to transmission function, the stability of system is influenced.In system
Middle selection speed is high, reinforced concrete structure low in energy consumption and the good linearity and output voltage swing, so the DC current gain error of two-stage
It can be compensated by adjusting RC constant, introducing pole, that can be equivalent to delay, and equivalent delay is as follows:
τD1And τD2It respectively indicates first order integrator and is delayed with the loop of second level integrator, ω1、ω2Respectively
Level-one integrator and with angular frequency corresponding to the integrator of the second level.
It should be noted τD1>>τD2, total delay calculated according to bigger delay.Loop delay system later is added
Adjustable model of uniting is as shown in Figure 5.For system shown in Figure 5, non-zero loop delay factor is subjected to Taylor series expansion
It obtains:
H~It (s) is the ssystem transfer function that non-zero loop loop delay factor is added, k0、k1、k2Three in respectively Fig. 5
The feedback factor of feedback branch, τ are that the loop of system shown in Figure 5 is delayed.
By the loop delay bound τ of General SystemELD=0.25TsThe bandwidth of second level integrator 502 in design drawing 5 is extremely
When being 4 times of sample frequency less, the formula is available compared with the transmission function of ideal second order system:
τD1+τELD=0.5Ts
To sum up, the limited gain bandwidth product error of amplifier can be equivalent at a system delay, and carries out together with ELD
Compensation, and amp DC gain error can be compensated by adjusting integrator.
As shown in Figure 1, a kind of analog-digital converter provided in an embodiment of the present invention, may include: the first filter circuit 002,
First integrator 001, second integral device 003, third integral device 004, the 4th integrator 007, the first multi-bit quantizer 005,
First D/A conversion unit 011, the second D/A conversion unit 009, the first delay circuit 008, the second filter circuit 006 and non-thread
Property dynamic element matching logic device 010, the first input end of the first integrator 001 is input end of analog signal, described the
The output end of one integrator 001 is connect through first filter circuit 002 with the second input terminal of the second integral device 003,
The first input end of the second integral device 003 be input end of analog signal, the output end of the second integral device 003 with it is described
The first input end of third integral device 004 connects, the output end of the third integral device 004 and first multi-bit quantizer
005 input terminal connection, the first output end of first multi-bit quantizer 005 is through second filter circuit 006 and institute
State the first input end connection of the 4th integrator 007, the second output terminal of first multi-bit quantizer 005 and the described 4th
Second input terminal of integrator 007 connects, and the output end of the 4th integrator 007 is digital signal output end；
First output end of first multi-bit quantizer 005 is successively through first delay circuit 008, described second
D/A conversion unit 009 is connect with the second input terminal of the third integral device 004, forms the first negative-feedback circuit；
The second output terminal of first multi-bit quantizer 005 is successively through the nonlinear dynamical elements matching logic device
010, first D/A conversion unit 011 is connect with the second input terminal of the first integrator 001, forms the second negative-feedback
Circuit.
Optionally, second filter circuit 006 can be third-order filter.
It is multiple that the input of the quantized result divided reset of quantizer to integrator can be effectively reduced into dynamic element matching
Polygamy.But the input of quantized result divided reset to the integrator of quantizer be will lead into most significant bit (Most
Significant Bits, MSBs) D/A conversion unit (Digital to Analog Converter, DAC) and it is minimum effectively
Mismatch between (Least Significant Bits, LSBs) the DAC coefficient of position, occurs noise leakage.Leslie-Singh
The part MSBs is only directly fed back to the input of integrator by framework, by a digital processing module by the part MSBs and the portion LSBs
Integration is divided to obtain the output of system.Although the high bit part of Leslie-Singh framework feedback quantization device output, its
Performance Equivalent one system with high quantization bit number.In actual design the framework due to number noise transfer function and
Mismatch between the noise transfer function of simulation and lead to very big integrated noise leakage problem, noise leakage can make signal noise
Distortion is than reducing more than 10dB.
Therefore can effectively inhibit to integrate leakage problem present invention introduces noise coupling technology, as shown in Figure 1.The present invention is real
The MSBs that the second output terminal of first multi-bit quantizer 005 exports (can be used V by the analog-digital converter for applying example offer
(z) indicate) feed back the input terminal for arriving first integrator 001.And the first output end output of first multi-bit quantizer 005
LSBs (use Qd(z) indicate) it is considered as digital quantization noise, pass through second D/A conversion unit 009 feedback to more than first
The input terminal of multi-bit quantizer 005.Specifically, the MSBs of the second output terminal output of the first multi-bit quantizer 005 can in Fig. 1
With are as follows:
V (z)=STF (z) X (z)-(1-z-1)NTF(z)Qd(z)+Qa(z)NTF(z)
The then digital signal Y (z) of the output of analog-digital converter shown in Fig. 1 are as follows:
Y (z)=X (z) STF (z)+Qa(z)NTF(z)
Wherein, QaIt (z) is the analog quantization noise of the first multi-bit quantizer 005.
A kind of analog-digital converter provided by the invention, more bit Delta-Sigma modulation based on continuous time low-power consumption
Device framework.The present invention can be by the input of the quantized result divided reset of quantizer to integrator, and least significant bit segmentation is anti-
The input for being fed to digital analog converter realizes second-order noise shaping.The present invention can make the output voltage swing of integrator significantly subtract
It is small, the bandwidth and gain requirement of Design of Amplifiers are relaxed significantly.
The present invention carries out segment processing to the output of multi-bit quantizer, effectively reduces the output step-length of integrator in this way
With feedback DAC nonlinearity.The present invention also pass through the first negative-feedback circuit carry out digital noise coupling, greatly reduce due to
Mismatch between MSBs DAC and LSBs DAC coefficient and the noise leakage for leading to quantizer.Mould provided in an embodiment of the present invention
Number converter can meet the requirement of high-precision and low-power consumption simultaneously.
It can be incited somebody to action with one using the input terminal that need to only feed back MSBs to integrator of digital noise coupling technique
MSBs and LSBs feeds back the system equivalence to the input terminal of system.But when the output voltage swing of integrator is larger, noise coupling
Conjunction technology will receive the influence of integrator conversion rate.In conjunction with above analysis, in the digital noise of Leslie-Singh framework
It couples on framework, as shown in Fig. 2, the invention proposes the dual noise shaping continuous time system framves coupled based on digital noise
A kind of analog-digital converter of structure.
As shown in Fig. 2, it is provided in an embodiment of the present invention another kind analog-digital converter, may include: first filter 102,
5th integrator 101, the 6th integrator 103, the 7th integrator 104, the 8th integrator 106, the 9th integrator more than 109, second
Multi-bit quantizer 107, second filter 105, third D/A conversion unit 111, the 4th D/A conversion unit 113, the 5th digital-to-analogue
Converting unit 114, the second delay circuit 108, third delay circuit 110 and the 4th delay circuit 112,
The first input end of 5th integrator 101 is input end of analog signal, the output of the 5th integrator 101
End is connect through the first filter 102 with the second input terminal of the 6th integrator 103, the 6th integrator 103
First input end is input end of analog signal, the output end of the 6th integrator 103 and the first of the 7th integrator 104
Input terminal connection, the output end of the 7th integrator 104 is through the second filter 105 and the 8th integrator 106
First input end connection, the output end of the 8th integrator 106 and the input terminal of second multi-bit quantizer 107 connect
It connects, the first output end of second multi-bit quantizer 107 is through second delay circuit 108 and the 9th integrator
109 first input end connection, the second output terminal of second multi-bit quantizer 107 and the 9th integrator 109
The connection of second input terminal, the output end of the 9th integrator 109 are digital signal output end；
First output end of second multi-bit quantizer 107 is successively through the third delay circuit 110, the third
D/A conversion unit 111 is connect with the second input terminal of the 8th integrator 106, forms third negative-feedback circuit；
First output end of second multi-bit quantizer 107 is also successively through the 4th delay circuit 112, described
Four D/A conversion units 113 are connect with the second input terminal of the 7th integrator 104, form the 4th negative-feedback circuit；
The second output terminal of second multi-bit quantizer 107 through the 5th D/A conversion unit 114 respectively with institute
State the second input terminal of the 5th integrator 101, the third input terminal of the 6th integrator 102, the 8th integrator 105
The connection of third input terminal, forms the 5th negative-feedback circuit.
The MSBs that second multi-bit quantizer 107 exports in analog-digital converter shown in Fig. 2 are as follows:
V (z)=z-1X(z)STF(z)-(1-z-1)Qd(z)+Qa(z)NTF(z)
The digital signal of analog-digital converter output shown in Fig. 2 are as follows:
Y (z)=z-1X(z)STF(z)+Qa(z)NTF(z)
Wherein, QdIt (z) is subtracting property quantizing noise in analog-digital converter shown in Fig. 2, rather than additivity quantizing noise.Not
In the case where considering loop delay, have in analog-digital converter shown in Fig. 2:
H (z)=2I (z)+I2(z)；I (z)=z-1/1-z-1
Analog-digital converter shown in Fig. 2 relative to analog-digital converter shown in Fig. 1 the difference is that:
Analog-digital converter shown in Fig. 2 will also return the 7th integrator second level product by the LSBs partial feedback of period delay
Divide the input of device 104.
Third negative-feedback circuit and the signal of the 4th negative-feedback circuit feedback by making an uproar twice in analog-digital converter shown in Fig. 2
Sound shaping, respectively Qa(z) NTF (z) and (1-z-1)Qd(z), therefore, analog-digital converter shown in Fig. 2 does not need complicated number
Word processing module reduces the output voltage swing of integrator, is conducive to the realization of digital noise coupling technique.
Fig. 6 shows that two kinds of analog-digital converters provided by the invention and traditional modulus based on Leslie-Singh framework turn
The performance comparison of parallel operation.From fig. 6 it can be seen that traditional analog-digital converter based on Leslie-Singh framework, Fig. 1 institute
Show that analog-digital converter promotes the SNDR of system to analog-digital converter shown in 63.9, Fig. 2 from 59.9 to be increased to SNDR
87.4dB。
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (3)
1. a kind of analog-digital converter characterized by comprising the first filter circuit (002), first integrator (001), the second product
Divide device (003), third integral device (004), the 4th integrator (007), the first multi-bit quantizer (005), the first digital-to-analogue conversion
Unit (011), the second D/A conversion unit (009), the first delay circuit (008), the second filter circuit (006) and Nonlinear Dynamic
State Match of elemental composition logic device (010),
The first input end of the first integrator (001) is input end of analog signal, the output of the first integrator (001)
End is connect through first filter circuit (002) with the second input terminal of the second integral device (003), the second integral device
(003) first input end is input end of analog signal, the output end and the third integral device of the second integral device (003)
(004) first input end connection, the output end of the third integral device (004) and first multi-bit quantizer (005)
Input terminal connection, the first output end of first multi-bit quantizer (005) is through second filter circuit (006) and institute
State the 4th integrator (007) first input end connection, the second output terminal of first multi-bit quantizer (005) with it is described
Second input terminal of the 4th integrator (007) connects, and the output end of the 4th integrator (007) is digital signal output end；
First output end of first multi-bit quantizer (005) is successively through first delay circuit (008), described second
D/A conversion unit (009) is connect with the second input terminal of the third integral device (004), forms the first negative-feedback circuit；
The second output terminal of first multi-bit quantizer (005) is successively through the nonlinear dynamical elements matching logic device
(010), first D/A conversion unit (011) connect with the second input terminal of the first integrator (001), forms second
Negative-feedback circuit.
2. analog-digital converter according to claim 1, which is characterized in that second filter circuit is third-order filter.
3. a kind of analog-digital converter characterized by comprising first filter (102), the 5th integrator (101), the 6th integral
Device (103), the 7th integrator (104), the 8th integrator (106), the 9th integrator (109), the second multi-bit quantizer
(107), second filter (105), third D/A conversion unit (111), the 4th D/A conversion unit (113), the 5th digital-to-analogue turn
Unit (114), the second delay circuit (108), third delay circuit (110) and the 4th delay circuit (112) are changed,
The first input end of 5th integrator (101) is input end of analog signal, the output of the 5th integrator (101)
End is connect through the first filter (102) with the second input terminal of the 6th integrator (103), the 6th integrator
(103) first input end is input end of analog signal, the output end and the 7th integrator of the 6th integrator (103)
(104) first input end connection, the output end of the 7th integrator (104) through the second filter (105) with it is described
The first input end of 8th integrator (106) connects, the output end of the 8th integrator (106) and more than second bit quantity
Change the input terminal connection of device (107), the first output end of second multi-bit quantizer (107) is through second delay circuit
(108) it is connect with the first input end of the 9th integrator (109), the second of second multi-bit quantizer (107) is defeated
Outlet is connect with the second input terminal of the 9th integrator (109), and the output end of the 9th integrator (109) is number letter
Number output end；
First output end of second multi-bit quantizer (107) is successively through the third delay circuit (110), the third
D/A conversion unit (111) is connect with the second input terminal of the 8th integrator (106), forms third negative-feedback circuit；
First output end of second multi-bit quantizer (107) is also successively through the 4th delay circuit (112), described
Four D/A conversion units (113) are connect with the second input terminal of the 7th integrator (104), form the 4th negative-feedback circuit；
The second output terminal of second multi-bit quantizer (107) through the 5th D/A conversion unit (114) respectively with institute
State the second input terminal of the 5th integrator (101), third input terminal, the 8th integrator of the 6th integrator (102)
(105) third input terminal connection, forms the 5th negative-feedback circuit.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107294537A (en) * | 2017-06-30 | 2017-10-24 | 湖南天羿领航科技有限公司 | A kind of analog-digital converter based on Sigma Delta Modulator |
| US10972319B2 (en) * | 2018-09-12 | 2021-04-06 | Texas Instruments Incorporated | Clockless decision feedback equalization (DFE) for multi-level signals |
| CN116436461A (en) * | 2023-06-12 | 2023-07-14 | 北京思凌科半导体技术有限公司 | Digital-to-analog converter and electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103929184A (en) * | 2014-04-16 | 2014-07-16 | 中国科学技术大学 | Delta-sigma modulator based on digital-noise coupling technology |
| CN107222216A (en) * | 2017-06-05 | 2017-09-29 | 中国科学技术大学 | The second order continuous-time SD analog-digital converters coupled using self noise |
| CN107395206A (en) * | 2017-07-26 | 2017-11-24 | 中国科学技术大学 | Band feedback shifts to an earlier date set successive approximation digital analog converter and corresponding Delta SigmaADC frameworks |
-
2018
- 2018-11-30 CN CN201811455314.5A patent/CN109560817A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103929184A (en) * | 2014-04-16 | 2014-07-16 | 中国科学技术大学 | Delta-sigma modulator based on digital-noise coupling technology |
| CN107222216A (en) * | 2017-06-05 | 2017-09-29 | 中国科学技术大学 | The second order continuous-time SD analog-digital converters coupled using self noise |
| CN107395206A (en) * | 2017-07-26 | 2017-11-24 | 中国科学技术大学 | Band feedback shifts to an earlier date set successive approximation digital analog converter and corresponding Delta SigmaADC frameworks |
Non-Patent Citations (1)
| Title |
|---|
| 严海月等: "双重噪声整形连续时间Δ－Σ调制器的架构设计", 《微电子学》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107294537A (en) * | 2017-06-30 | 2017-10-24 | 湖南天羿领航科技有限公司 | A kind of analog-digital converter based on Sigma Delta Modulator |
| CN107294537B (en) * | 2017-06-30 | 2023-08-29 | 湖南天羿领航科技有限公司 | Sigma Delta Modulator-based analog-to-digital converter |
| US10972319B2 (en) * | 2018-09-12 | 2021-04-06 | Texas Instruments Incorporated | Clockless decision feedback equalization (DFE) for multi-level signals |
| CN116436461A (en) * | 2023-06-12 | 2023-07-14 | 北京思凌科半导体技术有限公司 | Digital-to-analog converter and electronic device |
| CN116436461B (en) * | 2023-06-12 | 2023-09-19 | 北京思凌科半导体技术有限公司 | Digital-to-analog converter and electronic device |
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