CN109547665B - Circuit for calculating square root of N times - Google Patents
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Abstract
The embodiment of the invention relates to the field of digital circuits, and discloses a circuit for calculating a square root of N times. In the invention, an initial value selection circuit and a Newton iteration circuit are electrically connected in sequence, wherein the initial value selection circuit comprises: a bit width confirmation circuit and a calculation circuit which are electrically connected in sequence; the bit width confirmation circuit is used for obtaining the bit width of the iteration initial value according to the bit number of the input binary number and the bit width of the input binary number; the calculating circuit is used for carrying out sectional calculation on the input binary number according to the bit width of the iteration initial value determined by the bit width confirming module and a first preset threshold value to obtain the iteration initial value; and the Newton iteration circuit is used for selecting the iteration initial value determined by the circuit and the input binary number according to the initial value, and calculating and obtaining the root of N times of the input binary number by using a Newton iteration algorithm, wherein N is an integer greater than or equal to 2. And applying the obtained N-times square root to the conversion process of the color space to realize the color space conversion of the image.
Description
Technical Field
The embodiment of the invention relates to the field of digital circuits, in particular to a circuit for calculating a square root of N times.
Background
In order to improve image quality, image data needs to be converted from one color space to another color space for processing, and when color space conversion is performed, the square root of degree n needs to be calculated. The square root of degree n is obtained through a digital circuit, and at present, the following methods are mainly realized: cyclic search methods, lookup table methods and newton's iteration methods.
The inventor finds that at least the following problems exist in the prior art: the cyclic search method starts from '0' to search and approach gradually, and the larger the number of the exponentiated parties is, the more the number of cycles is, which is not beneficial to the realization of the digital circuit. The lookup table method is to make the number of the radices and the result into a table and store the table into the storage space, and the larger the number of the radices is, the larger the table is, the larger the required storage space is. The newton iteration method, if an inappropriate iteration value is selected, may cause an increase in the number of iterations in order to achieve the target accuracy, thereby wasting hardware resources.
Disclosure of Invention
The invention aims to provide a circuit for calculating a square root of N times, which is used for obtaining an optimal iteration initial value by carrying out sectional calculation on an input binary number, obtaining the square root of the N times of the input binary number by using a Newton iteration algorithm through a digital circuit, and realizing the color space conversion of an image by applying the square root of the N times to the conversion process of a color space.
To solve the above technical problem, an embodiment of the present invention provides a circuit for calculating a square root of degree N, including: the circuit is selected to initial value and the newton's iteration circuit that connects electrically in proper order, and wherein, initial value selects the circuit to include: a bit width confirmation circuit and a calculation circuit which are electrically connected in sequence; the bit width confirmation circuit is used for obtaining the bit width of the iteration initial value according to the bit number of the input binary number and the bit width of the input binary number; the calculating circuit is used for carrying out sectional calculation on the input binary number according to the bit width of the iteration initial value determined by the bit width confirming circuit and a first preset threshold value to obtain the iteration initial value; and the Newton iteration circuit is used for calculating and obtaining the root of the N times of the input binary number by using a Newton iteration algorithm according to the iteration initial value and the input binary number, wherein N is an integer greater than or equal to 2.
Compared with the prior art, the embodiment of the invention obtains the N-th-order square root of the input binary number through the circuit for calculating the N-th-order square root, applies the N-th-order square root to the conversion process of the color space, reduces the Newton iteration times and achieves the target precision through the obtained optimal iteration initial value, can reduce the storage space, further saves the hardware resource, is easy to realize through a digital circuit, and realizes the color space conversion of the image.
Further, the bit width confirmation circuit includes: a judgment digit circuit and a bit width calculating circuit which are electrically connected in sequence; the judgment bit number circuit is used for judging whether the bit number of the input binary number is an integral multiple of N or not, and if yes, the bit width of the input binary number is used as the output bit width; otherwise, acquiring a new binary number and the bit width of the new binary number, and taking the bit width of the new binary number as the output bit width; outputting the output bit width to a bit width calculating circuit; and the bit width calculating circuit is used for obtaining the bit width of the iteration initial value according to the output bit width output by the bit judging circuit and the square root times N required to be calculated.
In the method, the bit width of the iteration initial value is obtained, preparation is made for further calculation of the iteration initial value, and the iteration times can be reduced on the premise of ensuring the target precision.
Additionally, a computational circuit, comprising: the device comprises a segmentation judgment circuit and an iteration initial value calculation circuit which are electrically connected in sequence; the segment judgment circuit is used for judging whether data on at least one segment of the binary number corresponding to the output bit width is equal to a first preset threshold value or not according to the binary number corresponding to the output bit width and the output bit width, and if yes, obtaining the number of segments of the segment, wherein the number of segments of the segment is smaller than or equal to the output bit width; and the iteration initial value calculation circuit is used for obtaining the iteration initial according to the number of the segmentation segments determined by the segmentation judgment circuit.
In the method, the binary number corresponding to the output bit width is subjected to segmentation value taking to obtain a corresponding iteration initial value, so that the calculation times are reduced, the storage space is further reduced, and the digital circuit is easy to realize.
In addition, the judgment bit number circuit is used for: judging whether the digit of the input binary number is an integral multiple of N, if so, obtaining the bit width of the input binary number; otherwise, generating a new binary number, enabling the digit of the new binary number to meet the integral multiple of N, and taking the bit width of the new binary number as the output bit width.
In addition, the segment judgment circuit is configured to: dividing binary numbers corresponding to the output bit width into L sections, and judging whether data on the ith section is equal to a first preset threshold value or not aiming at the ith section; if yes, outputting the segmentation segment number i to an iteration initial value calculation circuit for calculating an iteration initial value; otherwise, judging whether the data on the i-1 th subsection number is equal to a first preset threshold value or not; wherein L is an integer greater than or equal to 2, and the value range of i is a positive integer less than or equal to L.
In addition, the first preset threshold is obtained by calculation according to the number of the segmented segments and the output bit width.
Additionally, the newton iteration circuit is to: according to the iteration initial value and the input binary number, using a Newton iteration algorithm to perform the j-th calculation to obtain the N-th square root of the input binary number; judging whether the Newton iteration times j are equal to a second preset threshold value, if so, taking the N-time square root obtained by the iteration as the N-time square root of the input binary number, and ending the iteration; otherwise, continuing to perform the j +1 th iteration; wherein, the value range of j is an integer which is greater than or equal to 1 and less than or equal to B, B is an integer which is greater than or equal to 2, and B represents the preset total iteration times.
In the method, the iteration times are reduced by using the optimal iteration initial value, so that the hardware resources are saved.
In addition, the newton iteration circuit is also operable to: before the N-th root of the input binary number is calculated by using a Newton iterative algorithm, the input binary number and the iterative initial value determined by the initial value selection circuit are synchronously processed.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a block diagram of a circuit for calculating a root of power N according to a first embodiment of the present invention;
fig. 2 is a block diagram of a bit width confirmation circuit according to a first embodiment of the present invention;
FIG. 3 is a block diagram of a computing circuit according to a first embodiment of the invention;
FIG. 4 is a flowchart of the calculation of the number of segmentation segments in accordance with the first embodiment of the present invention;
fig. 5 is a flowchart for calculating the square root of degree N using the newton iteration method according to the second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that numerous technical details are set forth in order to provide a better understanding of the present application in various embodiments of the present invention. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
A first embodiment of the present invention relates to a circuit for calculating a square root of degree N for obtaining a square root of degree N of an input binary number, and applying the square root of degree N to a conversion process of a color space, thereby improving image quality. The implementation details of the circuit for calculating the square root of degree N in the present embodiment are specifically described below, and the following is only for the convenience of understanding the implementation details of the present solution and is not necessary for implementing the present solution.
Fig. 1 is a structural diagram of a circuit for calculating the root of the power N in the present embodiment, and specifically includes: an initial value selection circuit 101 and a newton iteration circuit 102 electrically connected in sequence, wherein the initial value selection circuit 101 includes: a bit width confirmation circuit 201 and a calculation circuit 202 electrically connected in sequence; the bit width confirmation circuit 201 is configured to obtain a bit width of the iteration initial value according to the bit number of the input binary number and the bit width of the input binary number; the calculating circuit 202 is configured to perform segmented calculation on the input binary number according to the bit width of the iteration initial value determined by the bit width confirming circuit 201 and a first preset threshold value, so as to obtain an iteration initial value; the newton iteration circuit 102 is configured to obtain an N-th power root of an input binary number by using a newton iteration algorithm according to an iteration initial value and the input binary number, where N is an integer greater than or equal to 2.
In one particular implementation, for function expression (1), the first derivative of function y is expressed as (2), and the approximation of the nth root is calculated as (3) using a newton's iterative algorithm, where X iskRepresenting the k-th approximation after iteration, where Xk+1Represents the (k + 1) th approximation after iteration, and y represents the number of the power of being opened by n.
y＝f(x)＝Xn (1)。
y＇＝f＇(x)＝nX(n-1) (2)。
Xk+1＝Xk–(f(x)/f＇(x))＝Xk–(y/nXk (n-1))＝(nXkn–y)/(nXk(n-1)) (3)。
The iteration initial value obtained by the initial value selection circuit 101 is set to X0The iteration is initialized to value X0Substituting the formula (3) to obtain the calculation result X of the first Newton iteration1Is mixing X1Substituting the formula (3) to obtain the calculation result X of the second Newton iteration2The result X of the second Newton iteration is calculated2Substituting the formula (3) to obtain the calculation result X of the third Newton iteration3By analogy, the calculation result X of the C-th Newton iteration can be obtainedCWherein C is an integer greater than or equal to 2.
As shown in fig. 2, the bit width confirmation circuit 201 includes: a judgment digit circuit 301 and a bit width calculation circuit 302 which are electrically connected in sequence; the bit number judging circuit 301 is configured to judge whether a bit number of an input binary number is an integer multiple of N, and if so, take a bit width of the input binary number as an output bit width; otherwise, acquiring a new binary number and the bit width of the new binary number, and taking the bit width of the new binary number as the output bit width; the output bit width is output to the bit width calculating circuit 302; the bit width calculating circuit 302 is configured to obtain a bit width of the iteration initial value according to the output bit width output by the bit judgment circuit 301 and the number N of square roots to be calculated.
In the case of a digital circuit, a corresponding binary number is represented by a high/low level of input data.
The judgment bit number circuit 301 is configured to: judging whether the digit of the input binary number is an integral multiple of N, if so, obtaining the bit width of the input binary number; otherwise, generating a new binary number, enabling the digit of the new binary number to meet the integral multiple of N, and taking the bit width of the new binary number as the output bit width.
In one specific implementation, setting N equal to 4, the input binary number is "111111000011110011", since there are 18 bits in total for one input binary number, i.e. the bit width of the input binary number is 18, since the bit width 18 of the input binary number is not an integer multiple of N, it is necessary to "00" on the highest complement of the input binary number to obtain a new binary number "00111111000011110011", and the bit width of the new binary number is 20, i.e. the output bit width is 20. And calculating the bit width of the iteration initial value according to the output bit width 20 and N. For example, the bit width of the new binary number is calculated as 20 divided by the integer part of N, 20 divided by 4 equals 5, and the bit width of the iteration initial value is 5.
As shown in fig. 3, the calculation circuit 202 includes: a segment judgment circuit 401 and an iteration initial value calculation circuit 402 which are electrically connected in sequence; the segment judgment circuit 401 is configured to judge, according to the binary number corresponding to the output bit width and the output bit width, whether data on at least one segment of the binary number corresponding to the output bit width is equal to a first preset threshold, and if yes, obtain the number of segments of the segment, where the number of segments of the segment is less than or equal to the output bit width; the iteration initial value calculation circuit 402 is configured to obtain an iteration initial value according to the number of segment segments determined by the segment determination circuit 401.
In one specific implementation, if the number of the segment segments determined by the segment determining circuit 401 is L and the data on the L-1 segment is equal to the first preset threshold, the obtained iteration initial value is PL-1Wherein L is an integer greater than or equal to 2.
Wherein the segmentation judging circuit 401 is configured to: dividing binary numbers corresponding to the output bit width into L sections, and judging whether data on the ith section is equal to a first preset threshold value or not aiming at the ith section; if yes, outputting the segmentation segment number i to an iteration initial value calculation circuit for calculating an iteration initial value; otherwise, judging whether the data on the i-1 th subsection number is equal to a first preset threshold value or not; wherein L is an integer greater than or equal to 2, and the value range of i is a positive integer less than or equal to L.
In one specific implementation, a specific flow chart for obtaining the number of segmented segments i is calculated using the segmentation decision circuit 401, as shown in fig. 4.
In step 501, the segment determination circuit 401 obtains the binary number corresponding to the output bit width input by the bit width confirmation circuit 201, and the segment determination circuit 401 divides the binary number corresponding to the output bit width into L segments, and then the process proceeds to step 502.
In step 502, for the ith segment, the segment determining circuit 401 determines whether the data on the ith segment is equal to a first preset threshold, if yes, go to step 503; otherwise, go to step 504.
In step 503, the segment judgment circuit 401 outputs the number i of segment segments to the iteration initial value calculation circuit 402, and the loop judgment flow is ended.
The iteration initial value calculation circuit 402 obtains the number i of segment segments, and then calculates the iteration initial value using the number i of segment segments.
In step 504, the segmentation decision circuit 401 calculates the next number of segmentation segments: i-1 and proceeds to step 502 to continue to determine whether the data in the i-1 th segment number is equal to the first preset threshold.
It should be noted that, by determining the data on each segment of the binary number corresponding to the output bit width input by the bit width confirmation circuit 201, when the data on one segment number is equal to the first preset threshold, the segment determination circuit 401 can output the segment number to the iteration initial value calculation circuit 402, so as to calculate the optimal iteration initial value, which is used to ensure newton iteration convergence. If the number of the divided segmented segments is more, the consumption of hardware resources is more, and the Newton iteration is faster.
The first preset threshold is obtained by calculation according to the number of the segmented segments and the output bit width.
In one specific implementation, setting N equal to 2 represents that the 2-th power root of the input binary number is to be computed, for example: if the input binary number is "10101110", if the input binary number is divided into 4 segments, and the data on each segment is composed of 2-bit data, the first preset threshold value may be set to be the binary number "11", and according to the first preset threshold value, the iteration initial value calculation circuit 402 may calculate to obtain the corresponding iteration initial value to be the binary number "1110".
In the embodiment, an output bit width is determined according to an input binary number in a sectional calculation mode, an optimal iteration initial value is further determined, the iteration initial value is brought into a newton iteration algorithm, and the root of the N times of the input binary number is obtained through calculation. The N-degree square root is applied to the conversion process of the color space, the Newton iteration times are reduced and the target precision is achieved through the obtained optimal iteration initial value, the storage space can be reduced, the hardware resource is further saved, the conversion of the color space of the image is easily realized through a digital circuit.
A second embodiment of the present invention relates to a circuit for calculating the square root of degree N. The second embodiment is substantially the same as the first embodiment, and mainly differs therefrom in that: the manner in which the use of the newton iteration circuit 102 to implement the computation of the square root of degree N is further refined.
Wherein the newton iteration circuit 102 is to: according to the iteration initial value and the input binary number, using a Newton iteration algorithm to perform the j-th calculation to obtain the N-th square root of the input binary number; judging whether the Newton iteration times j are equal to a second preset threshold value, if so, taking the N-time square root obtained by the iteration as the N-time square root of the input binary number, and ending the iteration; otherwise, continuing to perform the j +1 th iteration; wherein, the value range of j is an integer which is greater than or equal to 1 and less than or equal to B, B is an integer which is greater than or equal to 2, and B represents the preset total iteration times.
It should be noted that the preset total number B of iterations cannot exceed the maximum supportable number of iterations supported by the circuit for calculating the square root of the number N, where the maximum supportable number of iterations is determined according to the transistor resources in the circuit.
In one particular implementation, a flowchart for computing the root of the power N using newton's iteration is shown in fig. 5.
In step 601, the newton iteration circuit 102 obtains an iteration initial value and a binary number input by the initial value selection circuit 101, initially determines to perform newton iteration B times according to system requirements, and enters step 602.
In step 602, the newton iteration circuit 102 performs the j-th calculation using a newton iteration algorithm to obtain the N-th root of the input binary number, and then proceeds to step 603.
In step 603, the newton iteration circuit 102 determines whether the newton iteration number j is equal to a second preset threshold, if yes, go to step 604; otherwise, step 605 is entered.
In step 604, the newton iteration circuit 102 sets the N-th root obtained in the current iteration as the N-th root of the input binary number, and ends the iteration.
In step 605, the newton iteration circuit 102 calculates the next number of newton iterations: j +1, and then proceeds to step 602 to continue with the j +1 th iteration.
It should be noted that, by using the circuit for calculating the square root of the N times, the square root of the N times of the input binary number can be calculated quickly and accurately by applying a newton iteration algorithm. Wherein, for the accuracy requirement of the calculated N-th power root, a suitable newton iteration number may be selected, for example: under the conditions of low precision requirement and shortage of digital circuit resources, the iteration number B can be reduced, for example, 2 times or 1 time Newton iteration is selected to obtain the N-time root of the binary input of the input; under the conditions of high precision requirement and abundant digital circuit resources, the Newton iteration number B can be increased, and the precision of the N-th root of the calculation is further improved. For example, if it is determined that the 4 th root is calculated for the binary number "00111111000011110011", then 3 newton iterations are required for the binary number according to system requirements, and then the 4 th root of the binary number is "10110" is obtained. Since the transistor resources of the digital circuit are limited and the transistor resources with high quantity are high in price, in practical use, the proper transistor resources of the digital circuit can be properly selected according to the system requirements to realize the circuit for calculating the root of the power of the N.
In a specific implementation, if the number of iterations is 3, the N-th square root of the input binary number obtained by the circuit for calculating the N-th square root through calculation may be accurate to the 3 rd bit after the decimal point; if the iteration number is 4, the N-th square root of the input binary number obtained by the circuit for calculating the N-th square root through calculation can be accurate to the 4 th bit after the decimal point, and so on.
In an actual system, an optimal iteration value is selected by judging the size of an input binary number, if the division of a segmentation interval is smaller, the iteration number can be reduced under the same precision of obtaining an N-th-order root result, and it should be noted that if the division of the segmentation interval is too small, the storage space is increased, and further hardware resources are consumed, so that the comprehensive consideration needs to be combined with the actual situation.
Wherein the newton iteration circuitry 102 is further configured to: before the newton iterative algorithm is used to calculate the N-th root of the input binary number, the input binary number and the iterative initial value determined by the initial value selection circuit 101 are synchronized.
In a specific implementation, since the iteration initial value is determined according to the input binary number, a certain calculation period is required to synchronize with the input binary number, and after the input binary number and the iteration initial value determined by the initial value selection circuit 101 are subjected to synchronization processing, the N-th root of the input binary number can be calculated by using a newton iteration algorithm.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.
Claims (6)
1. A circuit for calculating a square root of degree N, comprising: the circuit comprises an initial value selection circuit and a Newton iteration circuit which are electrically connected in sequence, wherein the initial value selection circuit comprises: a bit width confirmation circuit and a calculation circuit which are electrically connected in sequence;
the bit width confirmation circuit is used for obtaining the bit width of the iteration initial value according to the bit number of the input binary number and the bit width of the input binary number;
the calculating circuit is configured to perform segmented calculation on the input binary number according to the bit width of the iteration initial value determined by the bit width confirming circuit and a first preset threshold value, so as to obtain an iteration initial value;
the Newton iteration circuit is used for calculating and obtaining the root of N times of the input binary number by using a Newton iteration algorithm according to the iteration initial value and the input binary number, wherein N is an integer greater than or equal to 2;
the computation circuit is to: dividing binary numbers corresponding to the output bit width into L sections, and judging whether data on the ith section is equal to a first preset threshold value or not aiming at the ith section; if yes, outputting the segmentation segment number i to the iteration initial value calculation circuit for calculating the iteration initial value; otherwise, judging whether the data on the i-1 th subsection number is equal to a first preset threshold value or not; wherein, L is an integer which is more than or equal to 2, and the value range of i is a positive integer which is less than or equal to L;
and the first preset threshold is obtained by calculation according to the number of the segmented segments and the output bit width.
2. The circuit for calculating a square root of degree N according to claim 1, wherein the bit width confirmation circuit comprises: a judgment digit circuit and a bit width calculating circuit which are electrically connected in sequence;
the judgment bit number circuit is used for judging whether the bit number of the input binary number is an integral multiple of N or not, and if so, taking the bit width of the input binary number as the output bit width; otherwise, obtaining a new binary number and the bit width of the new binary number, and taking the bit width of the new binary number as the output bit width; outputting the output bit width to the bit width calculating circuit;
and the bit width calculating circuit is used for obtaining the bit width of the iteration initial value according to the output bit width output by the judgment bit number circuit and the N.
3. The circuit for calculating the square root of degree N according to claim 2, wherein the calculation circuit comprises: the device comprises a segmentation judgment circuit and an iteration initial value calculation circuit which are electrically connected in sequence;
the segment judgment circuit is configured to judge whether data on at least one segment of the binary number corresponding to the output bit width is equal to a first preset threshold according to the binary number corresponding to the output bit width and the output bit width, and if so, obtain a bit width of the data on the segment, where the bit width of the data on the segment is less than or equal to the output bit width;
the iteration initial value calculation circuit is used for obtaining the iteration initial value according to the data on the segment determined by the segment judgment circuit.
4. The circuit for calculating the square root of degree N according to claim 2, wherein the decision bit number circuit is configured to:
judging whether the digit of the input binary number is an integral multiple of N, if so, obtaining the bit width of the input binary number; otherwise, generating a new binary number, enabling the digit of the new binary number to meet the integral multiple of N, and taking the bit width of the new binary number as the output bit width.
5. The circuit for computing a square root of degree N of claim 1, wherein the newton iteration circuit is configured to:
according to the iteration initial value and the input binary number, performing j-th calculation by using a Newton iteration algorithm to obtain a square root of the input binary number for N times;
judging whether the Newton iteration times j are equal to a second preset threshold value, if so, taking the N-th power root obtained by the iteration as the N-th power root of the input binary number, and ending the iteration; otherwise, continuing to perform the j +1 th iteration; wherein the value range of j is an integer greater than or equal to 1 and less than or equal to B, B is an integer greater than or equal to 2, and B represents the preset total iteration number.
6. The circuit for computing a square root of degree N of claim 1, wherein the newton iteration circuit is further configured to: and before the N-th root of the input binary number is calculated by using a Newton iterative algorithm, the input binary number and the iterative initial value determined by the initial value selection circuit are subjected to synchronous processing.
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