CN109542392A - Low-power consumption weighted sum circuit based on memristor crossed array - Google Patents
Low-power consumption weighted sum circuit based on memristor crossed array Download PDFInfo
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- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
Abstract
The invention belongs to technical field of integrated circuits, specially a kind of low-power consumption weighted sum circuit based on memristor crossed array.Weighted sum circuit and a current sampling circuit of the circuit of the present invention by a tradition based on resistive type memory crossed array are constituted；Its work is divided into two stages, and the first stage is precharge, and second stage is weighted sum and current sample；The present invention realizes weighted sum operation to one group of input voltage using the crossed array of resistive type memory, as a result by electric current and in the form of characterize, and charge storage by electric current and is converted into using current sample.Compared to traditional method, the present invention can shorten the duration of direct current in weighted sum operation, advantageously reduce power consumption.
Description
Technical field
The invention belongs to microelectronics technologies, and in particular to it is a kind of based on memristor crossed array low-power consumption weighting ask
And circuit.
Background technique
In 2017 International Solid State Circuits Conference (ISSCC), professor Verhelst from Belgian Univ Louvain refers to
Out, deep learning will become trend in Embedded Application.Because being embedded in wearable device, Internet of Things (IoT) and mobile phone etc.
Formula application needs to analyze the collected data of sensor, to obtain the use of user to improve user experience
The information such as habit.The often interference by factors such as complicated external environment, emergency cases of the collected data of sensor, it is right
This traditional signal processing technology and machine learning often fall into chaos, and deep learning is capable of providing reliable and robust
(robust) analysis.But embedded device relies on battery to power mostly, and the capacity of battery and service life (charge and discharge number)
It is all limited, reduction chip power-consumption, which helps to extend, uses time and battery life.Therefore, run the low-power consumption of hardware for
Embedded deep learning is using extremely important.From quantization angle, Embedded Application requires the energy consumption efficiency (efficiency) of deep learning
The multiply-add operand that every watts carry out is consumed more than 100G ops/W(), even up to 1T ops/W.
Traditional hardware chip (CPU&GPU) is not able to satisfy requirement of the embedded deep learning to low-power consumption.Tradition is used
In the hardware chip of deep learning be mainly CPU(central processing unit) and GPU(graphics processor).The too many area of cpu chip
With in complicated control logic, and the unit that is used to calculate and few, and deep learning is it is desirable that a large amount of concurrent operations,
Its control stream is simultaneously uncomplicated.Compared to CPU, the control stream in GPU is simpler, and most of chip area is all used as operation, and adopts
With SIMT(single instruction stream multithreading) framework, can be realized high performance parallel computation.However, GPU cannot reduce memory access
It asks number, accesses the memory (DRAM) outside piece every time all along with energy consumption, this allows for GPU and can not apply be important to
Seek the embedded occasion of low-power consumption.From the angle of quantization, the efficiency of CPU is also far smaller than 10G ops/W at present, GPU also less than
100 G ops/W。
For the big problem of conventional hardware power consumption, primary solutions are design specialized framework (specialized at present
Architecture).The characteristics of specific practice is according to deep learning operation, using mature digital integrated circuit technology, if
Count ASIC(specific integrated circuit), Accelerator(accelerator) or Custom Processor(customized processor), to mention
Degree of parallelism that elevator is calculated simultaneously is reduced to the access times of memory, to improve the efficiency of deep learning operation.But special frame
Structure still has the waste of power consumption, because weighted sum needs a large amount of MAC(multiplicaton addition unit), power consumption highly significant, in addition, power
Value is still stored on the DRAM outside the piece or SRAM of on piece, also brings along larger function to moving for weight in calculating process
Consumption.
The characteristic of memristor (memristor) provides important channel to reduce the power consumption of deep learning.As " the 4th kind
Passive device ", memristor show similar human nervous system synapse(cynapse in device level) characteristic, resistance value can
Gradual change supports STDP (spike-timing dependent plasticity) study mechanism, moreover, memristor can
State logic (stateful logic) operation is carried out, realizes that in-memory computing(is calculated in storage).In circuit
Level, the crossbar array of memristor can be realized the product of matrix-vector, and essence is weighted sum operation, vector
Be equivalent to the input of crossbar line direction, and weight be in the form of memristor conductance (inverse of resistance value) non-volatilely
Be stored in crossbar array, output be crossbar column direction electric current and.The advantages of this weighted sum circuit is nothing
MAC is needed, and power consumption can be reduced without the carrying to weight in operation.Nanyang Technolohy University in 2016 for the first time
It proposes to accelerate machine learning using the crossbar array of memristor, specific practice is with using two layers
Memristor, one layer is used to store image data, and one layer of acceleration for being used to realize vector-matrix multiplication finally makes machine learning
Energy Efficiency Ratio ASIC promote 10 times or more.
Since the convolution operation of deep learning convolutional neural networks (CNNs) is also weighted sum in itself, can also be used
The advantage of memristor low-power consumption in terms of realizing weighted sum circuit reduces the power consumption of deep learning.But deep learning
Different from general machine learning although belonging to machine learning in itself, deep learning CNNs is in structure comprising very much
Level (at most up to several hundred layers), and the neural network of general machine learning in structure only there are three level (input, hidden layer,
Output).Existing weighted sum circuit and speeding scheme both for general machine learning neural network, and for depth
CNNs is practised, existing weighted sum circuit power consumption is still bigger.Current weighted sum be all by input voltage and
The weight (inverse of memristor resistance value) that crossbar array vertical direction one arranges synapse carries out product, obtains electric current,
Then it sums to electric current.In entire calculating process, each input can introduce direct current, and the duration is longer, meeting in this way
Bring bigger power consumption, the efficiency of influence depth study.
Summary of the invention
That the purpose of the present invention is to provide a kind of circuit power consumptions is small, study efficiency is high based on the low of memristor crossed array
Power consumption weighted sum circuit.
Low-power consumption weighted sum circuit proposed by the present invention based on memristor crossed array, using resistive type memory
Crossed array weighted sum operation is realized to one group of weighted input summing circuit voltage, as a result by electric current and in the form of characterize, and
Charge storage by electric current and is converted into using current sample.Compared to traditional method, the present invention can shorten in weighted sum operation
The duration of direct current, advantageously reduce power consumption.
Low-power consumption weighted sum circuit proposed by the present invention based on memristor crossed array is based on resistive class by a tradition
The weighted sum circuit of type memory crossover array and a current sampling circuit are constituted.
The above-mentioned low-power consumption weighted sum circuit based on memristor crossed array, work are divided into two stages, the first rank
Section is precharge, and second stage is weighted sum and current sample.
The resistive type memory has two-end structure, can be phase transition storage, ferroelectric memory, magnetic storage
Device, resistance-variable storing device or other any memories with resistance value height characterization logic value.The crossed array of resistive type memory
It is to be crossed one another to constitute by the interconnection line of the interconnection line of several horizontal directions and several vertical directions, each infall has a resistance
Become type memory cells, in the both ends of the resistive type memory cells, one end connects the interconnection line of horizontal direction, the other end
Connect the interconnection line of vertical direction.The input voltage of weighted sum operation is consequently exerted at the crossed array of resistive type memory
One end of horizontal direction interconnection line.
The weighted sum operation is by the crossed array vertical direction of one group of input voltage and resistive type memory
A column resistive type memory cells conductance distinguish product, as a result from the friendship of resistive type memory in the form of electric current sum
The corresponding interconnection line output of array vertical direction same row is pitched to obtain.
In the present invention, the current sampling circuit can be a NMOS transistor, and the source of the NMOS transistor connects
Ground, drain terminal connect one interconnection line of crossed array vertical direction of resistive type memory, and grid end passes through a switch connection leakage
End；It is shown in Figure 2.The switch has just been begun to turn off, so in the first stage shutdown of summing circuit work in second stage
After be connected to, finally turn off again.
In the present invention, the current sampling circuit also may include: a switch, first NMOS transistor and second
A NMOS transistor.Wherein, the drain electrode connection crossed array vertical direction of one end of switch and first NMOS transistor is mutual
Line, the other end of switch connect the grid of first NMOS transistor and second NMOS transistor, first NMOS crystal
The source electrode of pipe is grounded, and the source electrode and drain electrode of second NMOS transistor is all grounded；The low-power consumption weighted sum circuit, work
It is divided into two steps: the first step as process, switch is closed, that is, is in connected state, the electric current of crossed array weighted sum and flows into the
The drain electrode of one NMOS transistor, while the grid voltage phase of the grid of first NMOS transistor and second NMOS transistor
It should increase；Second step, switch are opened, that is, are in an off state, the grid and second NMOS crystal of first NMOS transistor
The grid voltage of pipe can keep a period of time, characterize the size of electric current sum, i.e. realization current sample.
In the present invention, the current sampling circuit also may include: first NMOS transistor (is used as gating), and one
Amplifier and second NMOS transistor, a switch, third NMOS transistor and four NMOS transistors；Wherein,
The drain electrode of one NMOS transistor connects crossed array Vertical Square frontad interconnection line, and the grid of first NMOS transistor connects choosing
Messenger, the drain electrode of the positive input and second NMOS transistor of the source electrode connection amplifier of first NMOS transistor,
The negative input of amplifier connects a reference voltage, and the output of amplifier connects the grid of second NMOS transistor, the
One end of the source electrode connection switch of two NMOS transistors and the drain electrode of third NMOS transistor, the other end connection the of switch
The grid of three NMOS transistors and four NMOS transistors, the source electrode ground connection of third NMOS transistor, the 4th NMOS
The source electrode and drain electrode of transistor is all grounded.The low-power consumption weighted sum circuit, the course of work are divided into two steps: the first step,
The grid of first NMOS transistor connects high level, is in strobe state, meanwhile, switch closes to be in connected state, hands over
Pitch the electric current of array weight summation and followed by first NMOS transistor, second NMOS transistor and third NMOS crystalline substance
The drain electrode of body pipe and source electrode, while the grid of third NMOS transistor and the grid voltage of four NMOS transistors accordingly rise
It is high；Second step, switch are opened, that is, are in an off state, the grid of first NMOS transistor and second NMOS transistor
Grid voltage can keep a period of time, characterize the size of electric current sum, can turn off first NMOS gate tube later, thus
Realize current sample.
Detailed description of the invention
Fig. 1 is traditional weighted sum circuit based on resistive type memory crossed array.
Fig. 2 is that first, the weighted sum circuit implementation based on resistive type memory crossed array is added after current sample
Example.
Fig. 3 is that first, the weighted sum circuit implementation based on resistive type memory crossed array is added after current sample
The working sequence of example.
Fig. 4 is that second, the weighted sum circuit implementation based on resistive type memory crossed array is added after current sample
Example.
Fig. 5 is that second, the weighted sum circuit implementation based on resistive type memory crossed array is added after current sample
The working sequence of example.
Figure label: 100 be traditional weighted sum circuit based on resistive type memory crossed array；101-104 points
Not Wei input line, weighted sum operation voltage apply port；111-113 is respectively output line, weighted sum operation electric current
Output port；121 for 111 output line weighted sums electric current and.
200 be first reality of the weighted sum circuit based on resistive type memory crossed array after current sample is added
Apply the circuit diagram of example；201-204 is respectively input line, the port that weighted sum operation voltage applies；211-213 is respectively to export
Line, the output port of weighted sum operation electric current；221 for 211 output line weighted sums electric current and；222 be control switch SW；
223 be the NMOS transistor of electric current sampling action；224 are to provide the NMOS transistor of parasitic capacitance；225 be 223 and 224
Grid；226 be earth signal.
301 be the work wave of one embodiment control switch SW；302 be the work of the grid of NMOS transistor 223 and 224
Make waveform.
400 be first reality of the weighted sum circuit based on resistive type memory crossed array after current sample is added
Apply the circuit diagram of example；401-404 is respectively input line, the port that weighted sum operation voltage applies；405-407 is respectively to export
Line, the output port of weighted sum operation electric current；408 be precharging signal；409-411 is precharge NMOS transistor；412 are
Power supply signal；413 be gate tube；414 be the enable signal of gate tube；415 and 416 point half be voltage adjust amplifier forward direction
Input terminal and negative input；417 for 405 output line weighted sums electric current and；418 be the crystal of starting voltage adjustment effect
Pipe；419 be the drain terminal of current sampling transistor 421；420 be control switch SW；421 be the NMOS crystalline substance of electric current sampling action
Body pipe；423 are to provide the NMOS transistor of parasitic capacitance；422 be 421 and 423 grid；424 be earth signal.
Specific embodiment
The present invention is described more fully below in association with being shown in reference implementation example, the present invention provides preferred implementation
Example, but should not be considered limited to embodiment set forth herein.On the contrary, thesing embodiments are provided so that the displosure is thorough
With it is complete, the scope of the present invention is entirely delivered to those skilled in the relevant art.
It is the schematic diagram of idealized embodiments of the invention with reference to figure herein, embodiment shown in the present invention should not be recognized
For the specific shape for being only limitted to region shown in figure.
Fig. 1 gives traditional weighted sum circuit based on resistive type memory crossed array, and input voltage is applied to
The interconnection line 101-104 of horizontal direction, after the product of input voltage and resistive type memory cells voltage, electric current and
Interconnection line 111-113 output from vertical direction.In Fig. 1, the electric current on interconnection line 111 and 121 are only provided.Conventional weight is asked
With the shortcomings that be, in order to maintain output electric current and, input voltage needs to be applied on crossed array, bring long period direct current,
Power consumption and energy consumption are all bigger.
Fig. 2 is that first, the weighted sum circuit implementation based on resistive type memory crossed array is added after current sample
Example.Compared to Figure 1, Fig. 2 joined by NMOS transistor 223, switch control 222 and provide the NMOS crystal of MOS parasitic capacitance
Pipe 224 constitutes current sampling circuit.Fig. 3 gives the weighting based on resistive type memory crossed array after addition current sample
The working sequence of summing circuit one embodiment.While input voltage is applied to input line 201-204, control switch 222
Conducting, the electric current of such weighted sum and 221 are just adopted by the progress electric current of NMOS transistor 223 connected with diode fashion
Sample, later, control switch 222 disconnect, and electric current and 221 is stored in node 225(as illustrated at 302 in the form of a charge), it is applied to
The input voltage of input line 201-204 can disconnect, in this way, there is no direct current presence in weighted sum circuit.As it can be seen that passing through
The direct current duration of current sample, weighted sum circuit can substantially shorten, and then reduce the power consumption of entire circuit.
Fig. 4 is that second, the weighted sum circuit implementation based on resistive type memory crossed array is added after current sample
Example.Compared with one embodiment, the circuit of second embodiment increases precharge transistor 409-411, gate tube 414 again
With the voltage regulator being made of transistor 418 and amplifier 426.Fig. 5 is to be stored after current sample is added based on resistive type
The working sequence of second embodiment of weighted sum circuit of device crossed array.Entire work is divided into two stages: first stage,
Effectively, precharge NMOS transistor 409-411 respectively charges to output line 405-406 a certain with reference to electricity precharging signal 408
Press Vref；Second stage, while input voltage is applied to input line 401-404, gating signal 414 is effective, control switch 420
Conducting, under the action of voltage regulator, output line 405 is maintained at voltage Vref, and the electric current of such weighted sum and 417 just lead to
It crosses and current sample is carried out with the NMOS transistor 421 of diode fashion connection, later, control switch 420 disconnects, and believes with backgating
Numbers 414 failures, electric current and 417 will be stored in node 422(as shown in 505 in the form of a charge), it is applied to input line 401-
404 input voltage can disconnect, in this way, there is no direct current presence in weighted sum circuit.As it can be seen that by current sample,
The direct current duration of weighted sum circuit can substantially shorten, and then reduce the power consumption of entire circuit.
Claims (4)
1. a kind of low-power consumption weighted sum circuit based on memristor crossed array, which is characterized in that be based on resistive by a tradition
The weighted sum circuit of type memory crossed array and a current sampling circuit are constituted；Its work is divided into two stages, the
One stage was precharge, and second stage is weighted sum and current sample；
The resistive type memory has two-end structure, is that phase transition storage, ferroelectric memory, magnetic memory, resistive are deposited
Reservoir or other any memories with resistance value height characterization logic value；If the crossed array of resistive type memory is by solid carbon dioxide
Square to interconnection line and the interconnection lines of several vertical directions cross one another composition, each infall has a resistive type storage
Device unit, in the both ends of the resistive type memory cells, one end connects the interconnection line of horizontal direction, the vertical side of other end connection
To interconnection line；The input voltage of weighted sum operation is applied to the horizontal direction interconnection of the crossed array of resistive type memory
One end of line；
The weighted sum operation is one of the crossed array vertical direction by one group of input voltage Yu resistive type memory
The conductance of column resistive type memory cells distinguishes product, as a result from the intersecting maneuver of resistive type memory in the form of electric current sum
The corresponding interconnection line output of column vertical direction same row obtains.
2. the low-power consumption weighted sum circuit according to claim 1 based on memristor crossed array, which is characterized in that institute
The current sampling circuit stated is a NMOS transistor, the source ground connection of the NMOS transistor, drain terminal connection resistive type storage
One interconnection line of crossed array vertical direction of device, grid end connect drain terminal by a switch；The switch, in summing circuit work
The first stage of work turns off, and has just begun to turn off in second stage, has then been connected to, finally turns off again.
3. the low-power consumption weighted sum circuit according to claim 1 based on memristor crossed array, which is characterized in that institute
The current sampling circuit stated a, comprising: switch, first NMOS transistor and second NMOS transistor, wherein switch
The interconnection line of the drain electrode connection crossed array vertical direction of one end and first NMOS transistor, the other end connection first of switch
The grid of a NMOS transistor and second NMOS transistor, the source electrode ground connection of first NMOS transistor, second NMOS crystalline substance
The source electrode and drain electrode of body pipe is all grounded；
The low-power consumption weighted sum circuit, the course of work are divided into two steps: the first step, and switch is closed, that is, are in connected state
State, the electric current of crossed array weighted sum and the drain electrode for flowing into first NMOS transistor, while first NMOS transistor
The grid voltage of grid and second NMOS transistor accordingly increases；Second step, switch are opened, that is, are in an off state, first
The grid voltage of the grid of a NMOS transistor and second NMOS transistor is kept for a period of time, characterizes the size of electric current sum,
Realize current sample.
4. the low-power consumption weighted sum circuit according to claim 1 based on memristor crossed array, which is characterized in that
The current sampling circuit, comprising: first NMOS transistor is used as gating, an amplifier and second NMOS crystal
Pipe, a switch, third NMOS transistor and four NMOS transistors, wherein the drain electrode of first NMOS transistor connects
Crossed array Vertical Square frontad interconnection line is connect, the grid of first NMOS transistor connects gating signal, first NMOS crystal
The drain electrode of the positive input and second NMOS transistor of the source electrode connection amplifier of pipe, the negative input connection of amplifier
One reference voltage, the grid of output second NMOS transistor of connection of amplifier, the source electrode of second NMOS transistor connect
One end of switch and the drain electrode of third NMOS transistor are connect, the other end of switch connects third NMOS transistor and the 4th
The grid of NMOS transistor, the source electrode ground connection of third NMOS transistor, the source electrode and drain electrode of four NMOS transistors all connect
Ground；
The low-power consumption weighted sum circuit, the course of work are divided into two steps: the first step, the grid of first NMOS transistor
Connect high level, be in strobe state, meanwhile, switch close to be in connected state, the electric current of crossed array weighted sum and
Followed by first NMOS transistor, drain electrode and the source electrode of second NMOS transistor and third NMOS transistor, simultaneously
The grid of third NMOS transistor and the grid voltage of four NMOS transistors accordingly increase；Second step, switch are opened, i.e.,
It being in an off state, the grid voltage of the grid of first NMOS transistor and second NMOS transistor is kept for a period of time,
Characterize the size of electric current sum；First NMOS gate tube is turned off later, to realize current sample.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110390074A (en) * | 2019-07-01 | 2019-10-29 | 浙江大学 | A kind of computing system of resistive memory |
| CN111553415A (en) * | 2020-04-28 | 2020-08-18 | 哈尔滨理工大学 | Memristor-based ESN neural network image classification processing method |
| CN112700810A (en) * | 2020-12-22 | 2021-04-23 | 电子科技大学 | CMOS (complementary Metal oxide semiconductor) inductive-storage integrated circuit structure integrating memristor |
| WO2021103122A1 (en) * | 2019-11-29 | 2021-06-03 | 珠海复旦创新研究院 | Half adder based on memristor array, and full adder and multiplier |
| WO2023115883A1 (en) * | 2021-12-21 | 2023-06-29 | 上海集成电路装备材料产业创新中心有限公司 | Rram array summation operation circuit and method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101271148A (en) * | 2008-05-16 | 2008-09-24 | 湖南大学 | Switching current circuit tolerance confirming method based on group transconductance sensibility |
| CN101500358A (en) * | 2008-01-28 | 2009-08-05 | 杭州士兰微电子股份有限公司 | Output current compensation circuit of LED driving circuit |
| JP2013066097A (en) * | 2011-09-20 | 2013-04-11 | New Japan Radio Co Ltd | Sampling circuit |
| US20180089146A1 (en) * | 2016-09-29 | 2018-03-29 | Hewlett Packard Enterprise Development Lp | Convolution Accelerators |
| US20180253643A1 (en) * | 2017-03-03 | 2018-09-06 | Hewlett Packard Enterprise Development Lp | Analog multiplier-accumulators |
| US20180309451A1 (en) * | 2017-04-24 | 2018-10-25 | The Regents Of The University Of Michigan | Sparse Coding With Memristor Networks |
-
2018
- 2018-11-09 CN CN201811329936.3A patent/CN109542392A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101500358A (en) * | 2008-01-28 | 2009-08-05 | 杭州士兰微电子股份有限公司 | Output current compensation circuit of LED driving circuit |
| CN101271148A (en) * | 2008-05-16 | 2008-09-24 | 湖南大学 | Switching current circuit tolerance confirming method based on group transconductance sensibility |
| JP2013066097A (en) * | 2011-09-20 | 2013-04-11 | New Japan Radio Co Ltd | Sampling circuit |
| US20180089146A1 (en) * | 2016-09-29 | 2018-03-29 | Hewlett Packard Enterprise Development Lp | Convolution Accelerators |
| US20180253643A1 (en) * | 2017-03-03 | 2018-09-06 | Hewlett Packard Enterprise Development Lp | Analog multiplier-accumulators |
| CN108536422A (en) * | 2017-03-03 | 2018-09-14 | 慧与发展有限责任合伙企业 | analog multiplier-accumulator |
| US20180309451A1 (en) * | 2017-04-24 | 2018-10-25 | The Regents Of The University Of Michigan | Sparse Coding With Memristor Networks |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110390074A (en) * | 2019-07-01 | 2019-10-29 | 浙江大学 | A kind of computing system of resistive memory |
| WO2021103122A1 (en) * | 2019-11-29 | 2021-06-03 | 珠海复旦创新研究院 | Half adder based on memristor array, and full adder and multiplier |
| CN111553415A (en) * | 2020-04-28 | 2020-08-18 | 哈尔滨理工大学 | Memristor-based ESN neural network image classification processing method |
| CN111553415B (en) * | 2020-04-28 | 2022-11-15 | 宁波工程学院 | Memristor-based ESN neural network image classification processing method |
| CN112700810A (en) * | 2020-12-22 | 2021-04-23 | 电子科技大学 | CMOS (complementary Metal oxide semiconductor) inductive-storage integrated circuit structure integrating memristor |
| CN112700810B (en) * | 2020-12-22 | 2023-06-30 | 电子科技大学 | CMOS sense-memory integrated circuit structure integrating memristors |
| WO2023115883A1 (en) * | 2021-12-21 | 2023-06-29 | 上海集成电路装备材料产业创新中心有限公司 | Rram array summation operation circuit and method |
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