CN101271148A - Switching current circuit tolerance confirming method based on group transconductance sensibility - Google Patents

Abstract

The invention discloses a determining method of switched-current circuit tolerance on the basis of group transconductance sensitivity, which is characterized in that: the determining method comprises the following steps: 1) current calibration: a switched-current storage unit is taken as a basis for constructing a switched-current circuit, thus calculating the width to length ratio of channels of transistors and realizing the calibration of the current; 2) getting the hormalized transconductance value according to the current calibration: the transistor transconductance value of the input end of a sampling and maintaining circuit is taken as the reference, the values are given to other transistor hormalized transconductance values according to the current calibration; 3) carrying out the grouping of the switch transistors according to the hormalized transconductance value: all the transistors are grouped by setting the transistors with the same hormalized transconductance value into one group; 4) the sensitivity and the deviation of the group parameters on the parameters of the circuit performances are calculated; 5) the deviation is added or subtracted on a standard curve to obtain the error tolerance. The method can be used for carrying out the test of the fault defects of the analog integrated switched-current circuit, and the efficiency is high.

Description

Switched-Current Circuit tolerance based on group's transconductance sensitivity is determined method

Technical field

The present invention relates to the simulation integrated switch current circuit tolerance and determine method, particularly a kind of Switched-Current Circuit tolerance based on group's transconductance sensitivity is determined method, can be used for the simulation integrated switch current circuit is carried out the accident defect test.

Background technology

The traditional fault model of mimic channel is divided into bust or hard fault (analog component open circuit or short circuit) and parameter fault or is called soft fault (parameter value of analog device change fully exceed its range of tolerable variance cause unacceptable performance degradation).Have quite complicated relation between the mimic channel input and output signal, many mimic channels are nonlinear system, promptly adopt mosfet transistor as amplifier, the non-constant width of circuit parameter value variation range.Deterministic models are invalid to mimic channel.Thereby signal is to determine that with the tolerance interval around the normal value deviation of IC manufacturing process has been determined acceptable signal value tolerance by normal value.

Switched-Current Circuit only adopts MOS transistor as switch, mutual conductance and current source usually.(mutual conductance is the ratio of little variable of little variable of MOS transistor drain current and the gate source voltage that causes this variation for Switched-Current Circuit).Input capacitance C _GsStored charge is by corresponding transistor storaging current.This technology relies on accurate current mirror to realize sample data structures.Because the consistance of switching current transistor technology, different mutual conductances and bias current sources all are to obtain by the channel width that changes metal-oxide-semiconductor, so the variation of channel width-over-length ratio will produce considerable influence to circuit performance.And the also main reason of transistor mismatch effect just of channel width-over-length ratio (W/L).The channel width-over-length ratio that is caused by factors such as technologies changes the deviation that not only can cause transconductance value, also can cause the error of the calibration of electric current, produces mismatch effects and response variance.Thereby determine that the acceptable signal value range of tolerable variance of this distinctive response variance is all is the key factor that must consider when Switched-Current Circuit design and test.This deviation can detect by sensitivity analysis.

Summary of the invention

Technical matters to be solved by this invention is to provide a kind of Switched-Current Circuit tolerance based on group's transconductance sensitivity to determine method.

The present invention solves the problems of the technologies described above the technical scheme that is adopted to be:

A kind of Switched-Current Circuit tolerance based on group's transconductance sensitivity is determined method, it is characterized in that, may further comprise the steps:

1) electric current calibration: with the switched current memory cells is the base configuration Switched-Current Circuit, calculates the transistor channel breadth length ratio, realizes the calibration of electric current;

2), according to electric current calibration normalization transconductance value: the sampling hold circuit transistor transconductance value with input end is a benchmark, and other transistor normalization transconductance value are carried out assignment according to the electric current calibration;

3), switching transistor is carried out group by the normalization transconductance value: promptly the standard that is made as a group according to the transistor of identical normalization transconductance value is divided into groups all transistors;

4), calculate sensitivity and the deviation of group parameters about circuit performance parameters;

5), add or deduct deviation and obtain error margin from typical curve.

Described Switched-Current Circuit is delayer, integrator, differentiator, biquad filter and other practical circuits.

Described step 4) is:

Computing node voltage E _{L, mk}(z) for the mutual conductance G of the input branch road a that is operated in out of phase with output branch road b _Mab(z) sensitivity is:

$S_{G_{\mathrm{mab}}}^{E_i}=\frac{G_{\mathrm{mab}}}{E_i}\underset{m=1}{\overset{f}{\mathrm{\Σ}}}\underset{k=1}{\overset{f}{\mathrm{\Σ}}}\underset{l=1}{\overset{f}{\mathrm{\Σ}}}{V}_{a,\mathrm{lk}}{\hat{V}}_{b,\mathrm{lm}}$

V in the formula _{A, lk}Be the voltage on the branch road a in phase place l, its input service is at phase place k,

It is the corresponding voltage in the adjoint network;

Parameter E _l(z) the maximum tolerance deviation to component parameters x (z) is:

$\mathrm{\&Delta;}\left|E_i\left(z\right)\right|={\mathrm{<figure-callout\; id="0"\; label="P"\; filenames="A20081003131300191.png,A20081003131300201.png"\; state="\{\{state\}\}">P</figure-callout>}}_0\&times;\sqrt{\underset{i}{\mathrm{\&Sigma;}}{\left(\mathrm{Re}{S}_{G_{\mathrm{mi}}}^{E_i\left(z\right)}\right)}^2}$ Or

$\mathrm{\&Delta;}\left|E_i\left(z\right)\right|={\mathrm{<figure-callout\; id="0"\; label="P"\; filenames="A20081003131300191.png,A20081003131300201.png"\; state="\{\{state\}\}">P</figure-callout>}}_0\&times;8.686\sqrt{\underset{i}{\mathrm{\&Sigma;}}{\left(\mathrm{Re}{S}_{G_{\mathrm{mi}}}^{E_i\left(z\right)}\right)}^2}---\left(\mathrm{dB}\right)$

P wherein ₀Be the stochastic error of a given device parameters x of group (z), 0.868 is the db-loss constant.The db-loss coefficient need be in formula, added when promptly adopting the decibel expression, otherwise this coefficient needn't be added.

Beneficial effect:

Beneficial technical effects of the present invention is: the present invention is at first according to the peculiar structure of switching current, the cmos element of forming circuit is classified by the method for group's sensitivity analysis, calculate absolute error or statistical error in the mode of group, finally determine the circuit tolerance border.To improve the efficient of matrix analysis widely in the analysis of carrying out error margin.

Description of drawings

Fig. 1 is the method flow diagram that decomposes based on multi-scale wavelet in the time-domain and frequency-domain among the present invention and the Neural Network Based Nonlinear mapping is concluded carries out the accident defect test to the simulation integrated switch current circuit;

Fig. 2 SI basic unit of storage (a) SI basic unit of storage circuit (b) clock waveform;

The topological circuit figure of Fig. 3 switching capacity biquadratic function;

Fig. 4 is used for the switching current biquadratic joint of 6 rank chebyshev low-pass filters;

Fig. 56 rank switching current chebyshev low-pass filters;

Fig. 66 rank switching current chebyshev low-pass filter gain and tolerance (a) stochastic errors 1% thereof, (b) stochastic error 5%);

The statistic bias of Fig. 7 mutual conductance mismatch; (transverse axis is relative mismatch (%), and the longitudinal axis is statistic bias (dB))

Fig. 8 a group mutual conductance mismatch sensitivity real part; (transverse axis is relative mismatch (%), and the longitudinal axis is the sensitivity real part)

The gain tolerance upper and lower limit of Fig. 9 mismatch.

Embodiment

Below in conjunction with figure and embodiment the invention will be further described.

Embodiment 1:

As Fig. 1, determine may further comprise the steps based on the Switched-Current Circuit tolerance of group's transconductance sensitivity:

1) cmos current that constitutes Switched-Current Circuit is calibrated.Based on switched current memory cells, adopt mode such as cascade and the transistor channel breadth length ratio is calculated, realize the calibration of electric current, be the basic skills that constructs various practical circuits such as delayer, integrator, differentiator and biquad filter joint.

Switch, current mirroring circuit that Switched-Current Circuit (SI circuit) was controlled by MOS storage tube, the time that is subjected to constitute, utilize the processing of the charge-storage effect realization of stray capacitance between MOS device grid source to current signal, so in the SI circuit, do not need the linearity electric capacity of floating, and on principle, have the low supply voltage operating potential, can adopt standard VLSI CMOS technology to realize.Current memory is the basis that constitutes the SI circuit, as shown in Figure 2

SI structure shown in Fig. 2 (a) can be at single transistor T ₁The middle current memory that realizes, each clock waveform is shown in Fig. 2 (b).Switch S ₁, S ₂Be subjected to clock φ ₁Control, S ₃Then by φ ₂Control is at clock φ ₁The phase of promptly taking a sample, switch S ₁, S ₂Closure, so input current i is added on the bias current J, J+i is to T ₁The grid of pipe-source capacitor C charging are as gate source voltage V _GsSurpass threshold voltage V _TThe time, transistor T ₁Conducting is after C charges fully, that is:

$V_{\mathrm{gs}}\&ap;V_T+\sqrt{\frac{J+i}{k^{\&prime;}W/L}}$ Wherein k ' is called the intrinsic conduction factor, and $k^{\&prime;}=\frac{\mathrm{\&mu;}{C}_{\mathrm{ox}}}{2}(\mathrm{\&mu;A}/V^2).$ Wherein μ is a carrier mobility, C _OxBe unit-area capacitance, ^W/ _LBe the transistor breadth length ratio.

J+i all flows into T ₁Drain electrode.At clock φ ₂Promptly keep phase, S mutually ₁, S ₂Disconnect, and S ₃Closure, keep V on the capacitor C of grid source this moment _GsValue, thus make T ₁Drain current is kept J+i, at T ₁On the pipe drain node by Kirchhoff's current law (KCL) output current: i as can be known _o=-i is at whole φ ₂Finish storage mutually to sampling current i.This shows, pass through transistor T ₁Grid-source stray capacitance C goes up the storage of electric charge, can finish sampling and maintenance to input current.Certainly in this SI memory circuit of realizing by transistor, output i _oCan only be at φ ₂Value is arranged,, can adopt current copy device structure, promptly increase transistor T if will obtain output in the whole clock period ₂And corresponding bias structure, at φ ₁Phase, φ ₂Mutually, can obtain output current i ' by the current mirror effect _o=-i is simultaneously by selecting suitable T ₂Breadth length ratio can realize that the calibration of electric current (is that any electric current can be expressed as reference current i _oMultiply by a fixed coefficient, this coefficient depends on corresponding transistor channel breadth length ratio).In Fig. 2, T ₂, T ₁The ratio that wide raceway groove length compares is a, then i ' _o=-ai _o

Switched current memory cells so that Fig. 2 provides can construct various practical circuits such as delayer, integrator, differentiator and biquad filter joint easily.

2), according to electric current calibration normalization transconductance value.

The mutual conductance of desirable metal-oxide-semiconductor $g_m=\frac{W{u}_n{C}_{\mathrm{ox}}}{L}(V_{\mathrm{GS}}-V_T)=a\&CenterDot;u_n{C}_{\mathrm{ox}}(V_{\mathrm{GS}}-V_T),$ C _OxBe memory transistor gate zoneofoxidation unit-area capacitance, u _nBe electron mobility, V _GsBe gate source voltage, V _TBe the raceway groove threshold voltage, under the condition that manufacturing process is determined, these parameters all are constants, therefore can adopt transistor channel breadth length ratio a as the normalization transconductance value.

Sampling input transistors T1 transconductance value is arbitrarily, and other transistor normalization mutual conductances are carried out assignment according to the electric current calibration.

6 rank low-pass filters of the Chebyshev's response that constitutes with biquadratic joint below ripples such as () 0.5dB are that example describes, and adopt the clock frequency of 20MHz, its-3dB is 5MHz by frequency.Because the electric current calibration coefficient (breadth length ratio W/L) of capacity ratio in the switching capacity filter and switching current counter element has direct corresponding relation, can be by three biquadratic joint switching capacity topological structure transition structure Switched-Current Filter.First step selector switch electric capacity biquadratic joint transition function is:

$H\left(z\right)=\frac{x_o\left(z\right)}{x\left(z\right)}=-\frac{(a_5+a_6)z^2+(a_1{a}_3-2a_6-a_5)z+a_6}{(1+a_4)z^2+(a_2{a}_3-a_4-2)\text{z+1}}$

Topological structure such as Fig. 3:

Its transmission equation is as follows:

$i_A\left(z\right)=-\frac{a_2{i}_o\left(z\right)}{1-z^{-1}}-\frac{a_1{i}_{\mathrm{IN}}\left(z\right)}{1-z^{-1}}$

$i_o\left(z\right)=\frac{a_3}{1+a_4}\frac{z^{-1}}{1-\frac{z^{-1}}{1+a_4}}{i}_A\left(z\right)-\frac{a_5}{1+a_4}\frac{1}{1-\frac{z^{-1}}{1+a_4}}{i}_{\mathrm{IN}}\left(z\right)$

$-\frac{a_6}{1+a_4}\frac{1-z^{-1}}{1-\frac{z^{-1}}{1+a_4}}{i}_{\mathrm{IN}}\left(z\right)$

I wherein _A(z) be the output current of first integrator (A part among the figure), i _o(z) be output end current, i _IN(z) be the input end electric current.Adopt basic integrator structure to constitute switching current biquadratic joint as shown in Figure 4 in conjunction with top two formulas.

On the other hand, general s-territory building blocks of biquadratic transfer function is as follows:

$H\left(s\right)=\frac{x_o\left(s\right)}{x\left(s\right)}=\frac{k_2{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="A20081003131300171.png,A20081003131300191.png"\; state="\{\{state\}\}">s</figure-callout>}}^2+k_{1}s+k_0}{{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="A20081003131300171.png,A20081003131300191.png"\; state="\{\{state\}\}">s</figure-callout>}}^2+\frac{{\mathrm{\&omega;}}_0}{Q}s+{{\mathrm{\&omega;}}_0}^2}$

In the formula, x (s) and x _o(s) be input and output signal (voltage, electric current etc.), k ₀, k ₁And k ₂Be constant, ω ₀With Q be pole frequency and quality factor.With bilinearity z conversion s → 2 (1-z ^-1)/[T (1+z ^-1)] be used for formula and obtain

$H\left(z\right)=\frac{\left[\frac{4{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="A20081003131300171.png,A20081003131300191.png"\; state="\{\{state\}\}">k</figure-callout>}}_2+2k_{1}T+k_0{T}^2}{X}\right]z^2+\left[\frac{2k_0{T}^2-8k_2}{X}\right]z+\left[\frac{4k_2-2k_{1}T+k_0{T}^2}{X}\right]}{\left[\frac{{\mathrm{\&omega;}}_0{\mathrm{<figure-callout\; id="2"\; label="T"\; filenames="A20081003131300171.png,A20081003131300191.png"\; state="\{\{state\}\}">T</figure-callout>}}^2+\frac{2{\mathrm{\&omega;}}_{0}T}{Q}+4}{X}\right]z^2+\left[\frac{2{\mathrm{\&omega;}}_0{T}^2-8}{X}\right]z+1}$

In the formula

$X={\mathrm{\&omega;}}_0{T}^2-\frac{2{\mathrm{\&omega;}}_{0}T}{Q}+4$

Coefficient of comparisons,

$a_6=\frac{4k_2-2k_{1}T+k_0{T}^2}{X}$

$a_5=\frac{4k_{1}T}{X}$

$a_4=\frac{4{\mathrm{\&omega;}}_{0}T}{\mathrm{QX}}$

$a_2{a}_3=\frac{4{\mathrm{\&omega;}}_0^2{T}^2}{X}$

$a_1{a}_3=\frac{4k_0{T}^2}{X}$

Like this, if select coefficient can realize the bilinearity z conversion of biquadratic function according to above 5 formulas.The first step of numerical Design is to select the normalized multinomial coefficient of 6 rank Chebyshevs (0.5dB ripple) low-pass filter from the Design of Filter form.They are expressed as with the factorization form

$H\left(s\right)=\frac{n_1}{({\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="A20081003131300171.png,A20081003131300191.png"\; state="\{\{state\}\}">s</figure-callout>}}^2+m_{1}s+n_1)}\frac{n_2}{({\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="A20081003131300171.png,A20081003131300191.png"\; state="\{\{state\}\}">s</figure-callout>}}^2+m_{2}s+n_2)}\frac{n_3}{({\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="A20081003131300171.png,A20081003131300191.png"\; state="\{\{state\}\}">s</figure-callout>}}^2+m_{3}s+n_3)}$

Coefficient provides (known conditions) in subordinate list 1.

The Coefficient m of the biquadratic factor of subordinate list 1:6 rank 0.5dB ripple Chebyshev lowpass function and n (ω c=1.041029rad s ^-1)

Response+0.5dB and-3dB is by angular frequency 1.041029rads ^-1On peak value appears.To have the wave filter of 5MHz in order designing, biquadratic must to be saved the pre-warpage frequency of coefficient to determining of the factor by following formula by frequency ${\mathrm{\&omega;}}_p=\frac{2}{T}\tan \frac{\mathrm{\&omega;<figure-callout\; id="2"\; label="T"\; filenames="A20081003131300171.png,A20081003131300191.png"\; state="\{\{state\}\}">T</figure-callout>}}{2}$ Calibration, this is to be produced by bilinearity z conversion because of the frequency warpage.

In this example, ω=10 π * 10 ⁶s ^-1(corresponding to 5MHz) and T=0.05 * 10 ^-6S (corresponding to the clock frequency of 20MHz) calculates ω _p=40 * 10 ⁶s ^-1(ω _p=2 π f _pEqual 6.3662MHz).Then according to following formula calibration constant:

$m_p=\left[\frac{{\mathrm{\&omega;}}_p}{1.041029}\right]m$

$n_p=\left[\frac{{\mathrm{\&omega;}}_p}{1.041029}\right]n$

M in the formula _pAnd n _pBe respectively the ω that is applied to be used for derive the pre-warpage prototype of Switched-Current Filter ₀/ Q and ω ₀Calibration coefficient.And then in order to produce peak value in the response that 0dB occurs, the gain of establishing first segment is-0.5dB (0.9406).Subordinate list 2 has provided the calibration parameter, because the normalized multinomial coefficient molecule of 6 rank chebyshev low-pass filters has only constant term, therefore only provides k ₀Value, k ₁k ₂Be 0.

Subordinate list 2: calibration and pre-warpage filter parameter (S ^-1)

Utilize a then ₁A ₆The formula expression formula is calculated the sampled data filter coefficient.It the results are shown in subordinate list 3.Utilize this table and Fig. 4 and Fig. 5 can constitute the design wave filter.

Subordinate list 3: data filter coefficient and corresponding transistor normalized parameter (the transistor correspondence among the transistor AND gate Fig. 5 in the table)

Sampling input transistors T ₁Transconductance value is arbitrarily, can set and be normalized to 1, and other transistor normalization mutual conductances are carried out assignment according to subordinate list 3.(preamble illustrates: the sampled data filter coefficient can be realized that promptly the electric current scaled values because the transistor transconductance value becomes the constant proportionate relationship with the breadth length ratio value, thereby can be determined the normalized value of mutual conductance thus by the breadth length ratio of transistor channel)

3), the normalization transconductance value that calibration is calculated according to electric current, the transistor growth technique of identical normalization transconductance value is consistent, the form that produces error or accident defect is also with unanimity, thereby can press normalization transconductance value group by switching transistor, identical normalization transconductance value transistor is a group.

4), calculate group parameters about the sensitivity of circuit performance parameters, absolute or statistic bias.

Because switching current is a kind of technology of complete compatible with digital CMOS technology, it only adopts the metal-oxide-semiconductor forming circuit, obtains switch, mutual conductance and current source by the channel width that changes metal-oxide-semiconductor.For obtaining the transmission response of designing requirement, transistorized area ratio at different levels must be strict consistent with the electric current scaled values of calculating.Selecting the sampling hold circuit transistor normalization transconductance value of input end is 1, and other transistor normalization mutual conductances are carried out assignment according to the electric current calibration.All switching transistor normalization mutual conductances are divided into groups by identical value.Sensitivity be circuit performance with a kind of measurement that circuit component values changes, be circuit element parameter x _iVariation is to circuit transmission performance parameter node voltage E _iInfluence.According to the method for analyzing general cycle switch linear circuit, under the ac small signal condition, adopt the node analysis method, thus the correlation properties of solution node voltage matrix and adjoint matrix analysis circuit thereof.For the Switched-Current Circuit network that a switch periods is T, its each switch periods is divided into N phase again, and each phase element effect once.The grid source resistance R of MOS transistor for example _Gs, under the identical situation of resistance, two different effects are arranged, one is to lead as electricity, another is as the mutual conductance of input and output during different phase places.Therefore to be this node voltage to the derivative of component value go out the derivative sum of present worth to all these of this element to node voltage, so node voltage E _i(z) the sensitivity expression formula to parameter x (z) is:

$S_x^{E_i}=\frac{x}{E_i}\underset{m=1}{\overset{f}{\mathrm{\&Sigma;}}}\underset{k=1}{\overset{f}{\mathrm{\&Sigma;}}}\underset{l=1}{\overset{f}{\mathrm{\&Sigma;}}}\frac{{\&PartialD;E}_{i,\mathrm{mk}}}{{\&PartialD;x}_l}$

M=1 wherein, 2...f is an output phase, k=1,2...f are input phase, x _l(z) be parameter x (2) during phase place 1.

Node voltage E _{L, mk}(z) for the mutual conductance G of the input branch road a that is operated in out of phase with output branch road b _Mab(z) sensitivity is:

$S_{G_{\mathrm{mab}}}^{E_i}=\frac{G_{\mathrm{mab}}}{E_i}\underset{m=1}{\overset{f}{\mathrm{\&Sigma;}}}\underset{k=1}{\overset{f}{\mathrm{\&Sigma;}}}\underset{l=1}{\overset{f}{\mathrm{\&Sigma;}}}{V}_{a,\mathrm{lk}}{\hat{V}}_{b,\mathrm{lm}}$

V in the formula _{A, lk}Be the voltage on the branch road a in phase place l, its input service is at phase place k,

It is the corresponding voltage in the adjoint network.After calculating sensitivity, under the condition of given mutual conductance stochastic error, can further calculate statistic bias, add or deduct deviation from typical curve and just can obtain error margin.The error of calculating with sensitivity analysis is a statistic bias, is example with the stochastic error of x (z) 5%, parameter E _i(z) the maximum tolerance deviation to component parameters x (z) is:

$\mathrm{\&Delta;}\left|E_i\left(z\right)\right|=0.05\&times;8.686\sqrt{\underset{i}{\mathrm{\&Sigma;}}{\left(\mathrm{Re}{S}_{G_{\mathrm{mi}}}^{E_i\left(z\right)}\right)}^2}$

Wherein 0.05 is the stochastic error of given group's device parameters, the 0.868th, and the db-loss constant if need not then can remove in the decibel expression.

With one 6 rank switching current chebyshev low-pass filter (Fig. 5) is that example is calculated, and establishing cutoff frequency is 5MHz, and getting clock frequency according to 1: 4 ratio is 20MHz, ripple 0.5dB in the band.Set each transistorized breadth length ratio according to the pre-warp line of biquadratic joint factor pair by the calibration of frequency, the simulated response of acquisition as shown in Figure 6.Can calculate associated sensitivity and statistic bias by formula.

5), add or deduct deviation and just can obtain error margin from typical curve.

Typical curve adds or deduct deviation just can obtain error margin.Fig. 6 (a) is that the normalization transconductance value is the gain tolerance bound that group's metal-oxide-semiconductor of 0.8577 calculates under 1% and 5% stochastic error condition respectively (b).

The system mismatch error of the wide length of transistor that produces for the diffusion of analysis process and plate-making technology is to the influence of circuit, the mutual conductance normalized value is that the transistor of 0.8577 group is an example in the above example, get positive and negative about 15% stochastic error respectively, calculate relative sensitivity value and the deviation of circuit under the mismatch situation.As seen from Figure 7, because the electric current calibration error that mismatch causes will have a strong impact on the relative deviation value of circuit, no matter error is positive and negative, the relative deviation of wave filter all is higher than nominal value significantly.And for the table 3a ₁The class coefficient is that the trickleer as can be seen forward mismatch (＜10%) of the sensitivity analysis (Fig. 8) of group's (being made as a group) of 1.984 is less to the value influence of sensitivity, claim linear decline, but it is obvious to be higher than 10% back change of sensitivity, and sensitivity value of real part and nominal value gap that the deviation of pre-negative value is obtained are obvious.

Deduct gain tolerance upper and lower limit that the absolute deviation value that forms thus obtains as shown in Figure 9 with standard gain, with the increasing of forward mismatch, the tolerance lower limit that calculates exceeds the nominal lower limit value and descends gradually, and oppositely the tolerance lower limit distortion that obtains of mismatch is obvious.

Claims (3)

1, a kind of Switched-Current Circuit tolerance based on group's transconductance sensitivity is determined method, it is characterized in that, may further comprise the steps:

1) electric current calibration: with the switched current memory cells is the base configuration Switched-Current Circuit, calculates the transistor channel breadth length ratio, realizes the calibration of electric current;

2), according to electric current calibration normalization transconductance value: the sampling hold circuit transistor transconductance value with input end is a benchmark, and other transistor normalization transconductance value are carried out assignment according to the electric current calibration;

3), switching transistor is carried out group by the normalization transconductance value: promptly the standard that is made as a group according to the transistor of identical normalization transconductance value is divided into groups all transistors;

4), calculate sensitivity and the deviation of group parameters about circuit performance parameters;

5), add or deduct deviation and obtain error margin from typical curve.

2, a kind of Switched-Current Circuit tolerance based on group's transconductance sensitivity as claimed in claim 1 is determined method, it is characterized in that, described Switched-Current Circuit is delayer, integrator, differentiator or biquad filter circuit.

3, a kind of Switched-Current Circuit tolerance based on group's transconductance sensitivity as claimed in claim 1 or 2 is determined method, it is characterized in that described step 4) is:

Computing node voltage E _{I, mk}(z) for the mutual conductance G of the input branch road a that is operated in out of phase with output branch road b _Mab(z) sensitivity is:

$S_{G_{\mathrm{mab}}}^{E_i}=\frac{G_{\mathrm{mab}}}{E_i}\underset{m=1}{\overset{f}{\mathrm{\&Sigma;}}}\underset{k=1}{\overset{f}{\mathrm{\&Sigma;}}}\underset{l=1}{\overset{f}{\mathrm{\&Sigma;}}}{V}_{a,\mathrm{lk}}{\hat{V}}_{b,\mathrm{lm}}$

V in the formula _{A, lk}Be the voltage on the branch road a in phase place l, its input service is at phase place k,

It is the corresponding voltage in the adjoint network;

Parameter E _l(z) the maximum tolerance deviation to component parameters x (z) is:

$\mathrm{\&Delta;}\left|E_i\left(z\right)\right|=P_0\&times;\sqrt{\underset{i}{\mathrm{\&Sigma;}}{\left(\mathrm{Re}{S}_{G_{\mathrm{mi}}}^{E_i\left(z\right)}\right)}^2}$ Or

$\mathrm{\&Delta;}\left|E_i\left(z\right)\right|=P_0\&times;8.686\sqrt{\underset{i}{\mathrm{\&Sigma;}}{\left(\mathrm{Re}{S}_{G_{\mathrm{mi}}}^{E_i\left(z\right)}\right)}^2}---\left(\mathrm{dB}\right)$

P wherein ₀Be the stochastic error of a given device parameters x of group (z), 0.868 is the db-loss constant.

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